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authorAdam <you@example.com>2020-05-17 05:51:50 +0200
committerAdam <you@example.com>2020-05-17 05:51:50 +0200
commite611b132f9b8abe35b362e5870b74bce94a1e58e (patch)
treea5781d2ec0e085eeca33cf350cf878f2efea6fe5 /private/ntos/fw/ppc
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Diffstat (limited to '')
-rw-r--r--private/ntos/fw/ppc/arceisa.h547
-rw-r--r--private/ntos/fw/ppc/debug.h7
-rw-r--r--private/ntos/fw/ppc/dmaregs.h207
-rw-r--r--private/ntos/fw/ppc/eisastr.h37
-rw-r--r--private/ntos/fw/ppc/fwp.h668
-rw-r--r--private/ntos/fw/ppc/fwstring.h131
-rw-r--r--private/ntos/fw/ppc/inc.h883
-rw-r--r--private/ntos/fw/ppc/ioaccess.h79
-rw-r--r--private/ntos/fw/ppc/iodevice.h378
-rw-r--r--private/ntos/fw/ppc/j4reset.h115
-rw-r--r--private/ntos/fw/ppc/jxfwhal.h94
-rw-r--r--private/ntos/fw/ppc/jxvideo.h158
-rw-r--r--private/ntos/fw/ppc/jzsetup.h155
-rw-r--r--private/ntos/fw/ppc/jzstring.h101
-rw-r--r--private/ntos/fw/ppc/kbdmouse.h149
-rw-r--r--private/ntos/fw/ppc/led.h125
-rw-r--r--private/ntos/fw/ppc/monitor.h159
-rw-r--r--private/ntos/fw/ppc/oli2msft.h39
-rw-r--r--private/ntos/fw/ppc/selfmap.h335
-rw-r--r--private/ntos/fw/ppc/selftest.h224
-rw-r--r--private/ntos/fw/ppc/sonictst.h246
21 files changed, 4837 insertions, 0 deletions
diff --git a/private/ntos/fw/ppc/arceisa.h b/private/ntos/fw/ppc/arceisa.h
new file mode 100644
index 000000000..df162ec7a
--- /dev/null
+++ b/private/ntos/fw/ppc/arceisa.h
@@ -0,0 +1,547 @@
+// -----------------------------------------------------------------------------
+//
+// Copyright (c) 1992 Olivetti
+//
+// File: arceisa.h
+//
+// Description: ARC-EISA Addendum Structures and Defines.
+//
+// -----------------------------------------------------------------------------
+
+
+//
+// Define the EISA firmware entry points
+//
+
+typedef enum _EISA_FIRMWARE_ENTRY
+ {
+ ProcessEOIRoutine,
+ TestIntRoutine,
+ RequestDMARoutine,
+ AbortDMARoutine,
+ GetDMAStatusRoutine,
+ DoLockRoutine,
+ RequestBusMasterRoutine,
+ ReleaseBusMasterRoutine,
+ RequestCpuAccessToBusRoutine,
+ ReleaseCpuAccessToBusRoutine,
+ FlushCacheRoutine,
+ InvalidateCacheRoutine,
+ ReservedRoutine,
+ BeginCriticalSectionRoutine,
+ EndCriticalSectionRoutine,
+ GenerateToneRoutine,
+ FlushWriteBuffersRoutine,
+ YieldRoutine,
+ StallProcessorRoutine,
+ MaximumEisaRoutine
+ } EISA_FIRMWARE_ENTRY;
+
+
+//
+// Define EISA interrupt functions
+//
+
+typedef
+ARC_STATUS
+(*PEISA_PROCESS_EOI_RTN)
+ (
+ IN ULONG BusNumber,
+ IN USHORT IRQ
+ );
+
+typedef
+BOOLEAN_ULONG
+(*PEISA_TEST_INT_RTN)
+ (
+ IN ULONG BusNumber,
+ IN USHORT IRQ
+ );
+
+//
+// Define EISA DMA functions
+//
+
+typedef enum _DMA_TRANSFER_TYPE
+ {
+ DmaVerify,
+ DmaWrite,
+ DmaRead,
+ DmaMaxType
+ } DMA_TRANSFER_TYPE, *PDMA_TRANSFER_TYPE;
+
+typedef enum _DMA_TRANSFER_MODE
+ {
+ DmaDemand,
+ DmaSingle,
+ DmaBlock,
+ DmaCascade,
+ DmaMaxMode
+ } DMA_TRANSFER_MODE, *PDMA_TRANSFER_MODE;
+
+typedef enum _DMA_TIMING_MODE
+ {
+ DmaIsaCompatible,
+ DmaTypeA,
+ DmaTypeB,
+ DmaBurst,
+ DmaMaxTiming
+ } DMA_TIMING_MODE, *PDMA_TIMING_MODE;
+
+typedef enum _DMA_ADDRESSING_MODE
+ {
+ Dma8Bit,
+ Dma16sBit,
+ Dma32Bit,
+ Dma16Bit,
+ DmaMaxAddressing
+ } DMA_ADDRESSING_MODE, *PDMA_ADDRESSING_MODE;
+
+typedef struct _DMA_TRANSFER
+ {
+ DMA_TRANSFER_MODE TransferMode;
+ ULONG ChannelNumber;
+ DMA_TRANSFER_TYPE TransferType;
+ ULONG Size;
+ PVOID Buffer;
+ } DMA_TRANSFER, *PDMA_TRANSFER;
+
+typedef struct _DMA_STATUS
+ {
+ BOOLEAN_ULONG CompleteTransfer;
+ ULONG ByteTransferred;
+ } DMA_STATUS, *PDMA_STATUS;
+
+typedef
+ARC_STATUS
+(*PEISA_REQ_DMA_XFER_RTN)
+ (
+ IN ULONG BusNumber,
+ IN PDMA_TRANSFER pDmaTransfer
+ );
+
+typedef
+ARC_STATUS
+(*PEISA_ABORT_DMA_RTN)
+ (
+ IN ULONG BusNumber,
+ IN PDMA_TRANSFER pDmaTransfer
+ );
+
+typedef
+ARC_STATUS
+(*PEISA_DMA_XFER_STATUS_RTN)
+ (
+ IN ULONG BusNumber,
+ IN PDMA_TRANSFER pDmaTransfer,
+ OUT PDMA_STATUS pDmaStatus
+ );
+
+//
+// Define EISA lock function
+//
+
+typedef enum _EISA_LOCK_OPERATION
+ {
+ Exchange,
+ LockMaxOperation
+ } EISA_LOCK_OPERATION;
+
+
+typedef enum _SEMAPHORE_SIZE
+ {
+ ByteSemaphore,
+ HalfWordSemaphore,
+ WordSemaphore,
+ MaxSemaphore
+ } SEMAPHORE_SIZE;
+
+typedef
+ARC_STATUS
+(*PEISA_LOCK_RTN)
+ (
+ IN ULONG BusNumber,
+ IN EISA_LOCK_OPERATION Operation,
+ IN PVOID Semaphore,
+ IN SEMAPHORE_SIZE SemaphoreSize,
+ IN PVOID OperationArgument,
+ OUT PVOID OperationResult
+ );
+
+//
+// Define EISA bus master functions.
+//
+
+typedef enum _BUS_MASTER_TRANSFER_TYPE
+ {
+ BusMasterWrite,
+ BusMasterRead,
+ BusMasterMaxType
+ } BUS_MASTER_TRANSFER_TYPE, *PBUS_MASTER_TRANSFER_TYPE;
+
+typedef enum _ADDRESS_RESTRICTION
+ {
+ LimitNone,
+ Limit16Mb,
+ Limit4Gb,
+ LimitMax
+ } ADDRESS_RESTRICTION, *PADDRESS_RESTRICTION;
+
+typedef struct _BUS_MASTER_TRANSFER
+ {
+ ADDRESS_RESTRICTION Limit;
+ ULONG SlotNumber;
+ BUS_MASTER_TRANSFER_TYPE TransferType;
+ ULONG Size;
+ PVOID Buffer;
+ } BUS_MASTER_TRANSFER, *PBUS_MASTER_TRANSFER;
+
+typedef
+ARC_STATUS
+(*PEISA_REQUEST_BUS_MASTER_RTN)
+ (
+ IN ULONG BusNumber,
+ IN PBUS_MASTER_TRANSFER pBusMasterTransfer,
+ OUT ULONG *TranslateBufferAddress
+ );
+
+typedef
+ARC_STATUS
+(*PEISA_RELEASE_BUS_MASTER_RTN)
+ (
+ IN ULONG BusNumber,
+ IN PBUS_MASTER_TRANSFER pBusMasterTransfer,
+ IN ULONG TranslateBufferAddress
+ );
+
+//
+// Define EISA slave functions
+//
+
+typedef struct _SLAVE_TRANSFER
+ {
+ ULONG SlotNumber;
+ ULONG Size;
+ ULONG Buffer;
+ } SLAVE_TRANSFER, *PSLAVE_TRANSFER;
+
+typedef
+ARC_STATUS
+(*PEISA_REQUEST_CPU_TO_BUS_ACCESS_RTN)
+ (
+ IN ULONG BusNumber,
+ IN PSLAVE_TRANSFER pSlaveTransfer,
+ OUT PVOID *TranslatedBufferAddress
+ );
+
+typedef
+ARC_STATUS
+(*PEISA_RELEASE_CPU_TO_BUS_ACCESS_RTN)
+ (
+ IN ULONG BusNumber,
+ IN PSLAVE_TRANSFER pSlaveTransfer,
+ IN PVOID TranslateBufferAddress
+ );
+
+typedef
+VOID
+(*PEISA_FLUSH_CACHE_RTN)
+ (
+ IN PVOID Address,
+ IN ULONG Length
+ );
+
+typedef
+VOID
+(*PEISA_INVALIDATE_CACHE_RTN)
+ (
+ IN PVOID Address,
+ IN ULONG Length
+ );
+
+typedef
+VOID
+(*PEISA_RESERVED_RTN)
+ (
+ VOID
+ );
+
+typedef
+VOID
+(*PEISA_BEGIN_CRITICAL_SECTION_RTN)
+ (
+ VOID
+ );
+
+typedef
+VOID
+(*PEISA_END_CRITICAL_SECTION_RTN)
+ (
+ VOID
+ );
+
+typedef
+ARC_STATUS
+(*PEISA_GENERATE_TONE_RTN)
+ (
+ IN ULONG Frequency,
+ IN ULONG Duration
+ );
+
+typedef
+VOID
+(*PEISA_FLUSH_WRITE_BUFFER_RTN)
+ (
+ VOID
+ );
+
+typedef
+BOOLEAN_ULONG
+(*PEISA_YIELD_RTN)
+ (
+ VOID
+ );
+
+typedef
+VOID
+(*PEISA_STALL_PROCESSOR_RTN)
+ (
+ IN ULONG Duration
+ );
+
+
+//
+// Define EISA callback vectors prototypes.
+//
+
+ARC_STATUS
+EisaProcessEndOfInterrupt
+ (
+ IN ULONG BusNumber,
+ IN USHORT Irq
+ );
+
+BOOLEAN_ULONG
+EisaTestEisaInterrupt
+ (
+ IN ULONG BusNumber,
+ IN USHORT Irq
+ );
+
+ARC_STATUS
+EisaRequestEisaDmaTransfer
+ (
+ IN ULONG BusNumber,
+ IN PDMA_TRANSFER pDmaTransfer
+ );
+
+ARC_STATUS
+EisaAbortEisaDmaTransfer
+ (
+ IN ULONG BusNumber,
+ IN PDMA_TRANSFER pDmaTransfer
+ );
+
+ARC_STATUS
+EisaGetEisaDmaTransferStatus
+ (
+ IN ULONG BusNumber,
+ IN PDMA_TRANSFER pDmaTransfer,
+ OUT PDMA_STATUS pDmaStatus
+ );
+
+ARC_STATUS
+EisaDoLockedOperation
+ (
+ IN ULONG BusNumber,
+ IN EISA_LOCK_OPERATION Operation,
+ IN PVOID Semaphore,
+ IN SEMAPHORE_SIZE SemaphoreSize,
+ IN PVOID OperationArgument,
+ OUT PVOID OperationResult
+ );
+
+ARC_STATUS
+EisaRequestEisaBusMasterTransfer
+ (
+ IN ULONG BusNumber,
+ IN PBUS_MASTER_TRANSFER pBusMasterTransfer,
+ OUT ULONG *TranslatedBufferAddress
+ );
+
+ARC_STATUS
+EisaReleaseEisaBusMasterTransfer
+ (
+ IN ULONG BusNumber,
+ IN PBUS_MASTER_TRANSFER pBusMasterTransfer,
+ IN ULONG TranslatedBufferAddress
+ );
+
+ARC_STATUS
+EisaRequestCpuAccessToEisaBus
+ (
+ IN ULONG BusNumber,
+ IN PSLAVE_TRANSFER pSlaveTransfer,
+ OUT PVOID *TranslatedAddress
+ );
+
+ARC_STATUS
+EisaReleaseCpuAccessToEisaBus
+ (
+ IN ULONG BusNumber,
+ IN PSLAVE_TRANSFER pSlaveTransfer,
+ IN PVOID TranslatedAddress
+ );
+
+VOID
+EisaFlushCache
+ (
+ IN PVOID Address,
+ IN ULONG Length
+ );
+
+VOID
+EisaInvalidateCache
+ (
+ IN PVOID Address,
+ IN ULONG Length
+ );
+
+VOID
+EisaBeginCriticalSection
+ (
+ IN VOID
+ );
+
+VOID
+EisaEndCriticalSection
+ (
+ IN VOID
+ );
+
+VOID
+EisaFlushWriteBuffers
+ (
+ VOID
+ );
+
+ARC_STATUS
+EisaGenerateTone
+ (
+ IN ULONG Frequency,
+ IN ULONG Duration
+ );
+
+BOOLEAN_ULONG
+EisaYield
+ (
+ VOID
+ );
+
+VOID
+EisaStallProcessor
+ (
+ IN ULONG Duration
+ );
+
+
+//
+// Define macros that call the EISA firmware routines indirectly through the
+// EISA firmware vector and provide type checking of argument values.
+//
+
+#define ArcEisaProcessEndOfInterrupt(BusNumber, IRQ) \
+ ((PEISA_PROCESS_EOI_RTN)(SYSTEM_BLOCK->Adapter0Vector[ProcessEOIRoutine])) \
+ ((BusNumber), (IRQ))
+
+#define ArcEisaTestEisaInterupt(BusNumber, IRQ) \
+ ((PEISA_TEST_INT_RTN)(SYSTEM_BLOCK->Adapter0Vector[TestIntRoutine])) \
+ ((BusNumber), (IRQ))
+
+#define ArcEisaRequestEisaDmaTransfer(BusNumber, pDmaTransfer) \
+ ((PEISA_REQ_DMA_XFER_RTN)(SYSTEM_BLOCK->Adapter0Vector[RequestDMARoutine])) \
+ ((BusNumber), (pDmaTransfer))
+
+#define ArcEisaAbortEisaDmaTransfer(BusNumber, pDmaTransfer) \
+ ((PEISA_ABORT_DMA_RTN)(SYSTEM_BLOCK->Adapter0Vector[AbortDMARoutine])) \
+ ((BusNumber), (pDmaTransfer))
+
+#define ArcEisaGetEisaDmaTransferStatus(BusNumber, pDmaTransfer, pDmaStatus) \
+ ((PEISA_DMA_XFER_STATUS_RTN)(SYSTEM_BLOCK->Adapter0Vector[GetDMAStatusRoutine])) \
+ ((BusNumber), (pDmaTransfer), (pDmaStatus))
+
+#define ArcEisaDoLockedOperation(BusNumber, Operation, Semaphore, SemaphoreSize, OperationArgument, OperationResult) \
+ ((PEISA_LOCK_RTN)(SYSTEM_BLOCK->Adapter0Vector[DoLockRoutine])) \
+ ((BusNumber), (Operation), (Semaphore), (SemaphoreSize), (OperationArgument), (OperationResult))
+
+#define ArcEisaRequestEisaBusMasterTransferCPUAddressToBusAddress(BusNumber, pBusMasterTransfer, TranslateBufferAddress) \
+ ((PEISA_REQUEST_BUS_MASTER_RTN)(SYSTEM_BLOCK->Adapter0Vector[RequestBusMasterRoutine])) \
+ ((BusNumber), (pBusMasterTransfer), (TranslateBufferAddress))
+
+#define ArcEisaReleaseEisaBusMasterTransfer(BusNumber, pBusMasterTransfer, TranslateBufferAddress) \
+ ((PEISA_RELEASE_BUS_MASTER_RTN)(SYSTEM_BLOCK->Adapter0Vector[ReleaseBusMasterRoutine])) \
+ ((BusNumber), (pBusMasterTransfer), (TranslateBufferAddress))
+
+#define ArcEisaRequestCpuAccessToEisaBus(BusNumber, pSlaveTransfer, TranslatedBufferAddress) \
+ ((PEISA_REQUEST_CPU_TO_BUS_ACCESS_RTN)(SYSTEM_BLOCK->Adapter0Vector[RequestCpuAccessToBusRoutine])) \
+ ((BusNumber), (pSlaveTransfer), (TranslatedBufferAddress))
+
+#define ArcEisaReleaseCpuAccessToEisaBus(BusNumber, pSlaveTransfer, TranslatedBufferAddress) \
+ ((PEISA_RELEASE_CPU_TO_BUS_ACCESS_RTN)(SYSTEM_BLOCK->Adapter0Vector[ReleaseCpuAccessToBusRoutine])) \
+ ((BusNumber), (pSlaveTransfer), (TranslatedBufferAddress))
+
+#define ArcEisaFlushCache(Address, Length) \
+ ((PEISA_FLUSH_CACHE_RTN)(SYSTEM_BLOCK->Adapter0Vector[FlushCacheRoutine])) \
+ ((Address), (Length))
+
+#define ArcEisaInvalidateCache(Address, Length) \
+ ((PEISA_INVALIDATE_CACHE_RTN)(SYSTEM_BLOCK->Adapter0Vector[InvalidateCacheRoutine])) \
+ ((Address), (Length))
+
+#define ArcEisaBeginCriticalSection() \
+ ((PEISA_BEGIN_CRITICAL_SECTION_RTN)(SYSTEM_BLOCK->Adapter0Vector[BeginCriticalSectionRoutine]))()
+
+#define ArcEisaEndCriticalSection() \
+ ((PEISA_END_CRITICAL_SECTION_RTN)(SYSTEM_BLOCK->Adapter0Vector[EndCriticalSectionRoutine]))()
+
+#define ArcEisaGenerateTone() \
+ ((PEISA_GENERATE_TONE_RTN)(SYSTEM_BLOCK->Adapter0Vector[GenerateToneRoutine])) \
+ ((Freqency), (Duration))
+
+#define ArcEisaFlushWriteBuffers() \
+ ((PEISA_FLUSH_WRITE_BUFFER_RTN)(SYSTEM_BLOCK->Adapter0Vector[FlushWriteBuffersRoutine]))()
+
+#define ArcEisaYield() \
+ ((PEISA_YIELD_RTN)(SYSTEM_BLOCK->Adapter0Vector[YieldRoutine]))()
+
+#define ArcEisaStallProcessor(Duration) \
+ ((PEISA_STALL_PROCESSOR_RTN)(SYSTEM_BLOCK->Adapter0Vector[StallProcessorRoutine])) \
+ (Duration)
+
+
+//
+// General OMF defines
+//
+
+#define OMF_BLOCK_SIZE 512 // OMF block size in bytes
+#define OMF_MAX_SIZE (32*1024*1024) // max OMF size in bytes
+#define OMF_MAX_FILE_LEN ((16*1024*1024)/(1<<WORD_2P2)) // (16 Mbytes max)/4
+#define OMF_MAX_FILE_LINK ((16*1024*1024)/(1<<WORD_2P2)) // (16 Mbytes max)/4
+#define OMF_ID_1ST 0x55 // 1st OMF ID
+#define OMF_ID_2ND 0x00 // 2nd OMF ID
+#define OMF_ID_3RD 0xAA // 3rd OMF ID
+#define OMF_ID_4TH 0xFF // 4th OMF ID
+#define OMF_FILE_NAME_LEN 12 // 12 chars
+
+//
+// Define OMF FAT file name structure
+//
+typedef struct _OMF_FAT_FILE_NAME
+ {
+ CHAR ProductId[7];
+ CHAR Version;
+ CHAR Dot;
+ CHAR Extension[2];
+ CHAR Revision;
+ } OMF_FAT_FILE_NAME, *POMF_FAT_FILE_NAME;
+
diff --git a/private/ntos/fw/ppc/debug.h b/private/ntos/fw/ppc/debug.h
new file mode 100644
index 000000000..d72c62146
--- /dev/null
+++ b/private/ntos/fw/ppc/debug.h
@@ -0,0 +1,7 @@
+
+#if OMF_DEBUG==TRUE
+ #define PRINTDBG(x) FwPrint(x); \
+ FwStallExecution(50*1000);
+#else
+ #define PRINTDBG(x) //
+#endif
diff --git a/private/ntos/fw/ppc/dmaregs.h b/private/ntos/fw/ppc/dmaregs.h
new file mode 100644
index 000000000..c78e63cfc
--- /dev/null
+++ b/private/ntos/fw/ppc/dmaregs.h
@@ -0,0 +1,207 @@
+/*++
+
+Copyright (c) 1990 Microsoft Corporation
+
+Module Name:
+
+ dmaregs.h
+
+Abstract:
+
+ This module defines the offsets of the MCTADR registers to allow
+ access to them from assembly code.
+
+ Register names correspond to the ones in the structure DMA_REGISTERS
+ declared in jazzdma.h
+
+Author:
+
+ Lluis Abello 6-May-91
+
+Revision History:
+
+ Lluis Abello 1-Apr-93 Added DUO registers
+
+--*/
+#ifndef _DMAREGS
+#define _DMAREGS
+
+#ifndef DUO
+//
+// DMA REGISTER OFFSETS
+//
+#define DmaConfiguration 0x000
+#define DmaRevisionLevel 0x008
+#define DmaInvalidAddress 0x010
+#define DmaTranslationBase 0x018
+#define DmaTranslationLimit 0x020
+#define DmaTranslationInvalidate 0x028
+#define DmaCacheMaintenance 0x030
+#define DmaRemoteFailedAddress 0x038
+#define DmaMemoryFailedAddress 0x040
+#define DmaPhysicalTag 0x048
+#define DmaLogicalTag 0x050
+#define DmaByteMask 0x058
+#define DmaBufferWindowLow 0x060
+#define DmaBufferWindowHigh 0x068
+#define DmaRemoteSpeed0 0x070
+#define DmaRemoteSpeed1 0x078
+#define DmaRemoteSpeed2 0x080
+#define DmaRemoteSpeed3 0x088
+#define DmaRemoteSpeed4 0x090
+#define DmaRemoteSpeed5 0x098
+#define DmaRemoteSpeed6 0x0a0
+#define DmaRemoteSpeed7 0x0a8
+#define DmaRemoteSpeed8 0x0b0
+#define DmaRemoteSpeed9 0x0b8
+#define DmaRemoteSpeed10 0x0c0
+#define DmaRemoteSpeed11 0x0c8
+#define DmaRemoteSpeed12 0x0d0
+#define DmaRemoteSpeed13 0x0d8
+#define DmaRemoteSpeed14 0x0e0
+#define DmaRemoteSpeed15 0x0e8
+#define DmaParityDiagnosticLow 0x0f0
+#define DmaParityDiagnosticHigh 0x0f8
+#define DmaChannel0Mode 0x100
+#define DmaChannel0Enable 0x108
+#define DmaChannel0ByteCount 0x110
+#define DmaChannel0Address 0x118
+#define DmaChannel1Mode 0x120
+#define DmaChannel1Enable 0x128
+#define DmaChannel1ByteCount 0x130
+#define DmaChannel1Address 0x138
+#define DmaChannel2Mode 0x140
+#define DmaChannel2Enable 0x148
+#define DmaChannel2ByteCount 0x150
+#define DmaChannel2Address 0x158
+#define DmaChannel3Mode 0x160
+#define DmaChannel3Enable 0x168
+#define DmaChannel3ByteCount 0x170
+#define DmaChannel3Address 0x178
+#define DmaChannel4Mode 0x180
+#define DmaChannel4Enable 0x188
+#define DmaChannel4ByteCount 0x190
+#define DmaChannel4Address 0x198
+#define DmaChannel5Mode 0x1a0
+#define DmaChannel5Enable 0x1a8
+#define DmaChannel5ByteCount 0x1b0
+#define DmaChannel5Address 0x1b8
+#define DmaChannel6Mode 0x1c0
+#define DmaChannel6Enable 0x1c8
+#define DmaChannel6ByteCount 0x1d0
+#define DmaChannel6Address 0x1d8
+#define DmaChannel7Mode 0x1e0
+#define DmaChannel7Enable 0x1e8
+#define DmaChannel7ByteCount 0x1f0
+#define DmaChannel7Address 0x1f8
+#define DmaInterruptSource 0x200
+#define DmaErrortype 0x208
+#define DmaRefreshRate 0x210
+#define DmaRefreshCounter 0x218
+#define DmaSystemSecurity 0x220
+#define DmaInterruptInterval 0x228
+#define DmaIntervalTimer 0x230
+#define DmaInterruptAcknowledge 0x238
+
+#else
+//
+// MP_DMA register offsets for DUO.
+//
+#define DmaConfiguration 0x000
+#define DmaRevisionLevel 0x008
+#define DmaRemoteFailedAddress 0x010
+#define DmaMemoryFailedAddress 0x018
+#define DmaInvalidAddress 0x020
+#define DmaTranslationBase 0x028
+#define DmaTranslationLimit 0x030
+#define DmaTranslationInvalidate 0x038
+#define DmaChannelInterruptAcknowledge 0x040
+#define DmaLocalInterruptAcknowledge 0x048
+#define DmaEisaInterruptAcknowledge 0x050
+#define DmaTimerInterruptAcknowledge 0x058
+#define DmaIpInterruptAcknowledge 0x060
+#define DmaWhoAmI 0x070
+#define DmaNMISource 0x078
+#define DmaRemoteSpeed0 0x080
+#define DmaRemoteSpeed1 0x088
+#define DmaRemoteSpeed2 0x090
+#define DmaRemoteSpeed3 0x098
+#define DmaRemoteSpeed4 0x0A0
+#define DmaRemoteSpeed5 0x0A8
+#define DmaRemoteSpeed6 0x0B0
+#define DmaRemoteSpeed7 0x0B8
+#define DmaRemoteSpeed8 0x0C0
+#define DmaRemoteSpeed9 0x0C8
+#define DmaRemoteSpeed10 0x0D0
+#define DmaRemoteSpeed11 0x0D8
+#define DmaRemoteSpeed12 0x0E0
+#define DmaRemoteSpeed13 0x0E8
+#define DmaRemoteSpeed14 0x0F0
+#define DmaInterruptEnable 0x0F8
+#define DmaChannel0Mode 0x100
+#define DmaChannel0Enable 0x108
+#define DmaChannel0ByteCount 0x110
+#define DmaChannel0Address 0x118
+#define DmaChannel1Mode 0x120
+#define DmaChannel1Enable 0x128
+#define DmaChannel1ByteCount 0x130
+#define DmaChannel1Address 0x138
+#define DmaChannel2Mode 0x140
+#define DmaChannel2Enable 0x148
+#define DmaChannel2ByteCount 0x150
+#define DmaChannel2Address 0x158
+#define DmaChannel3Mode 0x160
+#define DmaChannel3Enable 0x168
+#define DmaChannel3ByteCount 0x170
+#define DmaChannel3Address 0x178
+#define DmaArbitrationControl 0x180
+#define DmaErrortype 0x188
+#define DmaRefreshRate 0x190
+#define DmaRefreshCounter 0x198
+#define DmaSystemSecurity 0x1A0
+#define DmaInterruptInterval 0x1A8
+#define DmaIntervalTimer 0x1B0
+#define DmaIpi 0x1B8
+#define DmaInterruptDiagnostic 0x1C0
+#define DmaEccDiagnostic 0x1C8
+#define DmaMemoryConfig0 0x1D0
+#define DmaMemoryConfig1 0x1D8
+#define DmaMemoryConfig2 0x1E0
+#define DmaMemoryConfig3 0x1E8
+#define IoCacheBufferBase 0x200
+#define DmaIoCachePhysicalTag0 0x400
+#define DmaIoCachePhysicalTag1 0x408
+#define DmaIoCachePhysicalTag2 0x410
+#define DmaIoCachePhysicalTag3 0x418
+#define DmaIoCachePhysicalTag4 0x420
+#define DmaIoCachePhysicalTag5 0x428
+#define DmaIoCachePhysicalTag6 0x430
+#define DmaIoCachePhysicalTag7 0x438
+#define DmaIoCacheLogicalTag0 0x440
+#define DmaIoCacheLogicalTag1 0x448
+#define DmaIoCacheLogicalTag2 0x450
+#define DmaIoCacheLogicalTag3 0x458
+#define DmaIoCacheLogicalTag4 0x460
+#define DmaIoCacheLogicalTag5 0x468
+#define DmaIoCacheLogicalTag6 0x470
+#define DmaIoCacheLogicalTag7 0x478
+#define DmaIoCacheLowByteMask0 0x480
+#define DmaIoCacheLowByteMask1 0x488
+#define DmaIoCacheLowByteMask2 0x490
+#define DmaIoCacheLowByteMask3 0x498
+#define DmaIoCacheLowByteMask4 0x4A0
+#define DmaIoCacheLowByteMask5 0x4A8
+#define DmaIoCacheLowByteMask6 0x4B0
+#define DmaIoCacheLowByteMask7 0x4B8
+#define DmaIoCacheHighByteMask0 0x4C0
+#define DmaIoCacheHighByteMask1 0x4C8
+#define DmaIoCacheHighByteMask2 0x4D0
+#define DmaIoCacheHighByteMask3 0x4D8
+#define DmaIoCacheHighByteMask4 0x4E0
+#define DmaIoCacheHighByteMask5 0x4E8
+#define DmaIoCacheHighByteMask6 0x4F0
+#define DmaIoCacheHighByteMask7 0x4F8
+
+#endif // DUO
+
+#endif //_DMAREGS
diff --git a/private/ntos/fw/ppc/eisastr.h b/private/ntos/fw/ppc/eisastr.h
new file mode 100644
index 000000000..5244d9ba4
--- /dev/null
+++ b/private/ntos/fw/ppc/eisastr.h
@@ -0,0 +1,37 @@
+
+//
+// Common strings.
+//
+extern PCHAR EISA_OK_MSG;
+extern PCHAR EISA_CRLF_MSG;
+extern PCHAR EISA_ERROR1_MSG;
+
+//
+// Eisa strings.
+//
+
+// ----------------------------------------------------------------------------
+// GLOBAL: EISA error messages
+// ----------------------------------------------------------------------------
+//
+// 1 2 3 4 5 6 7
+// 01234567890123456789012345678901234567890123456789012345678901234567890
+
+extern PCHAR EisaCfgMessages[];
+
+extern EISA_CHECKPOINT_INFO EisaCheckpointInfo[];
+
+extern PCHAR EISA_INIT_MSG;
+extern PCHAR EISA_BUS_MSG;
+extern PCHAR EISA_ERROR_SLOT_MSG;
+extern PCHAR EISA_HOT_NMI_MSG;
+extern PCHAR EISA_BUS_NUMBER_MSG;
+extern PCHAR EISA_NMI_NOT_FOUND_MSG;
+extern PCHAR EISA_PARITY_ERROR_MSG;
+extern PCHAR EISA_IO_CHECK_ERROR_MSG;
+extern PCHAR EISA_IO_CHECK_NOT_SUP_MSG;
+extern PCHAR EISA_IN_SLOT_MSG;
+extern PCHAR EISA_BUS_MASTER_MSG;
+extern PCHAR EISA_TIMEOUT_MSG;
+extern PCHAR EISA_TIMEOUT2_MSG;
+extern PCHAR EISA_SLAVE_TIMEOUT_MSG;
diff --git a/private/ntos/fw/ppc/fwp.h b/private/ntos/fw/ppc/fwp.h
new file mode 100644
index 000000000..f7d09eb4a
--- /dev/null
+++ b/private/ntos/fw/ppc/fwp.h
@@ -0,0 +1,668 @@
+/*++
+
+Copyright (c) 1991 Microsoft Corporation
+
+Module Name:
+
+ fwp.h
+
+Abstract:
+
+ This module contains extensions to the firmware.h header file.
+
+Author:
+
+ David M. Robinson (davidro) 29-Aug-1991
+
+Revision History:
+
+--*/
+
+#ifndef _FWP_
+#define _FWP_
+
+#include "bldr.h"
+#include "firmware.h"
+#include "kbdmouse.h"
+#ifndef DUO
+#include "jazzdef.h"
+#include "jazzprom.h"
+#ifndef _PPC_
+#include "jazzdma.h"
+#else
+#include "ppcdef.h"
+#endif
+#else
+#include "duodef.h"
+#include "duoprom.h"
+#include "duodma.h"
+#endif
+
+
+//
+// TEMPTEMP Temporary defines.
+//
+
+#define SECONDARY_CACHE_SIZE (1 << 20)
+#define SECONDARY_CACHE_INVALID 0x0
+#define SECONDARY_CACHE_DIRTY_EXCLUSIVE 0x5
+#define TAGLO_SSTATE 0xA
+
+//
+// Current version and revision numbers.
+//
+
+#define ARC_VERSION 1
+#define ARC_REVISION 2
+
+
+//
+// Define the firmware vendor specific entry point numbers.
+//
+
+typedef enum _VENDOR_ENTRY {
+ AllocatePoolRoutine,
+ StallExecutionRoutine,
+ PrintRoutine,
+ SetDisplayAttributesRoutine,
+ OutputCharacterRoutine,
+ ScrollVideoRoutine,
+ BootRestartRoutine,
+ MaximumVendorRoutine
+ } VENDOR_ENTRY;
+
+//
+// Define vendor specific routine types.
+//
+
+typedef
+PVOID
+(*PVEN_ALLOCATE_POOL_ROUTINE) (
+ IN ULONG NumberOfBytes
+ );
+
+typedef
+VOID
+(*PVEN_STALL_EXECUTION_ROUTINE) (
+ IN ULONG Microseconds
+ );
+
+typedef
+ULONG
+(*PVEN_PRINT_ROUTINE) (
+ IN PCHAR Format,
+ ...
+ );
+
+typedef
+VOID
+(*PVEN_SET_DISPLAY_ATTRIBUTES_ROUTINE) (
+ IN ULONG ForegroundColor,
+ IN ULONG BackgroundColor,
+ IN BOOLEAN HighIntensity,
+ IN BOOLEAN Underscored,
+ IN BOOLEAN ReverseVideo,
+ IN ULONG CharacterWidth,
+ IN ULONG CharacterHeight
+ );
+
+typedef
+VOID
+(*PVEN_OUTPUT_CHARACTER_ROUTINE) (
+ IN PVOID Character,
+ IN ULONG Row,
+ IN ULONG Column
+ );
+
+typedef
+VOID
+(*PVEN_SCROLL_VIDEO_ROUTINE) (
+ VOID
+ );
+
+typedef
+VOID
+(*PVEN_BOOT_RESTART_ROUTINE) (
+ IN PRESTART_BLOCK RestartBlock
+ );
+
+//
+// Define vendor specific prototypes.
+//
+
+PVOID
+FwAllocatePool (
+ IN ULONG NumberOfBytes
+ );
+
+VOID
+FwStallExecution (
+ IN ULONG Microseconds
+ );
+
+ULONG
+FwPrint (
+ IN PCHAR Format,
+ ...
+ );
+
+VOID
+FwSetDisplayAttributes (
+ IN ULONG ForegroundColor,
+ IN ULONG BackgroundColor,
+ IN BOOLEAN HighIntensity,
+ IN BOOLEAN Underscored,
+ IN BOOLEAN ReverseVideo,
+ IN ULONG CharacterWidth,
+ IN ULONG CharacterHeight
+ );
+
+VOID
+FwOutputCharacter (
+ IN PVOID Character,
+ IN ULONG Row,
+ IN ULONG Column
+ );
+
+VOID
+FwScrollVideo (
+ VOID
+ );
+
+//
+// Define vendor specific functions.
+//
+#define VenRestartBlock(RestartBlock) \
+ ((PVEN_BOOT_RESTART_ROUTINE)(SYSTEM_BLOCK->VendorVector[BootRestartRoutine])) \
+ ((RestartBlock))
+
+#define VenAllocatePool(NumberOfBytes) \
+ ((PVEN_ALLOCATE_MEMORY_ROUTINE)(SYSTEM_BLOCK->VendorVector[AllocatePoolRoutine])) \
+ ((NumberOfBytes))
+
+#define VenStallExecution(Microseconds) \
+ ((PVEN_STALL_EXECUTION_ROUTINE)(SYSTEM_BLOCK->VendorVector[StallExecutionRoutine])) \
+ ((Microseconds))
+
+#define VenPrint(x) \
+ ((PVEN_PRINT_ROUTINE)(SYSTEM_BLOCK->VendorVector[PrintRoutine])) \
+ ((x))
+
+#define VenPrint1(x,y) \
+ ((PVEN_PRINT_ROUTINE)(SYSTEM_BLOCK->VendorVector[PrintRoutine])) \
+ ((x), (y))
+
+#define VenPrint2(x,y,z) \
+ ((PVEN_PRINT_ROUTINE)(SYSTEM_BLOCK->VendorVector[PrintRoutine])) \
+ ((x), (y), (z))
+
+#define VenSetDisplayAttributes(ForegroundColor, BackgroundColor, HighIntensity, Underscored, ReverseVideo, CharacterWidth, CharacterHeight) \
+ ((PVEN_SET_DISPLAY_ATTRIBUTES_ROUTINE)(SYSTEM_BLOCK->VendorVector[SetDisplayAttributesRoutine])) \
+ ((ForegroundColor), (BackgroundColor), (HighIntensity), \
+ (Underscored), (ReverseVideo), (CharacterWidth), (CharacterHeight))
+
+#define VenOutputCharacter(Character, Row, Column) \
+ ((PVEN_OUTPUT_CHARACTER_ROUTINE)(SYSTEM_BLOCK->VendorVector[OutputCharacterRoutine])) \
+ ((Character), (Row), (Column))
+
+#define VenScrollVideo() \
+ ((PVEN_SCROLL_VIDEO_ROUTINE)(SYSTEM_BLOCK->VendorVector[ScrollVideoRoutine])) ()
+
+
+//
+// Define the Lookup table. At initialization, the driver must fill this table
+// with the device pathnames it can handle.
+//
+
+typedef struct _DRIVER_LOOKUP_ENTRY {
+ PCHAR DevicePath;
+ PBL_DEVICE_ENTRY_TABLE DispatchTable;
+} DRIVER_LOOKUP_ENTRY, *PDRIVER_LOOKUP_ENTRY;
+
+#define SIZE_OF_LOOKUP_TABLE BL_FILE_TABLE_SIZE
+
+extern DRIVER_LOOKUP_ENTRY DeviceLookupTable[SIZE_OF_LOOKUP_TABLE];
+
+//
+// Define the Device Pathname. This table is indexed with the FileId.
+// FwOpen tries to match the OpenPath with the entries in this table, and
+// if it finds a match it increments the reference counter. If it doesn't
+// find a match it tries to match an entry in the DRIVER_LOOKUP_TABLE
+// and then calls the Open routine of that driver.
+//
+
+#define SIZE_OF_ARC_DEVICENAME 64
+
+typedef struct _OPENED_PATHNAME_ENTRY {
+ ULONG ReferenceCounter;
+ CHAR DeviceName[SIZE_OF_ARC_DEVICENAME];
+} OPENED_PATHNAME_ENTRY, *POPENED_PATHNAME_ENTRY;
+
+#define SIZE_OF_OPENED_PATHNAME_TABLE BL_FILE_TABLE_SIZE
+
+extern OPENED_PATHNAME_ENTRY OpenedPathTable[SIZE_OF_OPENED_PATHNAME_TABLE];
+
+//
+// Driver initialization routines.
+//
+
+VOID
+FwInitializeMemory(
+ IN VOID
+ );
+
+VOID
+FwResetMemory(
+ IN VOID
+ );
+
+VOID
+DisplayInitialize(
+ IN OUT PDRIVER_LOOKUP_ENTRY LookupTableEntry,
+ IN ULONG Entries
+ );
+
+VOID
+KeyboardInitialize(
+ IN OUT PDRIVER_LOOKUP_ENTRY LookupTableEntry,
+ IN ULONG Entries
+ );
+
+VOID
+SerialInitialize(
+ IN OUT PDRIVER_LOOKUP_ENTRY LookupTableEntry,
+ IN ULONG Entries
+ );
+
+VOID
+HardDiskInitialize(
+ IN OUT PDRIVER_LOOKUP_ENTRY LookupTable,
+ IN ULONG Entries
+ );
+
+VOID
+FloppyInitialize(
+ IN OUT PDRIVER_LOOKUP_ENTRY LookupTableEntry,
+ IN ULONG Entries
+ );
+
+
+
+//
+// Define the private configuration packet structure, which contains a
+// configuration component as well as pointers to the component's parent,
+// peer, child, and configuration data.
+//
+
+typedef struct _CONFIGURATION_PACKET {
+ CONFIGURATION_COMPONENT Component;
+ struct _CONFIGURATION_PACKET *Parent;
+ struct _CONFIGURATION_PACKET *Peer;
+ struct _CONFIGURATION_PACKET *Child;
+ PVOID ConfigurationData;
+} CONFIGURATION_PACKET, *PCONFIGURATION_PACKET;
+
+//
+// The compressed configuration packet structure used to store configuration
+// data in NVRAM.
+//
+
+typedef struct _COMPRESSED_CONFIGURATION_PACKET {
+ UCHAR Parent;
+ UCHAR Class;
+ UCHAR Type;
+ UCHAR Flags;
+ ULONG Key;
+ UCHAR Version;
+ UCHAR Revision;
+ USHORT ConfigurationDataLength;
+ USHORT Identifier;
+ USHORT ConfigurationData;
+} COMPRESSED_CONFIGURATION_PACKET, *PCOMPRESSED_CONFIGURATION_PACKET;
+
+//
+// Defines for Identifier index.
+//
+
+#define NO_CONFIGURATION_IDENTIFIER 0xFFFF
+
+//
+// Defines for the volatile and non-volatile configuration tables.
+//
+
+#define NUMBER_OF_ENTRIES 40
+#define LENGTH_OF_IDENTIFIER (1024 - (40*16) - 8)
+#define LENGTH_OF_DATA 2048
+#define LENGTH_OF_ENVIRONMENT 1024
+#define LENGTH_OF_EISA_DATA 2044
+
+#define MAXIMUM_ENVIRONMENT_VALUE 256
+
+//
+// The volatile configuration table structure.
+//
+
+typedef struct _CONFIGURATION {
+ CONFIGURATION_PACKET Packet[NUMBER_OF_ENTRIES];
+ UCHAR Identifier[LENGTH_OF_IDENTIFIER];
+ UCHAR Data[LENGTH_OF_DATA];
+ UCHAR EisaData[LENGTH_OF_EISA_DATA];
+} CONFIGURATION, *PCONFIGURATION;
+
+//
+// The non-volatile configuration table structure.
+//
+
+typedef struct _NV_CONFIGURATION {
+
+ //
+ // First Page
+ //
+
+ COMPRESSED_CONFIGURATION_PACKET Packet[NUMBER_OF_ENTRIES];
+ UCHAR Identifier[LENGTH_OF_IDENTIFIER];
+ UCHAR Data[LENGTH_OF_DATA];
+ UCHAR Checksum1[4];
+ UCHAR Environment[LENGTH_OF_ENVIRONMENT];
+ UCHAR Checksum2[4];
+
+ //
+ // Second Page
+ //
+
+ UCHAR EisaData[LENGTH_OF_EISA_DATA];
+ UCHAR Checksum3[4];
+
+} NV_CONFIGURATION, *PNV_CONFIGURATION;
+
+//
+// Define identifier index, data index, pointer to configuration table.
+//
+
+extern ULONG IdentifierIndex;
+extern ULONG DataIndex;
+extern ULONG EisaDataIndex;
+extern PCONFIGURATION Configuration;
+
+//
+// Non-volatile ram layout.
+//
+
+#define NVRAM_CONFIGURATION NVRAM_VIRTUAL_BASE
+#define NVRAM_SYSTEM_ID (NVRAM_VIRTUAL_BASE + 0x00002000)
+
+//
+// Memory size. The MctadrRev2 is used to interpret the memory size value
+// in the configuration register.
+//
+
+extern ULONG MemorySize;
+#define MEMORY_SIZE (MemorySize << 20)
+extern BOOLEAN MctadrRev2;
+
+//
+// Memory layout.
+//
+
+#ifndef _PPC_
+#define FW_POOL_BASE 0xa07ed000
+#define FW_POOL_SIZE 0xf000
+#else
+#define FW_POOL_BASE 0xe80000
+#define FW_POOL_SIZE 0x3000
+#endif
+
+//
+// Define special character values. TEMPTEMP These should go somewhere else.
+//
+
+#define ASCII_NUL 0x00
+#define ASCII_BEL 0x07
+#define ASCII_BS 0x08
+#define ASCII_HT 0x09
+#define ASCII_LF 0x0A
+#define ASCII_VT 0x0B
+#define ASCII_FF 0x0C
+#define ASCII_CR 0x0D
+#define ASCII_CSI 0x9B
+#define ASCII_ESC 0x1B
+#define ASCII_SYSRQ 0x80
+
+//
+// Define screen colors.
+//
+
+typedef enum _ARC_SCREEN_COLOR {
+ ArcColorBlack,
+ ArcColorRed,
+ ArcColorGreen,
+ ArcColorYellow,
+ ArcColorBlue,
+ ArcColorMagenta,
+ ArcColorCyan,
+ ArcColorWhite,
+ MaximumArcColor
+ } ARC_SCREEN_COLOR;
+
+//
+// Define video board types for Jazz.
+//
+
+typedef enum _JAZZ_VIDEO_TYPE {
+ JazzVideoG300,
+ JazzVideoG364,
+ JazzVideoVxl,
+ Reserved3,
+ Reserved4,
+ Reserved5,
+ Reserved6,
+ Reserved7,
+ Reserved8,
+ Reserved9,
+ ReservedA,
+ ReservedB,
+ ReservedC,
+ ReservedD,
+ ReservedE,
+ ReservedF,
+ MipsVideoG364,
+ MaximumJazzVideo
+ } JAZZ_VIDEO_TYPE, *PJAZZ_VIDEO_TYPE;
+
+
+
+//
+// Define firmware routine prototypes.
+//
+
+VOID
+FwIoInitialize1 (
+ VOID
+ );
+
+VOID
+FwIoInitialize2 (
+ VOID
+ );
+
+BOOLEAN
+FwGetPathMnemonicKey(
+ IN PCHAR OpenPath,
+ IN PCHAR Mnemonic,
+ OUT PULONG Key
+ );
+
+PCHAR
+FwEnvironmentLoad(
+ VOID
+ );
+
+VOID
+FwPrintVersion (
+ VOID
+ );
+
+ARC_STATUS
+DisplayBootInitialize(
+ VOID
+ );
+
+ARC_STATUS
+FwGetVideoData (
+ OUT PMONITOR_CONFIGURATION_DATA MonitorData
+ );
+
+VOID
+FwSetVideoData (
+ IN PMONITOR_CONFIGURATION_DATA MonitorData
+ );
+
+VOID
+FwTerminationInitialize(
+ IN VOID
+ );
+
+VOID
+FwHalt(
+ IN VOID
+ );
+
+VOID
+FwMonitor(
+ IN ULONG
+ );
+
+VOID
+FwExceptionInitialize(
+ IN VOID
+ );
+
+VOID
+ResetSystem (
+ IN VOID
+ );
+
+
+VOID
+FwpFreeStub(
+ IN PVOID Buffer
+ );
+
+typedef enum _GETSTRING_ACTION {
+ GetStringSuccess,
+ GetStringEscape,
+ GetStringUpArrow,
+ GetStringDownArrow,
+ GetStringMaximum
+} GETSTRING_ACTION, *PGETSTRING_ACTION;
+
+GETSTRING_ACTION
+FwGetString(
+ OUT PCHAR String,
+ IN ULONG StringLength,
+ IN PCHAR InitialString OPTIONAL,
+ IN ULONG CurrentRow,
+ IN ULONG CurrentColumn
+ );
+
+ARC_STATUS
+FwConfigurationCheckChecksum (
+ VOID
+ );
+
+ARC_STATUS
+FwEnvironmentCheckChecksum (
+ VOID
+ );
+
+VOID
+FwpReservedRoutine(
+ VOID
+ );
+
+VOID
+FwWaitForKeypress(
+ VOID
+ );
+
+VOID
+JzShowTime (
+ BOOLEAN First
+ );
+
+VOID
+JxBmp (
+ VOID
+ );
+
+ULONG
+JxDisplayMenu (
+ IN PCHAR Choices[],
+ IN ULONG NumberOfChoices,
+ IN LONG DefaultChoice,
+ IN ULONG CurrentLine
+ );
+
+BOOLEAN
+FwGetVariableSegment (
+ IN ULONG SegmentNumber,
+ IN OUT PCHAR Segment
+ );
+
+ARC_STATUS
+FwSetVariableSegment (
+ IN ULONG SegmentNumber,
+ IN PCHAR VariableName,
+ IN OUT PCHAR Segment
+ );
+
+ARC_STATUS
+JzAddProcessor (
+ IN ULONG ProcessorNumber
+ );
+
+//
+// Print macros.
+//
+
+extern BOOLEAN DisplayOutput;
+extern BOOLEAN SerialOutput;
+extern BOOLEAN FwConsoleInitialized;
+extern BOOLEAN SetupIsRunning;
+
+ULONG
+FwPrint (
+ PCHAR Format,
+ ...
+ );
+
+#define FwClearScreen() \
+ FwPrint("%c2J", ASCII_CSI)
+
+#define FwSetScreenColor(FgColor, BgColor) \
+ FwPrint("%c3%dm", ASCII_CSI, (UCHAR)FgColor); \
+ FwPrint("%c4%dm", ASCII_CSI, (UCHAR)BgColor)
+
+#define FwSetScreenAttributes( HighIntensity, Underscored, ReverseVideo ) \
+ FwPrint("%c0m", ASCII_CSI); \
+ if (HighIntensity) { \
+ FwPrint("%c1m", ASCII_CSI); \
+ } \
+ if (Underscored) { \
+ FwPrint("%c4m", ASCII_CSI); \
+ } \
+ if (ReverseVideo) { \
+ FwPrint("%c7m", ASCII_CSI); \
+ }
+
+#define FwSetPosition( Row, Column ) \
+ FwPrint("%c%d;%dH", ASCII_CSI, (Row + 1), (Column + 1))
+
+#define FwMoveCursorLeft(Spaces) \
+ FwPrint ("%c%dD", ASCII_CSI, Spaces)
+
+#define FwMoveCursorToColumn(Spaces) \
+ FwPrint( "\r" ); \
+ if ( Spaces > 1 ) \
+ FwPrint( "%c%dC", ASCII_CSI, Spaces - 1)
+#endif // _FWP_
diff --git a/private/ntos/fw/ppc/fwstring.h b/private/ntos/fw/ppc/fwstring.h
new file mode 100644
index 000000000..3285da9af
--- /dev/null
+++ b/private/ntos/fw/ppc/fwstring.h
@@ -0,0 +1,131 @@
+
+//
+// Common strings.
+//
+
+extern PCHAR FW_OK_MSG;
+extern PCHAR FW_CRLF_MSG;
+extern PCHAR FW_ERROR1_MSG;
+extern PCHAR FW_ERROR2_MSG;
+
+//
+// Firmware strings.
+//
+
+extern PCHAR FW_NOT_ENOUGH_ENTRIES_MSG;
+extern PCHAR FW_FILESYSTEM_NOT_REQ_MSG;
+extern PCHAR FW_UNKNOWN_SECTION_TYPE_MSG;
+extern PCHAR FW_UNKNOWN_RELOC_TYPE_MSG;
+extern PCHAR FW_START_MSG;
+extern PCHAR FW_RUN_A_PROGRAM_MSG;
+extern PCHAR FW_RUN_SETUP_MSG;
+extern PCHAR FW_ACTIONS_MSG;
+extern PCHAR FW_USE_ARROW_MSG;
+extern PCHAR FW_USE_ENTER_MSG;
+extern PCHAR FW_AUTOBOOT_MSG;
+extern PCHAR FW_BREAKPOINT_MSG;
+extern PCHAR FW_OFF_MSG;
+extern PCHAR FW_ON_MSG;
+extern PCHAR FW_DEBUGGER_CONNECTED_MSG;
+extern PCHAR FW_PROGRAM_TO_RUN_MSG;
+extern PCHAR FW_PATHNAME_NOT_DEF_MSG;
+extern PCHAR FW_PRESS_ANY_KEY_MSG;
+extern PCHAR FW_ERROR_CODE_MSG;
+extern PCHAR FW_PRESS_ANY_KEY2_MSG;
+extern PCHAR FW_INITIALIZING_MSG;
+extern PCHAR FW_CONSOLE_IN_ERROR_MSG;
+extern PCHAR FW_CONSOLE_IN_ERROR2_MSG;
+extern PCHAR FW_CONSOLE_OUT_ERROR_MSG;
+extern PCHAR FW_CONSOLE_OUT_ERROR2_MSG;
+extern PCHAR FW_SPIN_DISKS_MSG;
+extern PCHAR FW_SYSTEM_HALT_MSG;
+
+extern PCHAR FW_NVRAM_MSG[];
+#define FW_NVRAM_MSG_SIZE 4
+
+extern PCHAR FW_VIDEO_MSG[];
+#define FW_VIDEO_MSG_SIZE 8
+
+extern PCHAR FW_ERROR_MSG[];
+
+//
+// Monitor Strings.
+//
+
+extern PCHAR MON_INVALID_ARGUMENT_COUNT_MSG;
+extern PCHAR MON_UNALIGNED_ADDRESS_MSG;
+extern PCHAR MON_INVALID_VALUE_MSG;
+extern PCHAR MON_INVALID_REGISTER_MSG;
+extern PCHAR MON_NOT_VALID_ADDRESS_MSG;
+extern PCHAR MON_INVALID_ADDRESS_RANGE_MSG;
+extern PCHAR MON_FORMAT1_MSG;
+extern PCHAR MON_JAZZ_MONITOR_MSG;
+extern PCHAR MON_PRESS_H_MSG;
+extern PCHAR MON_NMI_MSG;
+extern PCHAR MON_CACHE_ERROR_MSG;
+extern PCHAR MON_EXCEPTION_MSG;
+extern PCHAR MON_PROCESSOR_B_EXCEPTION;
+extern PCHAR MON_PROCESSOR_A_EXCEPTION;
+extern PCHAR MON_BUS_PARITY_ERROR;
+extern PCHAR MON_ECC_ERROR_MSG;
+extern PCHAR MON_MEM_ECC_FAILED_MSG;
+extern PCHAR MON_MEM_PARITY_FAILED_MSG;
+extern PCHAR MON_CACHE_ERROR_EPC_MSG;
+extern PCHAR MON_CACHE_ERROR_REG_MSG;
+extern PCHAR MON_PARITY_DIAG_MSG;
+extern PCHAR MON_PROCESSOR_B_MSG;
+extern PCHAR MON_NO_RETURN_MSG;
+extern PCHAR MON_RESET_MACHINE_MSG;
+extern PCHAR MON_UNRECOGNIZED_COMMAND_MSG;
+
+extern PCHAR MON_HELP_TABLE[];
+#define MON_HELP_SIZE 15
+
+//
+// Selftest strings.
+//
+
+extern PCHAR ST_HANG_MSG;
+extern PCHAR ST_PROCESSOR_B_MSG;
+extern PCHAR ST_NMI_MSG;
+extern PCHAR ST_INVALID_ADDRESS_MSG;
+extern PCHAR ST_IO_CACHE_ADDRESS_MSG;
+extern PCHAR ST_KEYBOARD_ERROR_MSG;
+extern PCHAR ST_ENABLE_PROCESSOR_B_MSG;
+extern PCHAR ST_TIMEOUT_PROCESSOR_B_MSG;
+extern PCHAR ST_PROCESSOR_B_DISABLED_MSG;
+extern PCHAR ST_PROCESSOR_B_NOT_PRESENT_MSG;
+extern PCHAR ST_ZEROING_MEMORY_MSG;
+extern PCHAR ST_MEMORY_TEST_MSG;
+extern PCHAR ST_MEMORY_ERROR_MSG;
+extern PCHAR ST_TEST_MSG;
+extern PCHAR ST_MEMORY_CONTROLLER_MSG;
+extern PCHAR ST_INTERRUPT_CONTROLLER_MSG;
+extern PCHAR ST_KEYBOARD_CONTROLLER_MSG;
+extern PCHAR ST_ERROR_MSG;
+extern PCHAR ST_KEYBOARD_NOT_PRESENT_MSG;
+extern PCHAR ST_SERIAL_LINE_MSG;
+extern PCHAR ST_PARALLEL_PORT_MSG;
+extern PCHAR ST_FLOPPY_MSG;
+extern PCHAR ST_SCSI_MSG;
+extern PCHAR ST_ETHERNET_MSG;
+extern PCHAR ST_ETHERNET_ADDRESS_MSG;
+extern PCHAR ST_ETHERNET_LOOPBACK_MSG;
+extern PCHAR ST_ISP_MSG;
+extern PCHAR ST_RTC_MSG;
+extern PCHAR ST_ARC_MULTIBOOT_MSG;
+extern PCHAR ST_COPYRIGHT_MSG;
+
+//
+// Sonic test strings.
+//
+
+extern PCHAR ST_RECEIVED_MSG;
+
+//
+// Stubs strings.
+//
+
+extern PCHAR ST_BUGCHECK_MSG;
+extern PCHAR ST_ASSERT_MSG;
+extern PCHAR ST_UNIMPLEMENTED_ROUTINE_MSG;
diff --git a/private/ntos/fw/ppc/inc.h b/private/ntos/fw/ppc/inc.h
new file mode 100644
index 000000000..2cffce2fd
--- /dev/null
+++ b/private/ntos/fw/ppc/inc.h
@@ -0,0 +1,883 @@
+
+
+///////////////////////////////////////////////////////////////////////////////
+// General definitions
+///////////////////////////////////////////////////////////////////////////////
+
+
+#define WORD_2P2 2 // 2^2 = 4 bytes
+#define HALFWORD_2P2 1 // 2^1 = 2 bytes
+#define BYTE_2P2 0 // 2^0 = 1 bytes
+#define BITSXBYTE 8 // 8 bits = 1 byte
+
+#define ASCII_BLOCK_SIZE 512 // ASCII block size
+
+#define MIN(x,y) ((x) > (y) ? (y) : (x)) // minimum number
+
+
+#define INSTRUCTION_DELAY 10 // nsec for each instruction
+ // using 50MHZ externl clock
+#define MAX_DCACHE_LINE_SIZE 32 // max bytes per Data cache line
+
+#define UNMAPPED_SIZE (512*1024*1024) // 512 Mbytes of unmapped space
+
+#define PAGE_4G_SHIFT 32 // 2^32 = 4Gbytes
+#define PAGE_32M_SHIFT 25 // 2^25 = 32Mbytes
+#define PAGE_32M_SIZE (1 << PAGE_32M_SHIFT) // 32 Mbytes
+#define PAGE_16M_SHIFT 24 // 2^24 = 16Mbytes
+#define PAGE_16M_SIZE (1 << PAGE_16M_SHIFT) // 16 Mbytes
+#define PAGE_8M_SHIFT 23 // 2^23 = 8Mbytes
+#define PAGE_8M_SIZE (1 << PAGE_8M_SHIFT) // 8 Mbytes
+#define PAGE_4M_SHIFT 22 // 2^22 = 4Mbytes
+#define PAGE_4M_SIZE (1 << PAGE_4M_SHIFT) // 4 Mbytes
+#define PAGE_2M_SHIFT 21 // 2^21 = 2Mbytes
+#define PAGE_2M_SIZE (1 << PAGE_2M_SHIFT) // 2 Mbytes
+#define PAGE_1M_SHIFT 20 // 2^20 = 1Mbyte
+#define PAGE_1M_SIZE (1 << PAGE_1M_SHIFT) // 1 Mbyte
+#define PAGE_MAX_SHIFT PAGE_16M_SHIFT // max TLB page shift.
+#define PAGE_MAX_SIZE (1 << PAGE_MAX_SHIFT) // max TLB page (one entry)
+#define PAGES_IN_4G (1 << (PAGE_4G_SHIFT - PAGE_SHIFT)) // # 4k in 4Gbytes
+#define PAGES_IN_16M (1 << (PAGE_16M_SHIFT - PAGE_SHIFT)) // # 4k in 16Mbytes
+#define PAGES_IN_1M (1 << (PAGE_1M_SHIFT - PAGE_SHIFT)) // # 4k in 1Mbyte
+
+//#define HIT_WRITEBACK_D 0x19 // hit write back 1st cache
+//#define HIT_WRITEBACK_SD 0x1B // hit write back 2nd cache
+
+#define EISA_LATCH_VIRTUAL_BASE (DEVICE_VIRTUAL_BASE + 0xE000)
+#define EISA_LOCK_VIRTUAL_BASE (DEVICE_VIRTUAL_BASE + 0xE800)
+#define EISA_INT_ACK_ADDR (DEVICE_VIRTUAL_BASE + 0x238)
+#define INT_ENABLE_ADDR (DEVICE_VIRTUAL_BASE + 0xE8)
+
+//
+// coff image info structure
+//
+
+typedef struct _IMAGE_FLAGS
+ {
+ ULONG Exec : 1;
+ ULONG Reloc : 1;
+
+ } IMAGE_FLAGS, *PIMAGE_FLAGS;
+
+
+typedef struct _IMAGE_INFO
+ {
+ IMAGE_FLAGS Flags; // image characteristic
+ ULONG ImageBase; // base address
+ ULONG ImageSize; // in 4k units
+
+ } IMAGE_INFO, *PIMAGE_INFO;
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+// General function prototypes
+///////////////////////////////////////////////////////////////////////////////
+
+PCHAR
+FwToUpperStr
+ (
+ IN OUT PCHAR s
+ );
+
+PCHAR
+FwToLowerStr
+ (
+ IN OUT PCHAR s
+ );
+
+PCHAR
+FwGetPath
+ (
+ IN PCONFIGURATION_COMPONENT Component,
+ OUT PCHAR String
+ );
+
+PCHAR
+FwGetMnemonic
+ (
+ IN PCONFIGURATION_COMPONENT Component
+ );
+
+BOOLEAN
+FwValidMnem
+ (
+ IN PCHAR Str
+ );
+
+ULONG
+Fw4UcharToUlongLSB
+ (
+ IN PUCHAR String
+ );
+
+
+ULONG
+Fw4UcharToUlongMSB
+ (
+ IN PUCHAR String
+ );
+
+PCHAR
+FwStoreStr
+ (
+ IN PCHAR Str
+ );
+
+BOOLEAN
+FwGetNumMnemonicKey
+ (
+ IN PCHAR Path,
+ IN UCHAR KeyNumber,
+ IN PULONG Key
+ );
+
+BOOLEAN
+FwGetMnemonicKey
+ (
+ IN PCHAR Path,
+ IN PCHAR Mnemonic,
+ IN PULONG Key
+ );
+
+BOOLEAN
+FwGetNextMnemonic
+ (
+ IN PCHAR Path,
+ IN PCHAR Mnemonic,
+ OUT PCHAR NextMnemonic
+ );
+
+BOOLEAN
+FwGetMnemonicPath
+ (
+ IN PCHAR Path,
+ IN PCHAR Mnemonic,
+ OUT PCHAR MnemonicPath
+ );
+
+BOOLEAN
+FwGetEisaId
+ (
+ IN PCHAR PathName,
+ OUT PCHAR EisaId,
+ OUT PUCHAR IdInfo
+ );
+
+VOID
+FwUncompressEisaId
+ (
+ IN PUCHAR CompEisaId,
+ OUT PUCHAR UncompEisaId
+ );
+
+BOOLEAN
+FwGetEisaBusIoCpuAddress
+ (
+ IN PCHAR EisaPath,
+ OUT PVOID *IoBusAddress
+ );
+
+BOOLEAN
+GetNextPath
+ (
+ IN OUT PCHAR *PPathList,
+ OUT PCHAR PathTarget
+ );
+
+//PDRIVER_STRATEGY
+//FwGetStrategy
+// (
+// IN PCHAR Path
+// );
+
+ARC_STATUS
+FwGetImageInfo
+ (
+ IN PCHAR ImagePath,
+ OUT PIMAGE_INFO pImageInfo
+ );
+
+PCONFIGURATION_COMPONENT
+FwGetControllerComponent
+ (
+ IN PCHAR Path
+ );
+
+PCONFIGURATION_COMPONENT
+FwGetPeripheralComponent
+ (
+ IN PCHAR Path
+ );
+
+PCHAR
+FwGetControllerMnemonic
+ (
+ IN PCHAR Path
+ );
+
+PCHAR
+FwGetPeripheralMnemonic
+ (
+ IN PCHAR Path
+ );
+
+BOOLEAN
+FwSizeToShift
+ (
+ IN ULONG Size,
+ OUT ULONG Shift
+ );
+
+ARC_STATUS
+FwGetImageInfo
+ (
+ IN PCHAR ImagePath,
+ OUT PIMAGE_INFO pImageInfo
+ );
+
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+// EISA configuration
+///////////////////////////////////////////////////////////////////////////////
+
+
+
+#define NO_ADAP_ID 0x80000000 // adapter id not present
+#define WAIT_ADAP_ID 0x70000000 // adapter not ready yet
+#define TIMEOUT_UNITS 200 // 200 units of 10msec
+
+
+typedef struct _EISA_SLOT_INFO
+ {
+ UCHAR IdInfo;
+ UCHAR MajorRevLevel;
+ UCHAR MinorRevLevel;
+ UCHAR LSByteChecksum;
+ UCHAR MSByteChecksum;
+ UCHAR FunctionsNumber;
+ UCHAR FunctionInfo;
+ UCHAR Id1stChar;
+ UCHAR Id2ndChar;
+ UCHAR Id3rdChar;
+ UCHAR Id4thChar;
+ } EISA_SLOT_INFO, *PEISA_SLOT_INFO;
+
+
+#define ID_DIGIT_SIZE 4 // # of bits
+#define ID_CHAR_SIZE 5 // # of bits
+#define ID_DIGIT_MASK ((1<<ID_DIGIT_SIZE)-1) // field size
+#define ID_CHAR_MASK ((1<<ID_CHAR_SIZE)-1) // field size
+#define EISA_SLOT_INFO_SIZE sizeof(EISA_SLOT_INFO)
+#define EISA_FUNC_INFO_SIZE 320 // fixed length
+
+#define EISA_SLOT_MIN_INFO ( CONFIGDATAHEADER_SIZE + EISA_SLOT_INFO_SIZE )
+
+//
+// EISA configuration data extensions
+//
+
+typedef struct _EISA_ADAPTER_DETAILS
+ {
+ CONFIGDATAHEADER ConfigDataHeader;
+ ULONG NumberOfSlots;
+ PVOID IoStart;
+ ULONG IoSize;
+ } EISA_ADAPTER_DETAILS, *PEISA_ADAPTER_DETAILS;
+
+
+
+//
+// EISA_FUNC_INFO block offsets
+//
+
+#define CFG_ID_INFO_OFS 0x04 // offset to Id info byte
+#define CFG_SLOT_INFO_OFS 0x05 // offset to slot info byte
+#define CFG_FN_INFO_OFS 0x22 // offset to function info byte
+#define CFG_ASC_BLK_OFS 0x23 // offset to ASCII data block
+#define CFG_MEM_BLK_OFS 0x73 // offset to mem cfg data block
+#define CFG_IRQ_BLK_OFS 0xB2 // offset to IRQ cfg data block
+#define CFG_DMA_BLK_OFS 0xC0 // offset to DMA cfg data block
+#define CFG_PRT_BLK_OFS 0xC8 // offset to port I/O data block
+#define CFG_INI_BLK_OFS 0x104 // offset to port init data block
+
+#define CFG_FREE_BLK_OFS 0x73 // offset of free form cfg data block
+
+//
+// EISA_FUNC_INFO block lengths
+//
+
+#define CFG_ASC_BLK_LEN 80 // length of ASCII data block
+#define CFG_MEM_BLK_LEN 63 // length of mem cfg data block
+#define CFG_IRQ_BLK_LEN 14 // length of IRQ cfg data block
+#define CFG_DMA_BLK_LEN 8 // length of DMA cfg data block
+#define CFG_PRT_BLK_LEN 60 // length of port I/O data block
+#define CFG_INI_BLK_LEN 60 // length of port init data block
+
+#define CFG_FREE_BLK_LEN 205 // length of free form cfg data block
+
+//
+// ID info byte layout
+//
+
+#define CFG_DUPLICATE_ID 0x80 // more IDs with the same value
+#define CFG_UNREADABLE_ID 0x40 // the ID is not readable
+#define CFG_SLOT_MASK 0x30 // slot mask
+#define CFG_SLOT_EXP 0x00 // expansion slot
+#define CFG_SLOT_EMB 0x10 // embedded slot
+#define CFG_SLOT_VIR 0x20 // virtual slot
+
+//
+// slot info byte layout
+//
+
+#define CFG_INCOMPLETE 0x80 // configuration is incomplete
+#define CFG_EISA_IOCHKERR 0x02 // support for EISA IOCHKERR signal
+#define CFG_EISA_ENABLE 0x01 // support for disable feature
+
+//
+// function information byte layout
+//
+
+#define CFG_FN_DISABLED 0x80 // function is disabled
+#define CFG_FREE_FORM 0x40 // free-form data
+#define CFG_INI_ENTRY 0x20 // port init entry(s) exists
+#define CFG_PRT_ENTRY 0x10 // port range entry(s) exists
+#define CFG_DMA_ENTRY 0x08 // DMA entry(s) exists
+#define CFG_IRQ_ENTRY 0x04 // IRQ entry(s) exists
+#define CFG_MEM_ENTRY 0x02 // memory entry(s) exists
+#define CFG_ASC_ENTRY 0x01 // type/subtype entry follows
+
+#define CFG_MORE_ENTRY 0x80 // more mem/DMA/int/port entries
+
+//
+// memory configuration byte layout
+//
+
+#define CFG_MEM_RW 0x01 // memory is read/write
+#define CFG_MEM_CACHE 0x02 // enable caching of memory
+#define CFG_MEM_WRBACK 0x04 // cache is write-back
+#define CFG_MEM_TYPE 0x18 // memory type mask
+#define CFG_MEM_SYS 0x00 // base or extended
+#define CFG_MEM_EXP 0x08 // expanded
+#define CFG_MEM_VIR 0x10 // virtual
+#define CFG_MEM_OTHER 0x18 // other
+
+//
+// interrupt configuration byte layout
+//
+
+#define CFG_IRQ_SHARE 0x40 // IRQ is sharable
+#define CFG_IRQ_LEVEL 0x20 // IRQ is level triggered
+#define CFG_IRQ_MASK 0x0F // IRQ mask
+
+//
+// DMA configuration byte layout
+//
+
+#define CFG_DMA_SHARED 0x40 // DMA has to be chared
+#define CFG_DMA_MASK 0x07 // DMA mask
+#define CFG_DMA_CFG_MASK 0x3C // used to mask off the reserved bits
+#define CFG_DMA_TIM_MASK 0x30 // timing mode bits mask
+#define CFG_DMA_ADD_MASK 0x0C // addressing mode bits mask
+
+//
+// init configuration byte layout
+//
+
+#define CFG_INI_PMASK 0x04 // Port value or port and mask value
+#define CFG_INI_MASK 0x03 // Type of access (byte, word or dword)
+#define CFG_INI_BYTE 0x00 // Byte address (8-bit)
+#define CFG_INI_HWORD 0x01 // HalfWord address (16-bit)
+#define CFG_INI_WORD 0x02 // Word address (32-bit)
+
+
+//
+// eisa cfg errors
+//
+
+typedef enum _EISA_CFG_ERROR
+ {
+ CfgNoErrCode,
+ IdTimeout,
+ CfgIdError,
+ CfgMissing,
+ CfgIncomplete,
+ CfgIncorrect,
+ CfgDeviceFailed,
+ CfgMemError,
+ CfgIrqError,
+ CfgDmaError,
+ CfgIniError,
+ OmfRomError,
+ OmfError,
+ MemAllocError,
+ TooManyDeviceError,
+ MaximumValue
+ } EISA_CFG_ERROR;
+
+
+//
+// eisa pod messages index
+//
+
+typedef enum _EISA_CHECKPOINT
+ {
+ EisaPic,
+ EisaDma,
+ EisaNmi,
+ EisaRefresh,
+ EisaPort61,
+ EisaTimer1,
+ EisaTimer2,
+ EisaCfg,
+ EisaHotNmi,
+ EisaPodMaxMsg
+
+ } EISA_CHECKPOINT;
+
+//
+// define pod structure
+//
+
+typedef struct _EISA_CHECKPOINT_INFO
+ {
+ PCHAR Msg; // pod message
+ UCHAR Flags; // control flags
+ // bit 0 = error
+ // bit 1 = fatal
+ // bit 2 = configuration
+ // bit 3 = display pass/error message
+ UCHAR Par; // PARALLEL test number
+ UCHAR SubPar; // PARALLEL subtest number
+ UCHAR Led; // LED test number
+ UCHAR SubLed; // LED subtest number
+
+ } EISA_CHECKPOINT_INFO, *PEISA_CHECKPOINT_INFO;
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+// EISA I/O ports
+///////////////////////////////////////////////////////////////////////////////
+
+//
+// PIC
+//
+
+#define PIC1 0x20 // 1st PIC address (0-7 IRQs)
+#define PIC1_MASK 0x21 // 1st PIC mask port (0-7 IRQs)
+#define PIC1_ELCR 0x4D0 // 1st Edge/Level Control Register
+
+#define PIC2 0xA0 // 2nd PIC address (8-15 IRQs)
+#define PIC2_MASK 0xA1 // 2nd PIC mask port (8-15 IRQs)
+#define PIC2_ELCR 0x4D1 // 2nd Edge/Level Control Register
+
+#define EISA_IRQS 16 // # IRQ lines
+
+#define IRQ0 0x00 // 1st IRQ (1st PIC)
+#define IRQ1 0x01 // 2nd IRQ (1st PIC)
+#define IRQ2 0x02 // 3th IRQ (1st PIC)
+#define IRQ3 0x03 // 4th IRQ (1st PIC)
+#define IRQ4 0x04 // 5th IRQ (1st PIC)
+#define IRQ5 0x05 // 6th IRQ (1st PIC)
+#define IRQ6 0x06 // 7th IRQ (1st PIC)
+#define IRQ7 0x07 // 8th IRQ (1st PIC)
+#define IRQ8 0x08 // 9th IRQ (2nd PIC)
+#define IRQ9 0x09 // 10th IRQ (2nd PIC)
+#define IRQ10 0x0A // 11th IRQ (2nd PIC)
+#define IRQ11 0x0B // 12th IRQ (2nd PIC)
+#define IRQ12 0x0C // 13th IRQ (2nd PIC)
+#define IRQ13 0x0D // 14th IRQ (2nd PIC)
+#define IRQ14 0x0E // 15th IRQ (2nd PIC)
+#define IRQ15 0x0F // 16th IRQ (2nd PIC)
+
+#define OCW3_IRR 0x0A // OCW3 command to read the IRR
+#define OCW3_ISR 0x0B // OCW3 command to read the ISR
+#define OCW2_EOI 0x20 // OCW2 non specific EOI
+#define OCW2_SEOI 0x60 // OCW2 specific EOI mask
+
+
+
+//
+// DMA
+//
+
+
+#define EISA_DMAS 8 // # of DMA channels
+
+#define DMA_COUNT_0 0x01 // 16-bit count register
+#define DMA_COUNT_1 0x03 // 16-bit count register
+#define DMA_COUNT_2 0x05 // 16-bit count register
+#define DMA_COUNT_3 0x07 // 16-bit count register
+#define DMA_COUNT_4 0x0C2 // 16-bit count register
+#define DMA_COUNT_5 0x0C6 // 16-bit count register
+#define DMA_COUNT_6 0x0CA // 16-bit count register
+#define DMA_COUNT_7 0x0CE // 16-bit count register
+
+#define DMA_HCOUNT_0 0x0401 // I/O address high word count reg.
+#define DMA_HCOUNT_1 0x0403 // I/O address high word count reg.
+#define DMA_HCOUNT_2 0x0405 // I/O address high word count reg.
+#define DMA_HCOUNT_3 0x0407 // I/O address high word count reg.
+#define DMA_HCOUNT_5 0x04C6 // I/O address high word count reg.
+#define DMA_HCOUNT_6 0x04CA // I/O address high word count reg.
+#define DMA_HCOUNT_7 0x04CE // I/O address high word count reg.
+
+#define DMA_ADDR_0 0x00 // 16-bit address register
+#define DMA_ADDR_1 0x02 // 16-bit address register
+#define DMA_ADDR_2 0x04 // 16-bit address register
+#define DMA_ADDR_3 0x06 // 16-bit address register
+#define DMA_ADDR_4 0x0C0 // 16-bit address register
+#define DMA_ADDR_5 0x0C4 // 16-bit address register
+#define DMA_ADDR_6 0x0C8 // 16-bit address register
+#define DMA_ADDR_7 0x0CC // 16-bit address register
+
+#define DMA_PAGE_0 0x087 // 8-bit address, low page
+#define DMA_PAGE_1 0x083 // 8-bit address, low page
+#define DMA_PAGE_2 0x081 // 8-bit address, low page
+#define DMA_PAGE_3 0x082 // 8-bit address, low page
+#define DMA_PAGE_RFR 0x08F // DMA lo page register refresh
+#define DMA_PAGE_5 0x08B // 8-bit address, low page
+#define DMA_PAGE_6 0x089 // 8-bit address, low page
+#define DMA_PAGE_7 0x08A // 8-bit address, low page
+
+#define DMA_HPAGE_0 0x0487 // I/O address, high page
+#define DMA_HPAGE_1 0x0483 // I/O address, high page
+#define DMA_HPAGE_2 0x0481 // I/O address, high page
+#define DMA_HPAGE_3 0x0482 // I/O address, high page
+#define DMA_HPAGE_RFR 0x048F // DMA hi page register refresh
+#define DMA_HPAGE_5 0x048B // I/O address, high page
+#define DMA_HPAGE_6 0x0489 // I/O address, high page
+#define DMA_HPAGE_7 0x048A // I/O address, high page
+
+#define DMA_STOP_0 0x04E0 // stop register
+#define DMA_STOP_1 0x04E4 // stop register
+#define DMA_STOP_2 0x04E8 // stop register
+#define DMA_STOP_3 0x04EC // stop register
+#define DMA_STOP_5 0x04F4 // stop register
+#define DMA_STOP_6 0x04F8 // stop register
+#define DMA_STOP_7 0x04FC // stop register
+
+// channels 0 to 3
+
+#define DMA_STATUS03 0x08 // status register
+#define DMA_COMMAND03 0x08 // command register
+#define DMA_REQUEST03 0x09 // request register
+#define DMA_1MASK03 0x0A // set/clear one mask reg
+#define DMA_MODE03 0x0B // 6-bit write mode register
+#define DMA_FF_CLR03 0x0C // clear byte pointer flip/flop
+#define DMA_TEMP 0x0D // 8-bit read temporary register
+#define DMA_MASTER_CLR03 0x0D // master clear reg
+#define DMA_MASK_CLR03 0x0E // clear all mask reg bits
+#define DMA_MASKS03 0x0F // write all mask reg bits
+#define DMA_MASK_STAT03 0x0F // mask status register
+#define DMA_CHAIN03 0x040A // chaining mode register
+#define DMA_EXTMODE03 0x040B // extended mode register
+
+// channels 4 to 7
+
+#define DMA_STATUS47 0x0D0 // status register
+#define DMA_COMMAND47 0x0D0 // command register
+#define DMA_REQUEST47 0x0D2 // request register
+#define DMA_1MASK47 0x0D4 // set/clear one mask reg
+#define DMA_MODE47 0x0D6 // 6-bit write mode register
+#define DMA_FF_CLR47 0x0D8 // clear byte pointer flip/flop
+#define DMA_MASTER_CLR47 0x0DA // master clear reg
+#define DMA_MASK_CLR47 0x0DC // clear all mask reg bits
+#define DMA_MASKS47 0x0DE // write all mask reg bits
+#define DMA_MASK_STAT47 0x0DE // mask status register
+#define DMA_CHAIN47 0x04D4 // chaining mode register
+#define DMA_EXTMODE47 0x04D6 // extended mode register
+
+typedef struct _EISA_DMA_REGS_TEST
+ {
+ USHORT Address; // address register
+ USHORT LowPage; // low page register
+ USHORT HighPage; // high page register
+ USHORT LowCount; // low count register
+ USHORT HighCount; // high count register
+ USHORT Stop; // stop count register
+
+ } EISA_DMA_REGS_TEST, *PEISA_DMA_REGS_TEST;
+
+typedef struct _EISA_DMA_CTRL_TEST
+ {
+ USHORT Clear; // clear mask register
+ USHORT MaskAll; // set global mask register
+ USHORT Mask; // set single mask register
+ USHORT MaskStatus; // status mask register
+ USHORT Chain; // chaining register
+
+ } EISA_DMA_CTRL_TEST, *PEISA_DMA_CTRL_TEST;
+
+//
+// Option Boards
+//
+
+
+#define EISA_PRODUCT_ID 0xC80 // word
+#define EXPANSION_BOARD_CTRL_BITS 0xC84 // byte
+#define EISA_IOCHKERR 0x02 // IOCHKERR bit
+#define EISAROMBIT 0x08 // ARC ROM bit
+#define ROMINDEX 0xCB0 // word
+#define ROMREAD 0xCB4 // word
+
+
+//
+// General ports
+//
+
+#define EISA_TIMER1_CTRL 0x43 // interval timer1 ctrl port
+#define EISA_TIMER1_COUNTER0 0x40 // timer1 counter 0
+#define EISA_TIMER1_COUNTER1 0x41 // timer1 counter 1
+#define EISA_TIMER1_COUNTER2 0x42 // timer1 counter 2
+#define EISA_RFR_COUNT 0x12 // refresh count ~15usec
+#define EISA_SPEAKER_CLOCK 1193000 // timer1 counter2 clock
+#define EISA_SPEAKER_FREQ 896 // fw speaker frequence in Hz
+#define EISA_SPEAKER_MAX_FREQ EISA_SPEAKER_CLOCK
+#define EISA_SPEAKER_MIN_FREQ (EISA_SPEAKER_CLOCK/0xFFFF + 1)
+
+#define EISA_TIMER2_CTRL 0x4B // interval timer2 ctrl port
+#define EISA_TIMER2_COUNTER0 0x48 // timer2 counter 0
+#define EISA_TIMER2_COUNTER2 0x4A // timer2 counter 2
+
+// the meaning of EISA_RFR_RETRY is as follow :
+// 35usec ( 15usec * 2) = 35*1000 nsec
+// 3 instructions = read, test, jump (the worst case)
+
+#define EISA_RFR_RETRY ((35*1000)/(3*INSTRUCTION_DELAY))
+
+#define EISA_SYS_CTRL_PORTB 0x61 // System Control Port B
+
+#define EISA_SPEAKER_GATE 0x01 // gate signal for speaker timer
+#define EISA_SPEAKER_TIMER 0x02 // speaker timer on
+#define EISA_PARITY_OFF 0x04 // parity error disabled
+#define EISA_IOCHK_OFF 0x08 // I/O channel check disabled
+#define EISA_REFRESH 0x10 // refresh bit ( bit 4 )
+#define EISA_SPEAKER_OUT 0x20 // speaker output
+#define EISA_IOCHK_STATUS 0x40 // IOCHK# asserted
+#define EISA_PARITY_STATUS 0x80 // parity error
+
+#define EISA_RTC_CTRL 0x70 // real time clock address
+#define EISA_DISABLE_NMI 0x80 // disable nmi bit
+#define RTC_A_REG 0x0A // status reg a
+#define RTC_B_REG 0x0B // status reg b
+#define RTC_C_REG 0x0C // status reg c
+#define RTC_D_REG 0x0D // status reg d
+
+#define EISA_SYS_EXT_NMI 0x461 // ext NMI control and bus reset
+#define EISA_SW_NMI_PORT 0x462 // software NMI generation port
+#define EISA_BUSMASTER_LSTATUS 0x464 // 32-bit bus master status low
+#define EISA_BUSMASTER_HSTATUS 0x465 // 32-bit bus master status high
+
+#define EISA_BUS_RESET 0x01 // bus reset asserted bit
+#define EISA_ENABLE_NMI_IO 0x02 // NMI I/O port bit
+#define EISA_ENABLE_NMI_SAFE 0x04 // Fail-safe NMI bit
+#define EISA_ENABLE_NMI_32 0x08 // 32-bit bus timeout
+#define EISA_NMI_32_CAUSE 0x10 // 0=slave 1=bus master timeout
+#define EISA_NMI_IO_STATUS 0x20 // NMI I/O port status bit
+#define EISA_NMI_32_STATUS 0x40 // 32-bit bus timeout
+#define EISA_NMI_SAFE_STATUS 0x80 // Fail-save NMI status bit
+#define EISA_WAIT_NMI_TEST 500 // usec.
+
+
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Map Descriptor
+//
+// The following map descriptor is used to describe a specific region in
+// memory mapped through an entry/entries within the TLB (CPU) or within
+// the logical to physical table (bus master).
+///////////////////////////////////////////////////////////////////////////////
+
+
+#define TLB_FW_RES 0x00000020 // 0x20 (even + odd)
+#define TLB_BE_SPT 0x0000001C // TLB entry for the BE SPT
+#define BE_SPT_VIR_ADDR 0x70000000 // BE SPT virtual address
+#define TLB_USER 0x0000001E // user TLB entry (0-based)
+#define USER_VIR_ADDR 0x00000000 // user virtual address
+#define TLB_EISA_START TLB_FW_RES // TLB base for EISA descript.
+#define TLB_EISA_END 0x00000060 // last available TLB + 1
+#define TLB_EISA_NUMB TLB_EISA_END - TLB_EISA_START
+#define EISA_VIR_MEM 0x02000000 // start EISA mem virtual addr.
+#define EISA_MEM_BLOCKS 30 // max memory descriptors
+#define BUS_MASTERS 25 // max bus masters number
+
+#define FW_MD_POOL (BUS_MASTERS + TLB_EISA_NUMB + EISA_MEM_BLOCKS)
+
+
+
+typedef struct _FW_MD_FLAGS
+ {
+ ULONG Busy : 1;
+ } FW_MD_FLAGS, *PFW_MD_FLAGS;
+
+typedef struct _LOG_CONTEXT
+ {
+ ULONG LogAddr; // starting logical address
+ ULONG LogNumb; // # entries to map transfer
+ ULONG LogLimit; // logical limit
+ ULONG LogShift; // page shift (0xC=4k, 2^0xC=4k)
+ PVOID BuffVir; // virtual address buffer
+ } LOG_CONTEXT, *PLOG_CONTEXT;
+
+typedef struct _MEM_CONTEXT
+ {
+ //ULONG BusType; // memory bus type
+ ULONG BusNumber; // key of bus type
+ ULONG SlotNumber; // slot number if applicable
+ ULONG Type; // memory type
+ } MEM_CONTEXT, *PMEM_CONTEXT;
+
+typedef struct _EMEM_CONTEXT
+ {
+ ULONG WinRelAddr; // EISA
+ ULONG WinShift; // window size
+ PVOID WinRelAddrCtrl; // window ctrl port (vir.addr.)
+ } EMEM_CONTEXT, PEMEM_CONTEXT;
+
+typedef struct _FW_MD
+ {
+
+ // general fields
+
+ struct _FW_MD * Link; // next entry
+ FW_MD_FLAGS Flags; // map entry flags
+ ULONG Counter; // # entities sharing this entry
+
+ // physical and virtual address (size of page fixed to 4k)
+
+ ULONG PhysAddr; // physical address (4k)
+ ULONG PagOffs; // page offset (within 4k)
+ PVOID VirAddr; // virtual address
+ ULONG Size; // buffer size in bytes
+ ULONG PagNumb; // buffer in 4k pages
+ BOOLEAN Cache; // cache status
+
+ // private section
+
+ union
+ {
+ LOG_CONTEXT l; // logical context
+ MEM_CONTEXT m; // physical memory context
+ EMEM_CONTEXT em; // EISA memory space
+ } u;
+ } FW_MD, *PFW_MD;
+
+
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+// EISA buses defines
+///////////////////////////////////////////////////////////////////////////////
+
+
+#define EISA_BUSES 1 // number of eisa buses
+
+#ifdef KPW4010
+#define PHYS_0_SLOTS 6 // physical slots (max number)
+#else
+#define PHYS_0_SLOTS 5 // physical slots (max number)
+#endif
+
+#define VIR_0_SLOTS 16 // virtual slots (max number )
+// NOTE: Wait longer for JAZZ.
+//#define EISA_IO_DELAY FwStallExecution(1); // to define !
+#define EISA_IO_DELAY FwStallExecution(4); // to define !
+
+
+// note: the following structs have to be half word aligned
+
+typedef struct _EISA_POD_FLAGS
+ {
+ ULONG IniDone : 1; // POD initialization done
+ ULONG Error : 1; // POD status
+
+ } EISA_POD_FLAGS, *PEISA_POD_FLAGS;
+
+
+typedef struct _EISA_SLOTS_INFO
+ {
+ ULONG PhysSlots; // # of physical slots
+ ULONG VirSlots; // # of virtual slots
+ ULONG SlotCfgMap; // one bit x slot; 1 = slot ok
+
+ } EISA_SLOTS_INFO, *PEISA_SLOTS_INFO;
+
+
+typedef struct _EISA_DMA_FLAGS
+ {
+ UCHAR Busy : 1; // DMA channel busy flag
+ UCHAR Tc : 1; // Terminal count reached
+
+ } EISA_DMA_FLAGS, *PEISA_DMA_FLAGS;
+
+
+typedef struct _EISA_DMA_INFO
+ {
+ EISA_POD_FLAGS Flags; // POD flags
+ EISA_DMA_FLAGS DmaFlags[ EISA_DMAS ]; // DMA status
+ UCHAR DmaExtReg[ EISA_DMAS ]; // DMA extended reg.
+ ULONG TransferAddress[ EISA_DMAS ]; // Logical addresses
+
+ } EISA_DMA_INFO, *PEISA_DMA_INFO;
+
+
+typedef struct _EISA_INT_INFO
+ {
+ EISA_POD_FLAGS Flags; // POD flags
+ USHORT IrqPresent; // IRQ present (1 bit per IRQ)
+ USHORT IrqShareable; // IRQ shareable (1 bit per IRQ)
+ USHORT IrqLevel; // IRQ level (1 bit per IRQ)
+
+ } EISA_INT_INFO, *PEISA_INT_INFO;
+
+
+typedef struct _EISA_PORT_INFO
+ {
+ EISA_POD_FLAGS Flags; // POD flags
+
+ } EISA_PORT_INFO, *PEISA_PORT_INFO;
+
+
+typedef struct _EISA_BUS_INFO
+ {
+ EISA_POD_FLAGS Flags; // Bus Flags
+ PFW_MD IoBusInfo; // EISA I/O bus info
+ PFW_MD MemBusInfo; // EISA memory bus info
+ PEISA_SLOTS_INFO SlotsInfo; // physical slots info
+ PEISA_DMA_INFO DmaInfo; // DMA info struct pointer
+ PEISA_INT_INFO IntInfo; // Interrupts info struct point.
+ PEISA_PORT_INFO PortInfo; // Interrupts info struct point.
+
+ } EISA_BUS_INFO, *PEISA_BUS_INFO;
+
+
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+// EISA call back support
+///////////////////////////////////////////////////////////////////////////////
+
+
+#define STATUS_INT_MASK 0x0000FF01 // Hardware Interrupt Mask
+#define STATUS_IE 0x00000001 // Interrupts enable bit
+#define STATUS_SW0 0x00000100 // Software interrupt
+#define STATUS_SW1 0x00000200 // Software interrupt
+#define STATUS_MCT_ADR 0x00000400 // MCT_ADR interrupt
+#define STATUS_DEVICE 0x00000800 // I/O device interrupt
+#define STATUS_EISA 0x00001000 // EISA device interrupt
+#define STATUS_EISA_NMI 0x00002000 // EISA NMI interrupt
+#define STATUS_EX_TIMER 0x00004000 // Interval timer interrupt
+#define STATUS_IN_TIMER 0x00008000 // Internal timer interrupt
+#define EISA_VECTOR 0x04 // EISA device interrupt vector
+#define EISA_NMI_VECTOR 0x05 // EISA NMI interrupt vector
+
+
+
diff --git a/private/ntos/fw/ppc/ioaccess.h b/private/ntos/fw/ppc/ioaccess.h
new file mode 100644
index 000000000..e6db7c06b
--- /dev/null
+++ b/private/ntos/fw/ppc/ioaccess.h
@@ -0,0 +1,79 @@
+/*++
+
+Copyright (c) 1990 Microsoft Corporation
+
+Module Name:
+
+ ioaccess.h
+
+Abstract:
+
+ This file contains the definitions to read and write IO registers.
+
+Author:
+
+ Lluis Abello (lluis) 1-May-91
+
+Environment:
+
+ Kernel mode
+
+Revision History:
+
+--*/
+
+#ifndef _IOACCESS
+#define _IOACCESS
+//
+// I/O space read and write macros.
+//
+#ifdef R4000
+#undef READ_REGISTER_UCHAR
+#undef READ_REGISTER_USHORT
+#undef READ_REGISTER_ULONG
+#undef WRITE_REGISTER_UCHAR
+#undef WRITE_REGISTER_USHORT
+#undef WRITE_REGISTER_ULONG
+// #define READ_REGISTER_UCHAR(x) NtReadByte(x)
+// #define READ_REGISTER_USHORT(x) NtReadShort(x)
+// #define READ_REGISTER_ULONG(x) NtReadLong(x)
+// #define WRITE_REGISTER_UCHAR(x, y) NtFlushByteBuffer(x,y)
+// #define WRITE_REGISTER_USHORT(x, y) NtFlushShortBuffer(x,y)
+// #define WRITE_REGISTER_ULONG(x, y) NtFlushLongBuffer(x,y)
+#define READ_REGISTER_UCHAR(x) *(volatile UCHAR * const)(x)
+#define READ_REGISTER_USHORT(x) *(volatile USHORT * const)(x)
+#define READ_REGISTER_ULONG(x) *(volatile ULONG * const)(x)
+
+#define WRITE_REGISTER_UCHAR(x, y) *(volatile UCHAR * const)(x) = y
+#define WRITE_REGISTER_USHORT(x, y) *(volatile USHORT * const)(x) = y
+#define WRITE_REGISTER_ULONG(x, y) *(volatile ULONG * const)(x) = y
+
+#endif //R4000
+
+#ifdef R3000
+#undef READ_REGISTER_UCHAR
+#undef READ_REGISTER_USHORT
+#undef READ_REGISTER_ULONG
+#undef WRITE_REGISTER_UCHAR
+#undef WRITE_REGISTER_USHORT
+#undef WRITE_REGISTER_ULONG
+
+#define READ_REGISTER_UCHAR(x) \
+ *(volatile UCHAR * const)(x)
+
+#define READ_REGISTER_USHORT(x) \
+ *(volatile USHORT * const)(x)
+
+#define READ_REGISTER_ULONG(x) \
+ *(volatile ULONG * const)(x)
+
+#define WRITE_REGISTER_UCHAR(x, y) \
+ *(volatile UCHAR * const)(x) = y; FlushWriteBuffer()
+
+#define WRITE_REGISTER_USHORT(x, y) \
+ *(volatile USHORT * const)(x) = y; FlushWriteBuffer()
+
+#define WRITE_REGISTER_ULONG(x, y) \
+ *(volatile ULONG * const)(x) = y; FlushWriteBuffer()
+#endif //R3000
+#endif //_IOACCESS
diff --git a/private/ntos/fw/ppc/iodevice.h b/private/ntos/fw/ppc/iodevice.h
new file mode 100644
index 000000000..00dc19930
--- /dev/null
+++ b/private/ntos/fw/ppc/iodevice.h
@@ -0,0 +1,378 @@
+/*++
+
+Copyright (c) 1990 Microsoft Corporation
+
+Module Name:
+
+ iodevice.h
+
+Abstract:
+
+ This module contains definitions to access the
+ IO devices in the jazz system.
+
+Author:
+
+ Lluis Abello (lluis) 03-Jan-1991
+
+Environment:
+
+
+Revision History:
+
+--*/
+#ifndef _IODEVICE_
+#define _IODEVICE_
+
+#ifdef _PPC_
+#include "ppcdef.h"
+#else
+#ifndef DUO
+#include <jazzprom.h>
+#include <jazzdef.h>
+#else
+#include <duoprom.h>
+#include <duodef.h>
+#endif
+#endif
+
+#include <jazzserp.h>
+#include <eisa.h> // for the isp interrupt controller init.
+#include <jazzrtc.h>
+
+#ifndef DUO
+#include <ncr53c94.h>
+#else
+#include <ncrc700.h>
+
+#define SCSI_READ_UCHAR(ChipAddr,Register) \
+ (READ_REGISTER_UCHAR (&((ChipAddr)->Register)))
+
+#define SCSI_READ_USHORT(ChipAddr,Register) \
+ (READ_REGISTER_USHORT (&((ChipAddr)->Register)))
+
+#define SCSI_READ_ULONG(ChipAddr,Register) \
+ (READ_REGISTER_ULONG (&((ChipAddr)->Register)))
+
+#define SCSI_WRITE_UCHAR(ChipAddr,Register, Value) \
+ WRITE_REGISTER_UCHAR(&((ChipAddr)->Register), (Value))
+
+#define SCSI_WRITE_USHORT(ChipAddr, Register, Value) \
+ WRITE_REGISTER_USHORT(&((ChipAddr)->Register), (Value))
+
+#define SCSI_WRITE_ULONG(ChipAddr, Register, Value) \
+ WRITE_REGISTER_ULONG(&((ChipAddr)->Register), (Value))
+
+#endif
+
+ARC_STATUS
+FwWaitForDeviceInterrupt(
+ USHORT InterruptMask,
+ ULONG Timeout
+ );
+
+//
+// COM controller register pointer definitions.
+//
+#define SP1_READ ((volatile PSP_READ_REGISTERS) COMPORT1_VIRTUAL_BASE)
+#define SP1_WRITE ((volatile PSP_WRITE_REGISTERS)COMPORT1_VIRTUAL_BASE)
+
+#define SP2_READ ((volatile PSP_READ_REGISTERS) COMPORT2_VIRTUAL_BASE)
+#define SP2_WRITE ((volatile PSP_WRITE_REGISTERS)COMPORT2_VIRTUAL_BASE)
+
+//
+// PARALLEL port write registers.
+//
+typedef struct _PARALLEL_WRITE_REGISTERS {
+ UCHAR Data;
+ UCHAR Invalid;
+ UCHAR Control;
+ } PARALLEL_WRITE_REGISTERS, * PPARALLEL_WRITE_REGISTERS;
+
+//
+// PARALLEL port read Registers
+//
+
+typedef struct _PARALLEL_READ_REGISTERS {
+ UCHAR Data;
+ UCHAR Status;
+ UCHAR Control;
+ } PARALLEL_READ_REGISTERS,* PPARALLEL_READ_REGISTERS;
+
+//
+// PARALLEL controller register pointer definitions.
+//
+
+#define PARALLEL_READ ((volatile PPARALLEL_READ_REGISTERS) PARALLEL_VIRTUAL_BASE)
+#define PARALLEL_WRITE ((volatile PPARALLEL_WRITE_REGISTERS)PARALLEL_VIRTUAL_BASE)
+
+//
+// FLOPPY read registers.
+//
+
+typedef struct _FLOPPY_READ_REGISTERS {
+ UCHAR StatusA;
+ UCHAR StatusB;
+ UCHAR DigitalOutput;
+ UCHAR Reserved1;
+ UCHAR MainStatus;
+ UCHAR Fifo;
+ UCHAR Reserved2;
+ UCHAR DigitalInput;
+ } FLOPPY_READ_REGISTERS, * PFLOPPY_READ_REGISTERS;
+
+//
+// FLOPPY write registers.
+//
+
+typedef struct _FLOPPY_WRITE_REGISTERS {
+ UCHAR StatusA;
+ UCHAR StatusB;
+ UCHAR DigitalOutput;
+ UCHAR Reserved1;
+ UCHAR DataRateSelect;
+ UCHAR Fifo;
+ UCHAR Reserved2;
+ UCHAR ConfigurationControl;
+ } FLOPPY_WRITE_REGISTERS, * PFLOPPY_WRITE_REGISTERS ;
+
+//
+// FLOPPY controller register pointer definitions.
+//
+
+
+#define FLOPPY_READ ((volatile PFLOPPY_READ_REGISTERS)FLOPPY_VIRTUAL_BASE)
+#define FLOPPY_WRITE ((volatile PFLOPPY_WRITE_REGISTERS)FLOPPY_VIRTUAL_BASE)
+
+//
+// SOUND controller register pointer definitions.
+//
+typedef struct _SOUND_REGISTERS {
+ USHORT Control;
+ USHORT Mode;
+} SOUND_REGISTERS,* PSOUND_REGISTERS;
+
+typedef struct _SOUND_CONTROL {
+ USHORT SoundEnable : 1;
+ USHORT Direction : 1;
+ USHORT ChannelInUse : 1;
+ USHORT Reserved1 : 11;
+ USHORT TerminalCountInterrupt : 1;
+ USHORT DeviceInterrupt : 1;
+} SOUND_CONTROL, *PSOUND_CONTROL;
+
+#define DIRECTION_ACQUISITION 0
+#define DIRECTION_PLAYBACK 1
+
+#define CHANNEL2_IN_USE 0
+#define CHANNEL3_IN_USE 1
+
+typedef struct _SOUND_MODE {
+ USHORT Frequency : 2;
+ USHORT Reserved1 : 1;
+ USHORT Resolution : 1;
+ USHORT Reserved2 : 1;
+ USHORT NumberOfChannels : 1;
+ USHORT Reserved3 : 10;
+} SOUND_MODE, *PSOUND_MODE;
+
+#define CHANNEL_MONO 0
+#define CHANNEL_STEREO 1
+
+#define RESOLUTION_16BIT 1
+#define RESOLUTION_8BIT 0
+
+#define FREQUENCY_11KHZ 0
+#define FREQUENCY_22KHZ 1
+#define FREQUENCY_44KHZ 2
+#define FREQUENCY_DISABLED 3
+
+#define SOUND_CONTROL ((volatile PSOUND_REGISTERS) SOUND_VIRTUAL_BASE)
+
+
+//
+// cursor controller register pointer definitions.
+//
+
+#define CURSOR_CONTROLLER ((volatile PCURSOR_REGISTERS) (VIDEO_CURSOR_VIRTUAL_BASE))
+#define VIDEO_CONTROLLER ((volatile PVIDEO_REGISTERS) (VIDEO_CONTROL_VIRTUAL_BASE))
+
+//
+// KEYBOARD write registers.
+//
+typedef struct _KEYBOARD_WRITE_REGISTERS {
+ UCHAR Data;
+ UCHAR Command;
+ } KEYBOARD_WRITE_REGISTERS, * PKEYBOARD_WRITE_REGISTERS;
+
+//
+// KEYBOARD read Registers
+//
+
+typedef struct _KEYBOARD_READ_REGISTERS {
+ UCHAR Data;
+ UCHAR Status;
+ } KEYBOARD_READ_REGISTERS, * PKEYBOARD_READ_REGISTERS;
+
+//
+// KEYBOARD controller register pointer definitions.
+//
+#define KEYBOARD_READ ((volatile PKEYBOARD_READ_REGISTERS) KEYBOARD_VIRTUAL_BASE)
+#define KEYBOARD_WRITE ((volatile PKEYBOARD_WRITE_REGISTERS) KEYBOARD_VIRTUAL_BASE)
+
+//
+// Keyboard circular buffer type definition.
+//
+#define KBD_BUFFER_SIZE 32
+
+typedef struct _KEYBOARD_BUFFER {
+ volatile UCHAR Buffer[KBD_BUFFER_SIZE];
+ volatile UCHAR ReadIndex;
+ volatile UCHAR WriteIndex;
+} KEYBOARD_BUFFER, *PKEYBOARD_BUFFER;
+
+
+#define TIME_OUT 0xdead
+
+//
+// SONIC registers definition.
+//
+typedef struct _SONIC_REGISTER { // Structure to align the registers
+ USHORT Reg;
+ USHORT Fill;
+ } SONIC_REGISTER;
+
+typedef struct _SONIC_REGISTERS {
+ SONIC_REGISTER Command; // 0
+ SONIC_REGISTER DataConfiguration; // 1
+ SONIC_REGISTER ReceiveControl; // 2
+ SONIC_REGISTER TransmitControl; // 3
+ SONIC_REGISTER InterruptMask; // 4
+ SONIC_REGISTER InterruptStatus; // 5
+ SONIC_REGISTER UTDA; // 6
+ SONIC_REGISTER CTDA; // 7
+ SONIC_REGISTER InternalTPS; // 8
+ SONIC_REGISTER InternalTFC; // 9
+ SONIC_REGISTER InternalTSA0; // A
+ SONIC_REGISTER InternalTSA1; // B
+ SONIC_REGISTER InternalTFS; // C
+ SONIC_REGISTER URDA; // D
+ SONIC_REGISTER CRDA; // E
+ SONIC_REGISTER InternalCRBA0; // F
+ SONIC_REGISTER InternalCRBA1; //10
+ SONIC_REGISTER InternalRWBC0; //11
+ SONIC_REGISTER InternalRBWC1; //12
+ SONIC_REGISTER EOBC; //13
+ SONIC_REGISTER URRA; //14
+ SONIC_REGISTER RSA; //15
+ SONIC_REGISTER REA; //16
+ SONIC_REGISTER RRP; //17
+ SONIC_REGISTER RWP; //18
+ SONIC_REGISTER InternalTRBA0; //19
+ SONIC_REGISTER InternalTRBA1; //1A
+ SONIC_REGISTER InternalTBWC0; //1B
+ SONIC_REGISTER InternalTBWC1; //1C
+ SONIC_REGISTER InternalADDR0; //1D
+ SONIC_REGISTER InternalADDR1; //1E
+ SONIC_REGISTER InternalLLFA; //1F
+ SONIC_REGISTER InternalTTDA; //20
+ SONIC_REGISTER CamEntryPtr; //21
+ SONIC_REGISTER CamAddrPort2; //22
+ SONIC_REGISTER CamAddrPort1; //23
+ SONIC_REGISTER CamAddrPort0; //24
+ SONIC_REGISTER CamEnable; //25
+ SONIC_REGISTER CamDscrPtr; //26
+ SONIC_REGISTER CamDscrCount; //27
+ SONIC_REGISTER SiliconRevision; //28
+ SONIC_REGISTER WatchdogTimer0; //29
+ SONIC_REGISTER WatchdogTimer1; //2A
+ SONIC_REGISTER ReceiveSequenceCounter; //2B
+ SONIC_REGISTER CrcErrorTally; //2C
+ SONIC_REGISTER FaeTally; //2D
+ SONIC_REGISTER MissedPacketTally; //2E
+ SONIC_REGISTER InternalMDT; //2F
+// registers 30 to 3F are Test registers and must not be accessed
+// registers nammed "internal" must not be accessed either.
+ } SONIC_REGISTERS, * PSONIC_REGISTERS;
+
+//
+// SONIC register pointer definitions.
+//
+
+#define SONIC ((volatile PSONIC_REGISTERS) NET_VIRTUAL_BASE)
+
+ //
+// NVRAM address definitions.
+//
+#define NVRAM_PAGE0 NVRAM_VIRTUAL_BASE
+#define NVRAM_PAGE1 (NVRAM_VIRTUAL_BASE+0x1000)
+#define NVRAM_PAGE2 (NVRAM_VIRTUAL_BASE+0x2000)
+
+#define READ_ONLY_DISABLE_WRITE 0x6 // clear lower bit of Security register.
+
+//
+// EISA Stuff
+// ***** temp **** this should be replaced by the definition in
+// "ntos\inc\eisa.h" as soon as it is complete.
+//
+
+typedef struct _EISA {
+ UCHAR Dma1Ch0Address; //0x00
+ UCHAR Dma1Ch0Count; //0x01
+ UCHAR Dma1Ch1Address; //0x02
+ UCHAR Dma1Ch1Count; //0x03
+ UCHAR Dma1Ch2Address; //0x04
+ UCHAR Dma1Ch2Count; //0x05
+ UCHAR Dma1Ch3Address; //0x06
+ UCHAR Dma1Ch3Count; //0x07
+ UCHAR Dma1StatusCommand; //0x08
+ UCHAR Dma1Request; //0x09
+ UCHAR Dma1SingleMask; //0x0a
+ UCHAR Dma1Mode; //0x0b
+ UCHAR Dma1ClearBytePointer; //0x0c
+ UCHAR Dma1MasterClear; //0x0d
+ UCHAR Dma1ClearMask; //0x0e
+ UCHAR Dma1AllMask; //0x0f
+ ULONG Fill01; //0x10-13
+ ULONG Fill02; //0x14-17
+ ULONG Fill03; //0x18-1b
+ ULONG Fill04; //0x1c-1f
+ UCHAR Int1Control; //0x20
+ UCHAR Int1Mask; //0x21
+ USHORT Fill10; //0x22-23
+ ULONG Fill11; //0x24
+ ULONG Fill12; //0x28
+ ULONG Fill13; //0x2c
+ ULONG Fill14; //0x30
+ ULONG Fill15; //0x34
+ ULONG Fill16; //0x38
+ ULONG Fill17; //0x3c
+ UCHAR IntTimer1SystemClock; //0x40
+ UCHAR IntTimer1RefreshRequest; //0x41
+ UCHAR IntTimer1SpeakerTone; //0x42
+ UCHAR IntTimer1CommandMode; //0x43
+ ULONG Fill20; //0x44
+ UCHAR IntTimer2FailsafeClock; //0x48
+ UCHAR IntTimer2Reserved; //0x49
+ UCHAR IntTimer2CPUSpeeedCtrl; //0x4a
+ UCHAR IntTimer2CommandMode; //0x4b
+ ULONG Fill30; //0x4c
+ ULONG Fill31; //0x50
+ ULONG Fill32; //0x54
+ ULONG Fill33; //0x58
+ ULONG Fill34; //0x5c
+ UCHAR Fill35; //0x60
+ UCHAR NMIStatus; //0x61
+ UCHAR Fill40; //0x62
+ UCHAR Fill41; //0x63
+ ULONG Fill42; //0x64
+ ULONG Fill43; //0x68
+ ULONG Fill44; //0x6c
+ UCHAR NMIEnable; //0x70
+ }EISA, * PEISA;
+
+#define ISP ((volatile PEISA) EISA_IO_VIRTUAL_BASE)
+
+#define EISA_CONTROL ((volatile PEISA_CONTROL) EISA_IO_VIRTUAL_BASE)
+
+#endif // _IODEVICE_
diff --git a/private/ntos/fw/ppc/j4reset.h b/private/ntos/fw/ppc/j4reset.h
new file mode 100644
index 000000000..4a543dc5c
--- /dev/null
+++ b/private/ntos/fw/ppc/j4reset.h
@@ -0,0 +1,115 @@
+/*++
+
+Copyright (c) 1990 Microsoft Corporation
+
+Module Name:
+
+ j4reset.h
+
+Abstract:
+
+ This module defines various parameters for the reset module.
+
+Author:
+
+ Lluis Abello (lluis) 10-Jan-1991
+
+Revision History:
+
+--*/
+
+#ifndef _J4RESET_
+#define _J4RESET_
+
+//TEMPTEMP
+#define SECONDARY_CACHE_SIZE (1 << 20)
+#define SECONDARY_CACHE_INVALID 0x0
+#define TAGLO_SSTATE 0xA
+#define INDEX_FILL_I 0x14 // ****** temp ****** this must be moved to kxmips.h
+#define HIT_WRITEBACK_I 0x18 // ****** temp ****** this must be moved to kxmips.h
+
+//
+// redefine bal to be a relative branch and link instead of jal as it's
+// defined in kxmips.h. This allows calling routines when running in either
+// ROM_VIRT Addresses or ResetVector Addresses.
+// The cpp will issue a redefinition warning message.
+//
+#define bal bgezal zero,
+
+//
+// #define MCTADR register values.
+//
+
+//
+// Mctadr register reset values.
+//
+#ifndef DUO
+#define CONFIG_RESET_MCTADR_REV1 0x104
+#define CONFIG_RESET_MCTADR_REV2 0x410
+#define REMSPEED_RESET 0x7
+#define REFRRATE_RESET 0x18186
+#define SECURITY_RESET 0x7
+#else
+#define CONFIG_RESET_MP_ADR_REV1 0x4
+#define REMSPEED_RESET 0x7
+#define REFRRATE_RESET 0x18186
+#define SECURITY_RESET 0x7
+#endif
+
+//
+// Define remspeed registers.
+//
+#ifndef DUO
+#define REMSPEED0 7 // reserved
+#define REMSPEED1 0 // Ethernet
+#define REMSPEED2 1 // scsi
+#define REMSPEED3 2 // floppy
+#define REMSPEED4 7 // rtc
+#define REMSPEED5 3 // kbd/mouse
+#define REMSPEED6 2 // serial 1
+#define REMSPEED7 2 // serial 2
+#define REMSPEED8 2 // parallel
+#define REMSPEED9 4 // nvram
+#define REMSPEED10 1 // interrupt src
+#define REMSPEED11 2 // PROM (should be 4)
+#define REMSPEED12 1 // sound
+#define REMSPEED13 7 // new device
+#define REMSPEED14 1 // EISA latch
+#define REMSPEED15 1 // led
+#else
+#define REMSPEED0 7 // reserved
+#define REMSPEED1 0 // Ethernet
+#define REMSPEED2 0 // scsi
+#define REMSPEED3 0 // scsi
+#define REMSPEED4 7 // rtc
+#define REMSPEED5 3 // kbd/mouse
+#define REMSPEED6 2 // serial 1
+#define REMSPEED7 2 // serial 2
+#define REMSPEED8 2 // parallel
+#define REMSPEED9 4 // nvram
+#define REMSPEED10 3 // interrupt src
+#define REMSPEED11 3 // PROM (should be 4)
+#define REMSPEED12 7 // new device
+#define REMSPEED13 7 // new device
+#define REMSPEED14 1 // LED
+#endif
+
+
+//
+// Define the refresh rate. This value is 32/50th of the the reset value
+// because we are currently running at 32MHz
+//
+#ifndef DUO
+#define MEMORY_REFRESH_RATE 0x18186
+#else
+#define MEMORY_REFRESH_RATE 0x38186
+#endif
+
+
+#define PROM_BASE (KSEG1_BASE | 0x1fc00000)
+#define PROM_ENTRY(x) (PROM_BASE + ((x) * 8))
+
+#define DMA_CHANNEL_GAP 0x20 // distance beetwen DMA channels
+
+
+#endif // _J4RESET_
diff --git a/private/ntos/fw/ppc/jxfwhal.h b/private/ntos/fw/ppc/jxfwhal.h
new file mode 100644
index 000000000..53993d94b
--- /dev/null
+++ b/private/ntos/fw/ppc/jxfwhal.h
@@ -0,0 +1,94 @@
+/*++ BUILD Version: 0001 // Increment this if a change has global effects
+
+Copyright (c) 1991 Microsoft Corporation
+
+Module Name:
+
+ jxfwhal.h
+
+Abstract:
+
+ This header file defines the private Hardware Architecture Layer (HAL)
+ Jazz specific interfaces, defines and structures.
+
+Author:
+
+ Jeff Havens (jhavens) 09-Aug-91
+
+
+Revision History:
+
+--*/
+
+#ifndef _JXFWHAL_
+#define _JXFWHAL_
+
+
+//
+// Define global data used to locate the EISA control space and the realtime
+// clock registers.
+//
+
+extern PVOID HalpEisaControlBase;
+extern PVOID HalpRealTimeClockBase;
+
+//
+// Define adapter object structure.
+//
+
+typedef struct _ADAPTER_OBJECT {
+ CSHORT Type;
+ CSHORT Size;
+ ULONG MapRegistersPerChannel;
+ PVOID AdapterBaseVa;
+ PVOID MapRegisterBase;
+ ULONG NumberOfMapRegisters;
+ BOOLEAN AdapterInUse;
+ UCHAR ChannelNumber;
+ UCHAR AdapterNumber;
+ UCHAR AdapterMode;
+ PUCHAR PagePort;
+} ADAPTER_OBJECT;
+
+//
+// Define function prototypes.
+//
+
+PADAPTER_OBJECT
+HalpAllocateEisaAdapter(
+ IN PDEVICE_DESCRIPTION DeviceDescription
+ );
+
+BOOLEAN
+HalpCreateEisaStructures(
+ VOID
+ );
+
+VOID
+HalpDisableEisaInterrupt(
+ IN CCHAR Vector
+ );
+
+BOOLEAN
+HalpEisaDispatch(
+ IN PKINTERRUPT Interrupt,
+ IN PVOID ServiceContext
+ );
+
+VOID
+HalpEisaMapTransfer(
+ IN PADAPTER_OBJECT AdapterObject,
+ IN ULONG Offset,
+ IN ULONG Length,
+ IN BOOLEAN WriteToDevice
+ );
+
+VOID
+HalpEnableEisaInterrupt(
+ IN CCHAR Vector,
+ IN KINTERRUPT_MODE InterruptMode
+ );
+
+#define HalpAllocateEisaAdapter(DeviceDescritption) NULL
+
+#endif // _JXFWHAL_
diff --git a/private/ntos/fw/ppc/jxvideo.h b/private/ntos/fw/ppc/jxvideo.h
new file mode 100644
index 000000000..bf98df674
--- /dev/null
+++ b/private/ntos/fw/ppc/jxvideo.h
@@ -0,0 +1,158 @@
+/*++
+
+Copyright (c) 1989 Microsoft Corporation
+
+Module Name:
+
+ jxvideo.h
+
+Abstract:
+
+ This module implements contains definitions for the interface with
+ the video prom initialization code.
+
+
+Author:
+
+ Lluis Abello (lluis) 16-Jul-1992
+
+Environment:
+
+ Kernel mode.
+
+
+Revision History:
+
+--*/
+
+#ifndef _JXVIDEO_
+
+#define _JXVIDEO_
+
+// The video PROM contains the following structure starting at offset zero
+// from the PROM base address. Each entry is 8 bytes wide with the low byte
+// containing data and the upper 7 bytes reserved.
+//
+// 63 8 7 0 Offset
+// +------------------+ +------------------+
+// | reserved | | Board_Identifier | 0x00
+// +------------------+ +------------------+
+// | reserved | | PROM_Stride | 0x08
+// +------------------+ +------------------+
+// | reserved | | PROM_Width | 0x10
+// +------------------+ +------------------+
+// | reserved | | PROM_Size | 0x18
+// +------------------+ +------------------+
+// | reserved | | Test_Byte_0 | 0x20
+// +------------------+ +------------------+
+// | reserved | | Test_Byte_1 | 0x28
+// +------------------+ +------------------+
+// | reserved | | Test_Byte_2 | 0x30
+// +------------------+ +------------------+
+// | reserved | | Test_Byte_3 | 0x38
+// +------------------+ +------------------+
+//
+//
+// Board_Identifier - supplies two bytes identifying the video board.
+//
+// PROM_Stride - supplies the stride of the PROM in bytes. Possible
+// values are:
+//
+// 1 - data every byte
+// 2 - data every 2 bytes
+// 4 - data every 4 bytes
+// 8 - data every 8 bytes
+//
+// PROM_Width - supplies the width of the PROM in bytes. Possible values
+// are:
+//
+// 1 - 1 byte wide
+// 2 - 2 bytes wide
+// 4 - 4 bytes wide
+// 8 - 8 bytes wide
+//
+// PROM_Size - supplies the size of the PROM in 4 KByte pages.
+//
+// Test_Bytes_[3:0] - supplies a test pattern ("Jazz").
+//
+// This strucure viewed from the video prom, i.e. the system
+//prom reads it taking into account PROM_Stride and PROM_Width
+//follows:
+//
+//typedef struct _VIDEO_PROM_CONFIGURATION {
+// ULONG VideoMemorySize;
+// ULONG VideoControlSize;
+// ULONG CodeOffset;
+// ULONG CodeSize;
+//} VIDEO_PROM_CONFIGURATION; *PVIDEO_PROM_CONFIGURATION;
+//
+//
+// VideoMemorySize - Supplies the size of video memory in bytes
+//
+// VideoControlSize - Supplies the size of video control in bytes
+//
+// CodeOffset - Supplies the offset in bytes from the beginning
+// of the video prom to the first byte of code which
+// is also the entry point of the initialization routine.
+//
+// CodeSize - Supplies the size of the code in bytes.
+//
+//
+//
+// Following this structure there is a IdentifierString -
+// Zero terminated string that identifies the video card "JazzG364", "
+// JazzVXL" ...
+
+
+
+typedef struct _VIDEO_PROM_CONFIGURATION {
+ ULONG VideoMemorySize;
+ ULONG VideoControlSize;
+ ULONG CodeOffset;
+ ULONG CodeSize;
+} VIDEO_PROM_CONFIGURATION, *PVIDEO_PROM_CONFIGURATION;
+
+
+typedef struct _VIDEO_VIRTUAL_SPACE {
+ ULONG MemoryVirtualBase;
+ ULONG ControlVirtualBase;
+} VIDEO_VIRTUAL_SPACE, *PVIDEO_VIRTUAL_SPACE;
+
+typedef
+ARC_STATUS
+(*PVIDEO_INITIALIZE_ROUTINE) (
+ IN PVIDEO_VIRTUAL_SPACE VideoAdr,
+ IN PMONITOR_CONFIGURATION_DATA VideoConfig
+ );
+
+#define InitializeVideo(VideoAdr, VideoConfig) \
+ ((PVIDEO_INITIALIZE_ROUTINE)(VIDEO_PROM_CODE_VIRTUAL_BASE)) \
+ ((VideoAdr), (VideoConfig))
+
+ARC_STATUS
+InitializeVideoFromProm(
+ IN PMONITOR_CONFIGURATION_DATA Monitor
+ );
+
+//
+// Define colors, HI = High Intensity
+//
+
+#define FW_COLOR_BLACK 0x00
+#define FW_COLOR_RED 0x01
+#define FW_COLOR_GREEN 0x02
+#define FW_COLOR_YELLOW 0x03
+#define FW_COLOR_BLUE 0x04
+#define FW_COLOR_MAGENTA 0x05
+#define FW_COLOR_CYAN 0x06
+#define FW_COLOR_WHITE 0x07
+#define FW_COLOR_HI_BLACK 0x08
+#define FW_COLOR_HI_RED 0x09
+#define FW_COLOR_HI_GREEN 0x0A
+#define FW_COLOR_HI_YELLOW 0x0B
+#define FW_COLOR_HI_BLUE 0x0C
+#define FW_COLOR_HI_MAGENTA 0x0D
+#define FW_COLOR_HI_CYAN 0x0E
+#define FW_COLOR_HI_WHITE 0x0F
+
+#endif
diff --git a/private/ntos/fw/ppc/jzsetup.h b/private/ntos/fw/ppc/jzsetup.h
new file mode 100644
index 000000000..bc675fce8
--- /dev/null
+++ b/private/ntos/fw/ppc/jzsetup.h
@@ -0,0 +1,155 @@
+/*++
+
+Copyright (c) 1991 Microsoft Corporation
+
+Module Name:
+
+ jzsetup.h
+
+Abstract:
+
+ This module contains the definitions for the Jazz setup program.
+
+Author:
+
+ David M. Robinson (davidro) 25-Oct-1991
+
+Revision History:
+
+--*/
+
+#ifndef _JZSETUP_
+#define _JZSETUP_
+
+
+#include "fwp.h"
+#include "jazzvdeo.h"
+#include "jazzrtc.h"
+#include "string.h"
+#include "iodevice.h"
+#include "jzstring.h"
+
+#define KeFlushWriteBuffer()
+
+#define MAX_NUMBER_OF_ENVIRONMENT_VARIABLES 20
+
+#define EISA_NMI 0x70
+
+extern PCHAR BootString[];
+extern ULONG ScsiHostId;
+
+typedef enum _BOOT_VARIABLES {
+ LoadIdentifierVariable,
+ SystemPartitionVariable,
+ OsLoaderVariable,
+ OsLoadPartitionVariable,
+ OsLoadFilenameVariable,
+ OsLoadOptionsVariable,
+ MaximumBootVariable
+ } BOOT_VARIABLE;
+
+
+//
+// Print macros.
+//
+
+#define JzClearScreen() \
+ JzPrint("%c2J", ASCII_CSI)
+
+#define JzSetScreenColor(FgColor, BgColor) \
+ JzPrint("%c3%dm", ASCII_CSI, (UCHAR)FgColor); \
+ JzPrint("%c4%dm", ASCII_CSI, (UCHAR)BgColor)
+
+#define JzSetScreenAttributes( HighIntensity, Underscored, ReverseVideo ) \
+ JzPrint("%c0m", ASCII_CSI); \
+ if (HighIntensity) { \
+ JzPrint("%c1m", ASCII_CSI); \
+ } \
+ if (Underscored) { \
+ JzPrint("%c4m", ASCII_CSI); \
+ } \
+ if (ReverseVideo) { \
+ JzPrint("%c7m", ASCII_CSI); \
+ }
+
+#define JzSetPosition( Row, Column ) \
+ JzPrint("%c%d;", ASCII_CSI, (Row + 1)); \
+ JzPrint("%dH", (Column + 1))
+
+#define JzStallExecution( Wait ) \
+ { \
+ ULONG HackStall; \
+ for (HackStall = 0;HackStall < (Wait << 4);HackStall++) { \
+ } \
+ }
+
+
+
+//
+// Routine prototypes.
+//
+
+VOID
+JzSetEthernet (
+ VOID
+ );
+
+VOID
+JzSetTime (
+ VOID
+ );
+
+VOID
+JzShowTime (
+ BOOLEAN First
+ );
+
+BOOLEAN
+JzMakeDefaultConfiguration (
+ VOID
+ );
+
+VOID
+JzMakeDefaultEnvironment (
+ VOID
+ );
+
+VOID
+JzAddBootSelection (
+ VOID
+ );
+
+VOID
+JzDeleteBootSelection (
+ VOID
+ );
+
+BOOLEAN
+JzSetBootEnvironmentVariable (
+ IN ULONG CurrentBootSelection
+ );
+
+BOOLEAN
+JzSetEnvironmentVariable (
+ VOID
+ );
+
+VOID
+JzAddNetwork(
+ PCONFIGURATION_COMPONENT Parent
+ );
+
+VOID
+JzDeleteVariableSegment (
+ PCHAR VariableName,
+ ULONG Selection
+ );
+
+ULONG
+JzGetSelection(
+ IN PCHAR Menu[],
+ IN ULONG NumberOfChoices,
+ IN ULONG DefaultChoice
+ );
+
+#endif // _JZSETUP_
diff --git a/private/ntos/fw/ppc/jzstring.h b/private/ntos/fw/ppc/jzstring.h
new file mode 100644
index 000000000..c2958bdab
--- /dev/null
+++ b/private/ntos/fw/ppc/jzstring.h
@@ -0,0 +1,101 @@
+//
+// Common strings.
+//
+
+extern PCHAR JZ_CRLF_MSG;
+
+//
+// Prompt strings.
+//
+
+extern PCHAR JZ_COUNTDOWN_MSG;
+extern PCHAR JZ_OSLOADER_MSG;
+extern PCHAR JZ_OS_MSG;
+extern PCHAR JZ_OS_ROOT_MSG;
+extern PCHAR JZ_BOOT_NAME_MSG;
+extern PCHAR JZ_INIT_DEBUG_MSG;
+extern PCHAR JZ_CANT_SET_VARIABLE_MSG;
+extern PCHAR JZ_NO_SELECTIONS_TO_DELETE_MSG;
+extern PCHAR JZ_SELECTION_TO_DELETE_MSG;
+extern PCHAR JZ_ENVIR_FOR_BOOT_MSG;
+extern PCHAR JZ_FORMAT1_MSG;
+extern PCHAR JZ_USE_ARROWS_MSG;
+extern PCHAR JZ_NO_SELECTIONS_TO_EDIT_MSG;
+extern PCHAR JZ_SELECTION_TO_EDIT_MSG;
+extern PCHAR JZ_NO_SELECTIONS_TO_REARRANGE_MSG;
+extern PCHAR JZ_PICK_SELECTION_MSG;
+extern PCHAR JZ_SHOULD_AUTOBOOT_MSG;
+extern PCHAR JZ_ENVIRONMENT_VARS_MSG;
+extern PCHAR JZ_CHECKING_BOOT_SEL_MSG;
+extern PCHAR JZ_VARIABLE_NULL_MSG;
+extern PCHAR JZ_CANT_BE_FOUND_MSG;
+extern PCHAR JZ_PROBLEMS_FOUND_MSG;
+extern PCHAR JZ_PRESS_KEY_MSG;
+extern PCHAR JZ_PRESS_KEY2_MSG;
+extern PCHAR JZ_NAME_MSG;
+extern PCHAR JZ_VALUE_MSG;
+extern PCHAR JZ_NO_NVRAM_SPACE_MSG;
+extern PCHAR JZ_NVRAM_CHKSUM_MSG;
+extern PCHAR JZ_CURRENT_ENET_MSG;
+extern PCHAR JZ_NEW_ENET_MSG;
+extern PCHAR JZ_WRITTEN_ENET_MSG;
+extern PCHAR JZ_FOUND_NET_MSG;
+extern PCHAR JZ_FIXED_MSG;
+extern PCHAR JZ_NOT_FIXED_MSG;
+extern PCHAR JZ_INVALID_ENET_MSG;
+extern PCHAR JZ_SELECT_MEDIA_MSG;
+extern PCHAR JZ_ENTER_FAT_PART_MSG;
+extern PCHAR JZ_ENTER_PART_MSG;
+extern PCHAR JZ_SELECT_SYS_PART_MSG;
+extern PCHAR JZ_SCSI_HD_MSG;
+extern PCHAR JZ_SCSI_FL_MSG;
+extern PCHAR JZ_SCSI_CD_MSG;
+extern PCHAR JZ_NEW_SYS_PART_MSG;
+extern PCHAR JZ_LOCATE_SYS_PART_MSG;
+extern PCHAR JZ_ENTER_SCSI_ID_MSG;
+extern PCHAR JZ_LOCATE_OS_PART_MSG;
+extern PCHAR JZ_MONITOR_RES_MSG;
+extern PCHAR JZ_FLOPPY_SIZE_MSG;
+extern PCHAR JZ_2ND_FLOPPY_MSG;
+extern PCHAR JZ_SCSI_HOST_MSG;
+extern PCHAR JZ_CLEAR_CONFIG_MSG;
+extern PCHAR JZ_ADD_CONFIG_MSG;
+extern PCHAR JZ_ADD_ENVIR_MSG;
+extern PCHAR JZ_SAVE_CONFIG_MSG;
+extern PCHAR JZ_DONE_CONFIG_MSG;
+extern PCHAR JZ_DEFAULT_SYS_PART_MSG;
+extern PCHAR JZ_ENTER_DATE_MSG;
+extern PCHAR JZ_ENTER_TIME_MSG;
+extern PCHAR JZ_ILLEGAL_TIME_MSG;
+extern PCHAR JZ_PM;
+extern PCHAR JZ_AM;
+
+//
+// Menus.
+//
+
+extern PCHAR ProblemChoices[];
+#define NUMBER_OF_PROBLEMS 3
+
+extern PCHAR YesNoChoices[];
+#define NUMBER_OF_YES_NO 2
+
+extern PCHAR MediaChoices[];
+#define NUMBER_OF_MEDIA 3
+
+extern PCHAR JzBootChoices[];
+#define NUMBER_OF_JZ_BOOT_CHOICES 7
+
+extern PCHAR ResolutionChoices[];
+#define NUMBER_OF_RESOLUTIONS 4
+
+extern PCHAR FloppyChoices[];
+#define NUMBER_OF_FLOPPIES 2
+
+extern PCHAR Weekday[];
+
+extern PCHAR JzSetupChoices[];
+#define NUMBER_OF_JZ_SETUP_CHOICES 3
+
+PCHAR ConfigurationChoices[];
+#define NUMBER_OF_CONFIGURATION_CHOICES 7
diff --git a/private/ntos/fw/ppc/kbdmouse.h b/private/ntos/fw/ppc/kbdmouse.h
new file mode 100644
index 000000000..b22543d77
--- /dev/null
+++ b/private/ntos/fw/ppc/kbdmouse.h
@@ -0,0 +1,149 @@
+/*++
+
+Copyright (c) 1990 Microsoft Corporation
+
+Module Name:
+
+ Kbdmouse.h
+
+Abstract:
+
+ This module contains definitions for the keyboard controller
+ in the jazz system.
+
+ It supports Mouse and Keyboard.
+
+Author:
+
+ Lluis Abello (lluis) 11-Jul-1990
+
+Environment:
+
+
+Revision History:
+
+--*/
+
+#ifndef _KBDMOUSE_
+#define _KBDMOUSE_
+//
+// Keyboard Controller Commands
+//
+#define KBD_CTR_WRITE_COMMAND 0x60
+#define KBD_CTR_READ_COMMAND 0x20
+#define KBD_CTR_TEST_PASSWORD 0xA4
+#define KBD_CTR_LOAD_PASSWORD 0xA5
+#define KBD_CTR_ENABLE_PASSWORD 0xA6
+#define KBD_CTR_DISABLE_AUX 0xA7
+#define KBD_CTR_ENABLE_AUX 0xA8
+#define KBD_CTR_AUXLINES_TEST 0xA9
+#define KBD_CTR_SELFTEST 0xAA
+#define KBD_CTR_KBDLINES_TEST 0xAB
+#define KBD_CTR_ENABLE_KBD 0xAE
+#define KBD_CTR_WRITE_AUX 0xD4
+
+//
+// Keyboard Controller Data
+//
+#define Kbd_Ctr_Selftest_Passed 0x55
+#define Kbd_Ctr_Password_Installed 0xFA
+#define Kbd_Ctr_Password_Not_Installed 0xF1
+
+//
+// Controller Command Byte bit definitions.
+//
+#define KbdCommandByteDisableAux (1 << 5)
+#define KbdCommandByteDisableKbd (1 << 4)
+#define KbdCommandEnableAuxInt (1 << 1)
+#define KbdCommandEnableKbdInt (1 << 0)
+
+//
+// Keyboard Controller Status byte masks
+//
+#define KBD_OBF_MASK 0x1 // Output buffer full
+#define KBD_IBF_MASK 0x2 // Input buffer full
+#define KBD_FROM_AUX_MASK 0x20 // Byte from Aux Port.
+
+//
+// Interface Test Results
+//
+#define INTERFACE_NO_ERROR 0x00
+#define CLOCK_STUCK_LOW 0x01
+#define CLOCK_STUCK_HIGH 0x02
+#define DATA_STUCK_LOW 0x03
+#define DATA_STUCK_HIGH 0x04
+
+//
+// Timeout
+//
+#define KBD_TIMEOUT 0xFFFFF
+#define KBD_INT_TIMEOUT 0xFFFF
+
+//
+// Keyboard Commands
+//
+#define KbdEcho 0xee // request keyboard to return echo response "EE"
+#define KbdSelScanCode 0xf0 // Scan codes 1,2,3 or 0 = rquest current.
+#define KbdReadID 0xf2 // Request for two byte response
+#define KbdSetRate 0xf3 // Set tellematic Rate
+#define KbdEnable 0xF4 // Clears Buffer and Starts Scanning.
+#define KbdDisable 0xF5 // reset to power up
+
+#define KbdSetDefault 0xf6 //
+#define KbdSetAllTlmtic 0xf7 // Set all keys telematic
+#define KbdSetAllMkBr 0xf8 // Set all keys Make /Break
+#define KbdSetAllMake 0xf9 // Set all keys Make only
+#define KbdSetKeyTlmtic 0xfb // Set individual key telemativ
+#define KbdSetKeyMkBr 0xfc // set individual key make/break
+#define KbdSetKeyMk 0xfd // set individual key make only
+#define KbdResend 0xfe // request to resend last transfer
+#define KbdReset 0xff // request to start a program reset
+#define KbdAck 0xfa // keyboard ack after reset
+#define KbdBat 0xAA // Keyboard Bat completion Response
+
+//
+// Define scan codes.
+//
+
+#define KEY_LEFT_SHIFT 0x2A
+#define KEY_RIGHT_SHIFT 0X36
+#define KEY_CAPS_LOCK 0X3A
+#define KEY_CONTROL 0X1D
+#define KEY_ALT 0X38
+#define KEY_UP_ARROW 0X48
+#define KEY_DOWN_ARROW 0X50
+#define KEY_LEFT_ARROW 0X4B
+#define KEY_RIGHT_ARROW 0X4D
+#define KEY_HOME 0X47
+#define KEY_END 0X4F
+#define KEY_INSERT 0X52
+#define KEY_DELETE 0X53
+#define KEY_SYS_REQUEST 0X54
+#define KEY_PRINT_SCREEN 0x37
+#define KEY_ESC 0x01
+#define KEY_PAGE_UP 0x49
+#define KEY_PAGE_DOWN 0x51
+#define KEY_F1 0x3B
+#define KEY_F2 0x3C
+#define KEY_F3 0x3D
+#define KEY_F4 0x3E
+#define KEY_F5 0x3F
+#define KEY_F6 0x40
+#define KEY_F7 0x41
+#define KEY_F8 0x42
+#define KEY_F9 0x43
+#define KEY_F10 0x44
+#define KEY_F11 0x57
+#define KEY_F12 0x58
+
+
+//
+// Define Keyboard controller register offsets.
+// Status (read) and Command (write) are the same register.
+//
+
+#define KbdDataReg 0x0
+#define KbdStatusReg 0x1
+#define KbdCommandReg 0x1
+
+#endif //_KBDMOUSE_
diff --git a/private/ntos/fw/ppc/led.h b/private/ntos/fw/ppc/led.h
new file mode 100644
index 000000000..94c7368d8
--- /dev/null
+++ b/private/ntos/fw/ppc/led.h
@@ -0,0 +1,125 @@
+/*++
+
+Copyright (c) 1990 Microsoft Corporation
+
+Module Name:
+
+ led.h
+
+Abstract:
+
+ This module defines test and subtest values to display in the
+ LED.
+
+Author:
+
+ Lluis Abello (lluis) 10-Jan-1991
+
+Revision History:
+
+--*/
+//
+// Diagnostic bits definitions.
+//
+#define DIAGNOSTIC_MASK ((1<<6) | (1<<7))
+#define CONFIGURATION_MASK (1<<7)
+#define LOOP_ON_ERROR_MASK (1<<6)
+#define LOOP_ON_ERROR 6
+#define CONFIGURATION 7
+#ifdef DUO
+#define IGNORE_ERRORS_MASK (1<<5)
+#endif
+//
+// LED symbols
+//
+#define LED_BLANK 0xD
+#define LED_MINUS_SIGN 0xB
+#define LED_DECIMAL_POINT 0x10
+
+//
+// LED Display routine control values
+//
+
+#define LED_NORMAL 0x0
+#define LED_BLINK 0x1
+#define LED_LOOP_ERROR 0x2
+#define LED_DELAY_LOOP 0xFFFF // time a digit shown in LED is:
+ // LED_DELAY_LOOP * time 2 ROM fetches
+//
+// LED display values
+//
+#define TEST_SHIFT 4
+
+#define LED_PROCESSOR_TEST 0xE0
+#define LED_TLB_TEST 0xE1
+#define LED_CACHE_INIT 0x60
+#define LED_ICACHE 0XE2
+#define LED_DCACHE 0XE3
+#define LED_SELFCOPY 0xE0
+
+#define LED_INTERRUPT 0x03
+#define LED_NOT_INTERRUPT 0x04 // for any not expected interrupt
+
+#define LED_MCTADR_RESET 0x00
+#define LED_MCTADR_REG 0x01
+#define LED_IO_CACHE 0x02
+
+#define LED_ROM_CHECKSUM 0xC0
+
+#define LED_MEMORY_TEST_1 0xAA
+#define LED_WRITE_MEMORY_2 0xA0
+#define LED_READ_MEMORY_2 0xA0
+#define LED_MAIN_MEMORY 0xA0 //becomes A1,A2,A3
+#define LED_READ_MERGE_WRITE 0xA4
+#define LED_WRONG_MEMORY 0xAE //bad SIMMs installed
+
+
+#define LED_VIDEOMEM 0x90
+#define LED_VIDEOMEM_CHECK_1 0x90
+#define LED_VIDEO_CONTROLLER 0x91
+#define LED_VIDEOMEM_CHECK_2 0x92
+
+
+#define LED_SERIAL_RESET 0x60
+#define LED_SERIAL1_REG 0x61
+#define LED_SERIAL2_REG 0x62
+#define LED_SERIAL1_LBACK 0x63
+#define LED_SERIAL2_LBACK 0x64
+#define LED_SERIAL_INIT 0x65
+#define LED_PARALLEL_REG 0x66
+
+#define LED_KEYBOARD_CTRL 0x50
+#define LED_KEYBOARD_INIT 0x51
+
+#define LED_BEEP 0x40
+#define LED_RTC 0x41
+#define LED_ISP 0x42
+
+#define LED_FLOPPY_RESET 0x30
+#define LED_FLOPPY_REG 0x31
+
+#define LED_SCSI_RESET 0x20
+#define LED_SCSI_REG 0X21
+
+#define LED_SONIC_RESET 0x10
+#define LED_SONIC_REG 0x11
+#define LED_SONIC_LOOPBACK 0x12
+
+#define LED_SOUND 0xC1
+
+#define LED_NVRAM 0x70
+
+#define LED_INIT_COMMAND 0xA5
+
+#define LED_ZEROMEM 0x00
+//
+// Exceptions
+//
+#define LED_PARITY 0xB0
+#define LED_NMI 0xB1
+
+//
+// Processor B selftest.
+//
+#define LED_B_MEMORY_TEST_1 0x20
+#define LED_B_MEMORY_TEST_2 0x21
diff --git a/private/ntos/fw/ppc/monitor.h b/private/ntos/fw/ppc/monitor.h
new file mode 100644
index 000000000..8ed220345
--- /dev/null
+++ b/private/ntos/fw/ppc/monitor.h
@@ -0,0 +1,159 @@
+/*++
+
+Copyright (c) 1991 Microsoft Corporation
+
+Module Name:
+
+ monitor.h
+
+Abstract:
+
+ This module contains definitions for monitor.c
+
+Author:
+
+ Lluis Abello (lluis) 09-Sep-1991
+
+Revision History:
+
+--*/
+
+#ifndef _MONITOR_
+#define _MONITOR_
+
+//
+// Define register names.
+//
+typedef enum _REGISTER_NAME_ID {
+ zero, // general register 0
+ at, // general register 1
+ v0, // general register 2
+ v1, // general register 3
+ a0, // general register 4
+ a1, // general register 5
+ a2, // general register 6
+ a3, // general register 7
+ t0, // general register 8
+ t1, // general register 9
+ t2, // general register 10
+ t3, // general register 11
+ t4, // general register 12
+ t5, // general register 13
+ t6, // general register 14
+ t7, // general register 15
+ s0, // general register 16
+ s1, // general register 17
+ s2, // general register 18
+ s3, // general register 19
+ s4, // general register 20
+ s5, // general register 21
+ s6, // general register 22
+ s7, // general register 23
+ t8, // general register 24
+ t9, // general register 25
+ k0, // general register 26
+ k1, // general register 27
+ gp, // general register 28
+ sp, // general register 29
+ s8, // general register 30
+ ra, // general register 31
+ f0, // fp register 0
+ f1, // fp register 1
+ f2, // fp register 2
+ f3, // fp register 3
+ f4, // fp register 4
+ f5, // fp register 5
+ f6, // fp register 6
+ f7, // fp register 7
+ f8, // fp register 8
+ f9, // fp register 9
+ f10, // fp register 10
+ f11, // fp register 11
+ f12, // fp register 12
+ f13, // fp register 13
+ f14, // fp register 14
+ f15, // fp register 15
+ f16, // fp register 16
+ f17, // fp register 17
+ f18, // fp register 18
+ f19, // fp register 19
+ f20, // fp register 20
+ f21, // fp register 21
+ f22, // fp register 22
+ f23, // fp register 23
+ f24, // fp register 24
+ f25, // fp register 25
+ f26, // fp register 26
+ f27, // fp register 27
+ f28, // fp register 28
+ f29, // fp register 29
+ f30, // fp register 30
+ f31, // fp register 31
+ fsr, // fp status register
+ index, // cop0 register 0
+ random, // cop0 register 1
+ entrylo0, // cop0 register 2
+ entrylo1, // cop0 register 3
+ context, // cop0 register 4
+ pagemask, // cop0 register 5
+ wired, // cop0 register 6
+ badvaddr, // cop0 register 8
+ count, // cop0 register 9
+ entryhi, // cop0 register 10
+ compare, // cop0 register 11
+ psr, // cop0 register 12
+ cause, // cop0 register 13
+ epc, // cop0 register 14
+ prid, // cop0 register 15
+ config, // cop0 register 16
+ lladdr, // cop0 register 17
+ watchlo, // cop0 register 18
+ watchhi, // cop0 register 19
+ ecc, // cop0 register 26
+ cacheerror, // cop0 register 27
+ taglo, // cop0 register 28
+ taghi, // cop0 register 29
+ errorepc, // cop0 register 30
+ invalidregister
+} REGISTER_NAME_ID;
+
+extern PCHAR RegisterNameTable[(REGISTER_NAME_ID)invalidregister];
+
+extern ULONG RegisterTable[(REGISTER_NAME_ID)invalidregister];
+
+//
+// Define Command names.
+//
+typedef enum _COMMAND_NAME_ID {
+ Dump,
+ DumpByte,
+ DumpWord,
+ DumpDouble,
+ Enter,
+ EnterByte,
+ EnterWord,
+ EnterDouble,
+ Output,
+ OutputByte,
+ OutputWord,
+ OutputDouble,
+ Input,
+ InputByte,
+ InputWord,
+ InputDouble,
+ Register,
+ Zero,
+ Fill,
+ AvailableDevices,
+ Help,
+ Help2,
+#ifdef DUO
+ SwitchProcessor,
+#endif
+ Quit,
+ invalidcommand
+} COMMAND_NAME_ID;
+
+extern PCHAR CommandNameTable[(COMMAND_NAME_ID)invalidcommand];
+
+#endif // _MONITOR_
diff --git a/private/ntos/fw/ppc/oli2msft.h b/private/ntos/fw/ppc/oli2msft.h
new file mode 100644
index 000000000..2733d4503
--- /dev/null
+++ b/private/ntos/fw/ppc/oli2msft.h
@@ -0,0 +1,39 @@
+
+// ----------------------------------------------------------------------------
+// File: oli2msft.h
+//
+// Description: General type definitions used in C files by Olivetti and
+// not Microsoft
+//
+// ----------------------------------------------------------------------------
+
+typedef ULONG BOOLEAN_ULONG;
+typedef BOOLEAN_ULONG *PBOOLEAN_ULONG;
+
+//
+// Configuration related defines
+//
+
+#define MAX_MNEMONIC_LEN 20 // max name length (with '\0')
+#define MAX_DEVICE_PATH_LEN 63 // ending '\0' excluded
+#define MAX_FILE_PATH_LEN 127 // ending '\0' excluded
+#define MAX_PATH_LEN (MAX_DEVICE_PATH_LEN + MAX_FILE_PATH_LEN)
+#define KEY_MAX_DIGITS 4 // max digits within a "key
+ // string" (\'0' not included).
+//
+// Configuration Data Header
+//
+
+typedef struct _CONFIGDATAHEADER
+ {
+ USHORT Version;
+ USHORT Revision;
+ PCHAR Type;
+ PCHAR Vendor;
+ PCHAR ProductName;
+ PCHAR SerialNumber;
+ } CONFIGDATAHEADER, *PCONFIGDATAHEADER;
+
+#define CONFIGDATAHEADER_SIZE sizeof(CONFIGDATAHEADER)
+
+#define MAXIMUM_SECTOR_SIZE 2048 // # bytes per sector
diff --git a/private/ntos/fw/ppc/selfmap.h b/private/ntos/fw/ppc/selfmap.h
new file mode 100644
index 000000000..8ea7d49a3
--- /dev/null
+++ b/private/ntos/fw/ppc/selfmap.h
@@ -0,0 +1,335 @@
+/*++
+
+Copyright (c) 1990 Microsoft Corporation
+
+Module Name:
+
+ selfmap.h
+
+Abstract:
+
+ This module defines various memory addresses for the ROM self-test.
+
+Author:
+
+ Lluis Abello (lluis) 10-Jan-1991
+
+Revision History:
+
+--*/
+
+#ifndef _SELFMAP_
+#define _SELFMAP_
+
+
+#define PROM256
+
+#ifdef PROM64
+#define ROM_SIZE 0x10000
+#endif
+#ifdef PROM128
+#define ROM_SIZE 0x20000
+#endif
+#ifdef PROM256
+#define ROM_SIZE 0x40000
+#endif
+
+//
+// TTable points to 2Mb
+//
+#define TT_BASE_ADDRESS 0x200000
+
+#define MEMTEST_SIZE 0x2000 // Size of memory tested first
+#define STACK_SIZE 0xA000 // 40Kb of stack
+#define RAM_TEST_STACK_ADDRESS 0x8000BFF0 // Stack for code copied to memory
+#define RAM_TEST_STACK_ADDRESS_B 0x80005FF0 // stack for processor B
+
+#ifdef R3000
+#define INSTRUCTION_CACHE_SIZE 0x10000 // 64Kb of I Cache
+#define DATA_CACHE_SIZE 0x10000 // 64Kb of D Cache
+#define SIZE_OF_CACHES 0x10000 // 64Kb bigest cache.
+#define ROM_TLB_ENTRIES (ROM_SIZE >> 12)
+#define DEVICE_TLB_ENTRIES 16
+#define FIRST_UNUSED_TLB_ENTRY ROM_TLB_ENTRIES+DEVICE_TLB_ENTRIES
+#endif // R3000
+
+//
+// Define firmware size.
+// Firmware size includes code and stack.
+//
+// FW_TOP_ADDRESS must be a 64K aligned address.
+// The upper 64Kb (0x50000 to 0x60000) are reserved for the video prom code.
+// Note that the firmware size is 0x40000, it is loaded starting
+// at address 0xC000, and the fonts are unpacked at 0x4C000.
+//
+// N.B. If any of these numbers change, adjust the are of memory zero'd by
+// j4start.s.
+//
+
+#define FW_BOTTOM_ADDRESS 0xC000
+#define FW_SIZE 0x40000
+#define FW_FONT_SIZE (0x50000 - FW_SIZE - FW_BOTTOM_ADDRESS)
+#define VIDEO_PROM_SIZE 0x10000
+#define FW_TOP_ADDRESS (FW_BOTTOM_ADDRESS + FW_SIZE + FW_FONT_SIZE + VIDEO_PROM_SIZE)
+
+#define FW_PAGES ((FW_TOP_ADDRESS) >> PAGE_SHIFT)
+
+#define VIDEO_PROM_CODE_VIRTUAL_BASE 0x10000000 // Link address of video prom code
+#define VIDEO_PROM_CODE_PHYSICAL_BASE (FW_TOP_ADDRESS - VIDEO_PROM_SIZE) // phys address of video prom code
+#define VIDEO_PROM_CODE_UNCACHED_BASE (KSEG1_BASE + VIDEO_PROM_CODE_PHYSICAL_BASE) // uncached address where video prom code is copied
+
+#define FW_FONT_ADDRESS (KSEG0_BASE + FW_BOTTOM_ADDRESS + FW_SIZE)
+
+//
+// Address definitions for the SelftTests written in C.
+// The code is copied to RAM_TEST_LINK_ADDRESS from RAM_TEST_ROM_ADDRESS
+// so that it runs at the address it was linked.
+//
+
+#define RAM_TEST_DESTINATION_ADDRESS 0xA000c000 // uncached link address
+#define RAM_TEST_LINK_ADDRESS 0x8000c000 // Link Address of code
+
+//
+// FW_TOP_ADDRESS ___________
+// | Video rom |
+// | code |
+// |___________|
+// FW_SIZE | Code |
+// | & |
+// | Data |
+// | |
+// |___________|
+// | Stack || |
+// |_______\/__|
+// MEMTEST_SIZE |PutLed | Memory tested from ROM
+// |ZeroMem |
+// |MemoryTest |
+// 0 |___________|
+//
+
+#ifdef DUO
+#define LINK_ADDRESS 0xE1040000
+#else
+#define LINK_ADDRESS 0xE1000000
+#endif
+#define RESET_VECTOR 0xBFC00000
+
+//
+// Virtual - Physiscal base address pairs
+//
+#define TLB_TEST_PHYS 0x0 // To test the tlb
+#define TLB_TEST_VIRT 0x20000000 //
+#define RESV_VIRT 0xE4000000
+
+//
+// Entry LO - HI pairs
+//
+#ifdef R4000
+#define PROM_HI ((PROM_VIRTUAL_BASE >> 13) << ENTRYHI_VPN2)
+#define PROM_LO0 ((PROM_PHYSICAL_BASE >> 12) << ENTRYLO_PFN) + (1 << ENTRYLO_G) + (1 << ENTRYLO_V) + (2 << ENTRYLO_C)
+#ifdef PROM256
+#define PROM_LO1 (1 << ENTRYLO_G)
+#define PROM_MASK (PAGEMASK_256KB << PAGEMASK_PAGEMASK)
+#endif
+#ifdef PROM128 //
+#define PROM_LO1 (((PROM_PHYSICAL_BASE+0x10000) >> 12) << ENTRYLO_PFN) + (1 << ENTRYLO_G) + \
+ (1 << ENTRYLO_V) + (2 << ENTRYLO_C)
+#define PROM_MASK (PAGEMASK_64KB << PAGEMASK_PAGEMASK)
+#endif
+#ifdef PROM64
+#define PROM_LO1 (1 << ENTRYLO_G) // If odd page not used
+#define PROM_MASK (PAGEMASK_64KB << PAGEMASK_PAGEMASK)
+#endif
+#define TLB_TEST_LO ((1 << ENTRYLO_G) + (1 << ENTRYLO_V) + \
+ (1 << ENTRYLO_D) + (2 << ENTRYLO_C) + TLB_TEST_PHYS)
+
+#define TLB_TEST_HI TLB_TEST_VIRT
+
+#define TLB_KSEG_PHYS 0x0
+#define TLB_KSEG_LO ((1 << ENTRYLO_G) + (1 << ENTRYLO_V) + \
+ (1 << ENTRYLO_D) + (3 << ENTRYLO_C) + TLB_KSEG_PHYS)
+#define TLB_KSEG_VIRT 0x10000000
+#define TLB_KSEG_HI TLB_KSEG_VIRT
+#define TLB_KSEG_MASK (PAGEMASK_64KB << PAGEMASK_PAGEMASK)
+#endif // R4000
+
+#ifdef R3000
+//
+// Entry LO - HI pairs
+//
+#define DIAGNOSTIC_PHYSICAL_BASE 0x8000F000
+
+#define LED_LO ((1 << ENTRYLO_G) | (1 << ENTRYLO_V) | \
+ (1 << ENTRYLO_N) | (1 << ENTRYLO_D) | \
+ DIAGNOSTIC_PHYSICAL_BASE)
+#define LED_HI DIAGNOSTIC_VIRTUAL_BASE
+
+#define TLB_TEST_LO ((1 << ENTRYLO_G) | (1 << ENTRYLO_V) | \
+ (1 << ENTRYLO_N) | (1 << ENTRYLO_D) | \
+ TLB_TEST_PHYS)
+#define TLB_TEST_HI TLB_TEST_VIRT
+
+#define ROM_LO ((1 << ENTRYLO_G) | (1 << ENTRYLO_V) | \
+ (1 << ENTRYLO_N) | \
+ PROM_PHYSICAL_BASE)
+#define ROM_HI PROM_VIRTUAL_BASE
+
+#define DEVICE_LO ((1 << ENTRYLO_G) | (1 << ENTRYLO_V) | \
+ (1 << ENTRYLO_N) | (1 << ENTRYLO_D) | \
+ DEVICE_PHYSICAL_BASE)
+#define DEVICE_HI DEVICE_VIRTUAL_BASE
+
+#define PROC_LO ((1 << ENTRYLO_G) | (1 << ENTRYLO_V) | \
+ (1 << ENTRYLO_N) | \
+ INTERRUPT_PHYSICAL_BASE)
+#define PROC_HI INTERRUPT_VIRTUAL_BASE
+
+#define VID_LO ((1 << ENTRYLO_G) | (1 << ENTRYLO_V) | \
+ (1 << ENTRYLO_N) | (1 << ENTRYLO_D) | \
+ VIDEO_CONTROL_PHYSICAL_BASE)
+#define VID_HI VIDEO_CONTROL_VIRTUAL_BASE
+
+#define VIDMEM_LO ((1 << ENTRYLO_G) | (1 << ENTRYLO_V) | \
+ (1 << ENTRYLO_N) | (1 << ENTRYLO_D) | \
+ VIDEO_MEMORY_PHYSICAL_BASE)
+#define VIDMEM_HI VIDEO_MEMORY_PHYSICAL_BASE
+
+
+#define CURSOR_LO ((1 << ENTRYLO_G) | (1 << ENTRYLO_V) | \
+ (1 << ENTRYLO_N) | (1 << ENTRYLO_D) | \
+ VIDEO_CURSOR_PHYSICAL_BASE)
+#define CURSOR_HI VIDEO_CURSOR_VIRTUAL_BASE
+
+#define RESV_LO ((1 << ENTRYLO_G) | (1 << ENTRYLO_N))
+#define RESV_HI RESV_VIRT
+
+#endif //R3000
+//
+// Trap handling definitions.
+//
+#define COMMON_EXCEPTION 0
+#define NMI_EXCEPTION 1
+#define CACHE_EXCEPTION 2
+
+
+//
+// Define offsets from Register Table.
+// Must match the definiton in monitor.h
+//
+#define zeroRegTable 0x0
+#define atRegTable 0x4
+#define v0RegTable 0x8
+#define v1RegTable 0xC
+#define a0RegTable 0x10
+#define a1RegTable 0x14
+#define a2RegTable 0x18
+#define a3RegTable 0x1C
+#define t0RegTable 0x20
+#define t1RegTable 0x24
+#define t2RegTable 0x28
+#define t3RegTable 0x2C
+#define t4RegTable 0x30
+#define t5RegTable 0x34
+#define t6RegTable 0x38
+#define t7RegTable 0x3C
+#define s0RegTable 0x40
+#define s1RegTable 0x44
+#define s2RegTable 0x48
+#define s3RegTable 0x4C
+#define s4RegTable 0x50
+#define s5RegTable 0x54
+#define s6RegTable 0x58
+#define s7RegTable 0x5C
+#define t8RegTable 0x60
+#define t9RegTable 0x64
+#define k0RegTable 0x68
+#define k1RegTable 0x6C
+#define gpRegTable 0x70
+#define spRegTable 0x74
+#define s8RegTable 0x78
+#define raRegTable 0x7C
+#define f0RegTable 0x80
+#define f1RegTable 0x84
+#define f2RegTable 0x88
+#define f3RegTable 0x8C
+#define f4RegTable 0x90
+#define f5RegTable 0x94
+#define f6RegTable 0x98
+#define f7RegTable 0x9C
+#define f8RegTable 0xA0
+#define f9RegTable 0xA4
+#define f10RegTable 0xA8
+#define f11RegTable 0xAC
+#define f12RegTable 0xB0
+#define f13RegTable 0xB4
+#define f14RegTable 0xB8
+#define f15RegTable 0xBC
+#define f16RegTable 0xC0
+#define f17RegTable 0xC4
+#define f18RegTable 0xC8
+#define f19RegTable 0xCC
+#define f20RegTable 0xD0
+#define f21RegTable 0xD4
+#define f22RegTable 0xD8
+#define f23RegTable 0xDC
+#define f24RegTable 0xE0
+#define f25RegTable 0xE4
+#define f26RegTable 0xE8
+#define f27RegTable 0xEC
+#define f28RegTable 0xF0
+#define f29RegTable 0xF4
+#define f30RegTable 0xF8
+#define f31RegTable 0xFC
+#define fsrRegTable 0x100
+#define indexRegTable 0x104
+#define randomRegTable 0x108
+#define entrylo0RegTable 0x10C
+#define entrylo1RegTable 0x110
+#define contextRegTable 0x114
+#define pagemaskRegTable 0x118
+#define wiredRegTable 0x11C
+#define badvaddrRegTable 0x120
+#define countRegTable 0x124
+#define entryhiRegTable 0x128
+#define compareRegTable 0x12C
+#define psrRegTable 0x130
+#define causeRegTable 0x134
+#define epcRegTable 0x138
+#define pridRegTable 0x13C
+#define configRegTable 0x140
+#define lladdrRegTable 0x144
+#define watchloRegTable 0x148
+#define watchhiRegTable 0x14C
+#define eccRegTable 0x150
+#define cacheerrorRegTable 0x154
+#define tagloRegTable 0x158
+#define taghiRegTable 0x15C
+#define errorepcRegTable 0x160
+#define RegisterTableSize 0x164
+
+//
+// Define Fw exception frame offsets.
+//
+
+#define FwFrameK1 0x4
+#define FwFrameRa 0x8
+#define FwFrameA0 0xC
+#define FwFrameA1 0x10
+#define FwFrameA2 0x14
+#define FwFrameA3 0x18
+#define FwFrameV0 0x1C
+#define FwFrameV1 0x20
+#define FwFrameT0 0x24
+#define FwFrameT1 0x28
+#define FwFrameT2 0x2C
+#define FwFrameT3 0x30
+#define FwFrameT4 0x34
+#define FwFrameT5 0x38
+#define FwFrameT6 0x3C
+#define FwFrameT7 0x40
+#define FwFrameT8 0x44
+#define FwFrameT9 0x48
+#define FwFrameAT 0x4C
+#define FwFrameSize 0x50
+
+#endif // _SELFMAP_
diff --git a/private/ntos/fw/ppc/selftest.h b/private/ntos/fw/ppc/selftest.h
new file mode 100644
index 000000000..4afa2db0e
--- /dev/null
+++ b/private/ntos/fw/ppc/selftest.h
@@ -0,0 +1,224 @@
+/*++
+
+Copyright (c) 1990 Microsoft Corporation
+
+Module Name:
+
+ selftest.c
+
+Abstract:
+
+ This module contains definitions for selftest.c
+
+Author:
+
+ Lluis Abello (lluis) 03-Jan-1991
+
+Environment:
+
+
+Revision History:
+
+--*/
+//
+// Video Memory Test
+//
+
+#define VIDEO_MEMORY_SIZE 0x200000 // 2 MB
+#define DISPLAY_MEMORY_SIZE 0x100000 // 1 MB
+
+//
+// Memory test stuff
+//
+
+#define TESTED_KB (FW_TOP_ADDRESS>>10)
+#define KB_OF_MEMORY (MEMORY_SIZE>>10) //
+#define KB_PER_TEST 0x400 // 1024K at a time
+#define NVRAM_TEST_END 0x800
+
+typedef ULONG (* TestRoutine)(VOID);
+typedef VOID (* LED_ROUTINE)(ULONG);
+
+#ifndef DUO
+#define PROM_BASE (KSEG1_BASE | 0x1fc00000)
+#else
+#define PROM_BASE (EEPROM_VIRTUAL_BASE)
+#endif
+
+#define PROM_ENTRY(x) (PROM_BASE + ((x) * 8))
+
+#define PutLedDisplay ((LED_ROUTINE) PROM_ENTRY(14))
+//
+// Declare static variables
+//
+extern PUCHAR TranslationTable;
+extern UCHAR StationAddress[6];
+
+extern BOOLEAN LanAddress; // True if station address is OK False Otherwise
+extern BOOLEAN ConfigurationBit; // read value from diagnostic register
+extern BOOLEAN LoopOnError; // read value from diagnostic register
+extern BOOLEAN IgnoreErrors; // read value from diagnostic register
+extern BOOLEAN VideoReady; // True if display on video monitor
+
+extern volatile LONG TimerTicks; // Counter for timeouts
+
+//
+// Routine declaration.
+//
+BOOLEAN ExecuteTest(TestRoutine,ULONG);
+VOID RomPutLine(CHAR *);
+ULONG RomVideoMemory();
+ULONG RomReadMergeWrite();
+ULONG RomIOCacheTest();
+ULONG RomSonicResetTest();
+ULONG RomSonicLoopBackTest();
+ULONG RomFloppyResetTest();
+ULONG RomScsiResetTest();
+ULONG RomSerialResetTest();
+ULONG RomSerial1RegistersTest();
+ULONG RomSerial2RegistersTest();
+ULONG RomSerial1LoopBackTest();
+ULONG RomSerial2LoopBackTest();
+ULONG RomParallelRegistersTest();
+ULONG RomScsiRegistersTest();
+ULONG RomFloppyRegistersTest();
+ULONG RomSonicRegistersTest();
+ULONG InterruptControllerTest();
+ULONG ConnectInterrupts();
+ULONG DisableInterrupts();
+ULONG RomRTCTest();
+ULONG InitMouse();
+ULONG InitKeyboard();
+ULONG InitKeyboardController();
+ULONG RomNvramTest();
+VOID RomBeep();
+ULONG RomInitISP (VOID);
+
+#define CHECK_ULONG(Address,Value) if (READ_REGISTER_ULONG(Address) != Value) {\
+ Errors++;\
+ }
+#define CHECK_USHORT(Address,Value) if ((Tmp=READ_REGISTER_USHORT(Address)) != Value) { \
+ FwPrint("Expected %lx received %lx\r\n",Value,Tmp);\
+ Errors++;\
+ }
+#define CHECK_UCHAR(Address,Value) if (READ_REGISTER_UCHAR(Address) != Value) { \
+ Errors++;\
+ }
+
+
+#ifdef DUO
+
+typedef
+ULONG
+(*PPROCESSOR_TASK_ROUTINE) (
+ IN PVOID Data
+ );
+
+BOOLEAN
+WaitForIpInterrupt();
+
+VOID
+WaitForAsIpInterrupt();
+
+BOOLEAN
+WaitForBsIpInterrupt(
+ IN ULONG Timeout
+ );
+
+VOID
+ProcessorBMain(
+ );
+
+BOOLEAN
+ProcessorBSelftest(
+ IN VOID
+ );
+
+VOID
+WriteMemoryAddressTest(
+ ULONG StartAddress,
+ ULONG Size,
+ ULONG Xorpattern
+ );
+
+PULONG
+CheckMemoryAddressTest(
+ ULONG StartAddress,
+ ULONG Size,
+ ULONG Xorpattern,
+ ULONG LedDisplayValue
+ );
+
+VOID
+WriteVideoMemoryAddressTest(
+ ULONG StartAddress,
+ ULONG Size
+ );
+
+ULONG
+CheckVideoMemoryAddressTest(
+ ULONG StartAddress,
+ ULONG Size
+ );
+
+typedef struct _PROCESSOR_B_TASK_VECTOR {
+ PPROCESSOR_TASK_ROUTINE Routine;
+ PVOID Data;
+ ULONG ReturnValue;
+ } PROCESSOR_B_TASK_VECTOR, *PPROCESSOR_B_TASK_VECTOR;
+
+
+extern volatile PROCESSOR_B_TASK_VECTOR ProcessorBTask;
+
+typedef struct _PROCESSOR_B_TEST {
+ PPROCESSOR_TASK_ROUTINE Routine;
+ PVOID Data;
+ } PROCESSOR_B_TEST, *PPROCESSOR_B_TEST;
+
+//
+// Define data structures for each of processor B's tests.
+//
+
+typedef struct _MEMORY_TEST_DATA {
+ ULONG StartAddress;
+ ULONG Size;
+ ULONG XorPattern;
+ ULONG LedDisplayValue;
+ } MEMORY_TEST_DATA, *PMEMORY_TEST_DATA;
+
+ULONG
+ProcessorBMemoryTest(
+ IN PMEMORY_TEST_DATA MemoryData
+ );
+
+ULONG
+ProcessorBVideoMemoryTest(
+ IN PMEMORY_TEST_DATA MemoryData
+ );
+
+VOID
+ProcessorBSystemBoot(
+ IN VOID
+ );
+
+ULONG
+RomScsiResetTest(
+ IN VOID
+ );
+
+ULONG
+CoherencyTest(
+ IN PVOID CoherentPage
+ );
+
+BOOLEAN
+IsIpInterruptSet(
+ IN VOID
+ );
+
+VOID
+RestartProcessor(
+ IN PRESTART_BLOCK RestartBlock
+ );
+
+#endif
diff --git a/private/ntos/fw/ppc/sonictst.h b/private/ntos/fw/ppc/sonictst.h
new file mode 100644
index 000000000..9ea0d367c
--- /dev/null
+++ b/private/ntos/fw/ppc/sonictst.h
@@ -0,0 +1,246 @@
+/*++
+
+Copyright (c) 1990 Microsoft Corporation
+
+Module Name:
+
+ sonictst.h
+
+Abstract:
+
+ This module contains the define constants for the SONIC ethernet controller
+ selftest in the jazz system.
+
+Author:
+
+ Lluis Abello (lluis) 19-Feb-1991
+
+Environment:
+
+
+Revision History:
+
+--*/
+
+#define LAN_MEMORY_ERROR 1
+#define LAN_ADDRESS_ERROR 2
+
+//
+// Transmit Control Register bit definitions
+//
+#define TCR_PTX (1 << 0)
+#define TCR_BCM (1 << 1)
+#define TCR_FU (1 << 2)
+#define TCR_PMB (1 << 3)
+#define TCR_OWC (1 << 5)
+#define TCR_EXC (1 << 6)
+#define TCR_CRSL (1 << 7)
+#define TCR_NCRS (1 << 8)
+#define TCR_DEF (1 << 9)
+#define TCR_EXD (1 << 10)
+#define TCR_EXDIS (1 << 12)
+#define TCR_CRCI (1 << 13)
+#define TCR_POWC (1 << 14)
+#define TCR_PINT (1 << 15)
+//
+// Receive Control Register
+//
+#define RCR_PRX (1 << 0) // Packet recived OK
+#define RCR_LBK (1 << 1) // Loopback packet received.
+#define RCR_FAER (1 << 2) // Frame alignament error.
+#define RCR_CRCR (1 << 3) // CRC Error
+#define RCR_COL (1 << 4) // Collision activity
+#define RCR_CRS (1 << 5) // Carrier sense activity
+#define RCR_LPKT (1 << 6) // Last packet in RBA
+#define RCR_BC (1 << 7) // Broadcast packet received
+#define RCR_MC (1 << 8) // Multicast packet received
+#define RCR_MAC (1 << 9) // MAC Loopback
+#define RCR_ENDEC (1 <<10) // ENDEC loopback
+#define RCR_TRANS (3 << 9) // Transceiver loopback
+#define RCR_AMC (1 <<11) // Accept all musticast packets
+#define RCR_PRO (1 <<12) // Physical promiscuious packets
+#define RCR_BRD (1 <<13) // Accept Broadcast packets
+#define RCR_RNT (1 <<14) // Accept Runt packets
+#define RCR_ERR (1 <<15) // Accept Packets with errors
+
+//
+// Data configuration register value.
+//
+#define DATA_CONFIGURATION 0x2439 // 0x2439
+
+//
+// Interrupt Mask Register and Interrupt Status Register bit definitions
+//
+#define INT_RFO (1 << 0) // receive fifo overrun
+#define INT_MP (1 << 1) // Missed Packed counter rollover
+#define INT_FAE (1 << 2) // Frame alignment error
+#define INT_CRC (1 << 3) // CRC tally counter rollover
+#define INT_RBAE (1 << 4) // Receive Buffer Area exceded
+#define INT_RBE (1 << 5) // Recive Buffers exhausted
+#define INT_RDE (1 << 6) // Recive descriptors exhausted
+#define INT_TC (1 << 7) // Timer complete
+#define INT_TXER (1 << 8) // Transmit error
+#define INT_TXDN (1 << 9) // Transmission done
+#define INT_PKTRX (1 << 10) // Packet received
+#define INT_PINT (1 << 11) // Programable interrupt
+#define INT_LCD (1 << 12) // Load CAM done.
+#define INT_HBL (1 << 13) // CD heartbeat lost
+#define INT_BR (1 << 14) // Bus retry
+//
+// Command register bit definitions.
+//
+#define CR_HTX (1 << 0) // Halt Transmission
+#define CR_TXP (1 << 1) // Transmit packets
+#define CR_RXDIS (1 << 2) // Receiver disable
+#define CR_RXEN (1 << 3) // receiver enable
+#define CR_STP (1 << 4) // stop timer
+#define CR_ST (1 << 5) // start timer
+#define CR_RST (1 << 7) // software reset
+#define CR_RRA (1 << 8) // read RRA
+#define CR_LCAM (1 << 9) // load CAM
+
+//
+// Resurce & Data tables structure definition.
+//
+typedef struct _SONIC_ENTRY {
+ USHORT Data; // all tables in memory
+ USHORT Fill; // trash the upper 16 bits
+ } SONIC_ENTRY;
+
+
+//
+// Receive Resource Area Format definition
+//
+
+typedef struct _RECEIVE_RESOURCE {
+ SONIC_ENTRY BufferPtr0;
+ SONIC_ENTRY BufferPtr1;
+ SONIC_ENTRY WordCount0;
+ SONIC_ENTRY WordCount1;
+ } RECEIVE_RESOURCE, * PRECEIVE_RESOURCE;
+
+//
+// Declare a variable that will point to the resource descriptor area.
+//
+PRECEIVE_RESOURCE ReceivePhysRsrc;
+PRECEIVE_RESOURCE ReceiveLogRsrc;
+//
+// Offset between physical and logical Receive Buffers to allow an easy
+// translation from logical to physical pointers to received packets.
+//
+ULONG ReceiveBufferTranslationOffset;
+
+#define RBA_SIZE 0x1000
+
+//
+// CAM_DESCRIPTOR format definition
+//
+typedef struct _CAM_DESCRIPTOR {
+ SONIC_ENTRY EntryPointer;
+ SONIC_ENTRY Port0;
+ SONIC_ENTRY Port1;
+ SONIC_ENTRY Port2;
+ } CAM_DESCRIPTOR;
+
+typedef CAM_DESCRIPTOR * PCAM_DESCRIPTOR;
+
+PCAM_DESCRIPTOR PhysCamDescriptor,LogCamDescriptor;
+
+//
+// Receive Descriptor Format definition.
+//
+typedef struct _RECEIVE_DESCRIPTOR {
+ SONIC_ENTRY Status;
+ SONIC_ENTRY ByteCount;
+ SONIC_ENTRY PktPtr0;
+ SONIC_ENTRY PktPtr1;
+ SONIC_ENTRY SeqNo;
+ SONIC_ENTRY Link;
+ SONIC_ENTRY InUse;
+ } RECEIVE_DESCRIPTOR;
+
+typedef RECEIVE_DESCRIPTOR * PRECEIVE_DESCRIPTOR;
+//
+// Receive Descriptor Field value definitions
+//
+
+#define AVAILABLE 0xFABA // Descriptor Available to SONIC
+#define IN_USE 0 // Descriptor being used by SONIC
+
+#define EOL 1 // To be ORed with the Link field to make the
+ // descriptor become the last one of the list
+#define NOT_EOL 0xFFFE // To be ANDed with the Link field to make the
+ // descriptor not be the last one of the list
+
+typedef struct _RECEIVE_DESCRIPTOR_QUEUE {
+ PRECEIVE_DESCRIPTOR Base;
+ ULONG Current;
+ ULONG Last;
+ } RECEIVE_DESCRIPTOR_QUEUE;
+
+RECEIVE_DESCRIPTOR_QUEUE ReceiveDscrQueue;
+#define CURRENT_DESCRIPTOR ((PRECEIVE_DESCRIPTOR)((ULONG) ReceiveDscrQueue.Base | ReceiveDscrQueue.Current))
+#define LAST_DESCRIPTOR ((PRECEIVE_DESCRIPTOR)((ULONG) ReceiveDscrQueue.Base | ReceiveDscrQueue.Last))
+
+//
+// Transmit Descriptor definition
+//
+
+typedef struct _TRANSMIT_DESCRIPTOR {
+ SONIC_ENTRY Status;
+ SONIC_ENTRY Config;
+ SONIC_ENTRY PktSize;
+ SONIC_ENTRY FragCount; // Must be 1. We don't need to scater
+ SONIC_ENTRY FragPtr0; // the paket in memory and this let's us define
+ SONIC_ENTRY FragPtr1; // a fixed size structure with only one pointer
+ SONIC_ENTRY FragSize; // and one size field per paket.
+ SONIC_ENTRY Link;
+ } TRANSMIT_DESCRIPTOR;
+
+typedef TRANSMIT_DESCRIPTOR * PTRANSMIT_DESCRIPTOR;
+
+PTRANSMIT_DESCRIPTOR PhysTransmitDscr;
+PTRANSMIT_DESCRIPTOR LogicalTransmitDscr;
+
+typedef struct _SONIC_DATA {
+ USHORT InterruptID;
+ USHORT ExpectedInt;
+ USHORT TransmitControl;
+ USHORT Status;
+ } SONIC_DATA,* PSONIC_DATA;
+
+volatile SONIC_DATA SonicStatus;
+//
+// Define status.
+//
+#define ERROR 1
+#define DONE 0
+//
+// Macro definition
+//
+
+#define EXPECTED_INT (InterruptStatus & SonicStatus.ExpectedInt)
+#define NO_OTHER_INT ((InterruptStatus & (~SonicStatus.ExpectedInt))==0)
+
+#define MAX_PACKET_SIZE 1520
+#define MAX_DATA_LENGTH 1500
+#define MIN_DATA_LENGTH 46
+
+
+//
+// Resources Logical & Physical addresses.
+//
+#define PHYS_RECEIVE_DSCR_ADDRESS 0xA0100000 // the lower 16 bits of both
+#define LOGICAL_RECEIVE_DSCR_ADDRESS 0x00000000 // Log & Phys add must match.
+#define RECEIVE_PHYS_RSRC_ADDRESS 0xA0101000
+#define RECEIVE_LOG_RSRC_ADDRESS 0x00001000
+#define RECEIVE_PHYS_BUFFER_ADDRESS 0xA0102000
+#define RECEIVE_LOG_BUFFER_ADDRESS 0x00002000
+#define PHYS_TRANSMIT_DSCR_ADDRESS 0xA0104000
+#define LOGICAL_TRANSMIT_DSCR_ADDRESS 0x00004000
+#define PHYS_TBA_ADDRESS 0xA0105000
+#define LOG_TBA_ADDRESS 0x00005000
+
+volatile ULONG SonicIntSemaphore;
+extern UCHAR StationAddress[6];
+ULONG SonicErrors;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 21:36:42 +0100