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author | Adam <you@example.com> | 2020-05-17 05:51:50 +0200 |
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committer | Adam <you@example.com> | 2020-05-17 05:51:50 +0200 |
commit | e611b132f9b8abe35b362e5870b74bce94a1e58e (patch) | |
tree | a5781d2ec0e085eeca33cf350cf878f2efea6fe5 /private/windbg/em/p_mips/regs.h | |
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Diffstat (limited to '')
-rw-r--r-- | private/windbg/em/p_mips/regs.h | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/private/windbg/em/p_mips/regs.h b/private/windbg/em/p_mips/regs.h new file mode 100644 index 000000000..2b080b498 --- /dev/null +++ b/private/windbg/em/p_mips/regs.h @@ -0,0 +1,120 @@ + +#define SIZE 64 + + { szR0, rtCPU | rtInvisible| rtInteger, SIZE, CV_M4_IntZERO }, + { szR1, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntAT }, + { szR2, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntV0 }, + { szR3, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntV1 }, + { szR4, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntA0 }, + { szR5, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntA1 }, + { szR6, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntA2 }, + { szR7, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntA3 }, + { szR8, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT0 }, + { szR9, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT1 }, + { szR10, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT2 }, + { szR11, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT3 }, + { szR12, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT4 }, + { szR13, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT5 }, + { szR14, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT6 }, + { szR15, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT7 }, + { szR24, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT8 }, + { szR25, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntT9 }, + { szR16, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS0 }, + { szR17, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS1 }, + { szR18, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS2 }, + { szR19, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS3 }, + { szR20, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS4 }, + { szR21, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS5 }, + { szR22, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS6 }, + { szR23, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS7 }, + { szR30, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntS8 }, + { szR26, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntKT0 }, + { szR27, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntKT1 }, + { szR28, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntGP }, + { szR29, rtCPU | rtRegular | rtExtended | rtInteger | rtFrame, SIZE, CV_M4_IntSP }, + { szR31, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntRA }, + { szLo, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntLO }, + { szHi, rtCPU | rtRegular | rtExtended | rtInteger, SIZE, CV_M4_IntHI }, + { szFir, rtCPU | rtRegular | rtExtended | rtInteger | rtPC, 32, CV_M4_Fir }, + { szPsr, rtCPU | rtRegular | rtExtended | rtInteger, 32, CV_M4_Psr }, + + { szFr0, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF0 }, + { szFr1, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF1 }, + { szFr2, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF2 }, + { szFr3, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF3 }, + { szFr4, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF4 }, + { szFr5, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF5 }, + { szFr6, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF6 }, + { szFr7, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF7 }, + { szFr8, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF8 }, + { szFr9, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF9 }, + { szFr10, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF10 }, + { szFr11, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF11 }, + { szFr12, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF12 }, + { szFr13, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF13 }, + { szFr14, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF14 }, + { szFr15, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF15 }, + { szFr16, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF16 }, + { szFr17, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF17 }, + { szFr18, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF18 }, + { szFr19, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF19 }, + { szFr20, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF20 }, + { szFr21, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF21 }, + { szFr22, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF22 }, + { szFr23, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF23 }, + { szFr24, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF24 }, + { szFr25, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF25 }, + { szFr26, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF26 }, + { szFr27, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF27 }, + { szFr28, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF28 }, + { szFr29, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF29 }, + { szFr30, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF30 }, + { szFr31, rtFPU | rtRegular | rtFloat, 32, CV_M4_FltF31 }, + + + { szFp0, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF0 << 8) | CV_M4_FltF1 }, + { szFp2, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF2 << 8) | CV_M4_FltF3 }, + { szFp4, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF4 << 8) | CV_M4_FltF5 }, + { szFp6, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF6 << 8) | CV_M4_FltF7 }, + { szFp8, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF8 << 8) | CV_M4_FltF9 }, + { szFp10, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF10 << 8) | CV_M4_FltF11 }, + { szFp12, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF12 << 8) | CV_M4_FltF13 }, + { szFp14, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF14 << 8) | CV_M4_FltF15 }, + { szFp16, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF16 << 8) | CV_M4_FltF17 }, + { szFp18, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF18 << 8) | CV_M4_FltF19 }, + { szFp20, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF20 << 8) | CV_M4_FltF21 }, + { szFp22, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF22 << 8) | CV_M4_FltF23 }, + { szFp24, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF24 << 8) | CV_M4_FltF25 }, + { szFp26, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF26 << 8) | CV_M4_FltF27 }, + { szFp28, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF28 << 8) | CV_M4_FltF29 }, + { szFp30, rtFPU | rtExtended | rtFloat, 64, + (CV_M4_FltF30 << 8) | CV_M4_FltF31 }, +/* + + { szFq0, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF0 }, + { szFq4, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF4 }, + { szFq8, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF8 }, + { szFq12, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF12 }, + { szFq16, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF16 }, + { szFq20, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF20 }, + { szFq24, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF24 }, + { szFq28, rtFPU | rtExtended | rtFloat, 128, CV_M4_FltF28 } +*/ + + + { szFsr, rtFPU | rtRegular | rtExtended | rtInteger, 32, CV_M4_FltFsr } |