summaryrefslogtreecommitdiffstats
path: root/src/core/arm/dyncom
diff options
context:
space:
mode:
Diffstat (limited to 'src/core/arm/dyncom')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp28
-rw-r--r--src/core/arm/dyncom/arm_dyncom_trans.cpp2
2 files changed, 15 insertions, 15 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 3522d1e82..fc2d6aabc 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -230,7 +230,7 @@ static unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sh
}
#define DEBUG_MSG \
- LOG_DEBUG(Core_ARM11, "inst is %x", inst); \
+ LOG_DEBUG(Core_ARM, "inst is %x", inst); \
CITRA_IGNORE_EXIT(0)
#define LnSWoUB(s) glue(LnSWoUB, s)
@@ -769,7 +769,7 @@ static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_ins
inst_index = table_length - 4;
*ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
} else {
- LOG_ERROR(Core_ARM11, "thumb decoder error");
+ LOG_ERROR(Core_ARM, "thumb decoder error");
}
break;
case 28:
@@ -827,9 +827,9 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
int idx;
if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
- LOG_ERROR(Core_ARM11, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32,
+ LOG_ERROR(Core_ARM, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32,
phys_addr, inst);
- LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
+ LOG_ERROR(Core_ARM, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
cpu->TFlag, cpu->Reg[15]);
CITRA_IGNORE_EXIT(-1);
}
@@ -1802,7 +1802,7 @@ BIC_INST : {
BKPT_INST : {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
- LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
+ LOG_DEBUG(Core_ARM, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
}
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(bkpt_inst));
@@ -2017,7 +2017,7 @@ EOR_INST : {
}
LDC_INST : {
// Instruction not implemented
- // LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
+ // LOG_CRITICAL(Core_ARM, "unimplemented instruction");
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(ldc_inst));
FETCH_INST;
@@ -2368,7 +2368,7 @@ MCRR_INST : {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
- LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
+ LOG_ERROR(Core_ARM, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
inst_cream->rt2);
}
@@ -2451,7 +2451,7 @@ MRRC_INST : {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
- LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
+ LOG_ERROR(Core_ARM, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
inst_cream->rt2);
}
@@ -3078,7 +3078,7 @@ SETEND_INST : {
else
cpu->Cpsr &= ~(1 << 9);
- LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE");
+ LOG_WARNING(Core_ARM, "SETEND %s executed", big_endian ? "BE" : "LE");
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(setend_inst));
@@ -3089,7 +3089,7 @@ SETEND_INST : {
SEV_INST : {
// Stubbed, as SEV is a hint instruction.
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
- LOG_TRACE(Core_ARM11, "SEV executed.");
+ LOG_TRACE(Core_ARM, "SEV executed.");
}
cpu->Reg[15] += cpu->GetInstructionSize();
@@ -3539,7 +3539,7 @@ SSAT16_INST : {
STC_INST : {
// Instruction not implemented
- // LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
+ // LOG_CRITICAL(Core_ARM, "unimplemented instruction");
cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(stc_inst));
FETCH_INST;
@@ -4529,7 +4529,7 @@ UXTB16_INST : {
WFE_INST : {
// Stubbed, as WFE is a hint instruction.
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
- LOG_TRACE(Core_ARM11, "WFE executed.");
+ LOG_TRACE(Core_ARM, "WFE executed.");
}
cpu->Reg[15] += cpu->GetInstructionSize();
@@ -4541,7 +4541,7 @@ WFE_INST : {
WFI_INST : {
// Stubbed, as WFI is a hint instruction.
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
- LOG_TRACE(Core_ARM11, "WFI executed.");
+ LOG_TRACE(Core_ARM, "WFI executed.");
}
cpu->Reg[15] += cpu->GetInstructionSize();
@@ -4553,7 +4553,7 @@ WFI_INST : {
YIELD_INST : {
// Stubbed, as YIELD is a hint instruction.
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
- LOG_TRACE(Core_ARM11, "YIELD executed.");
+ LOG_TRACE(Core_ARM, "YIELD executed.");
}
cpu->Reg[15] += cpu->GetInstructionSize();
diff --git a/src/core/arm/dyncom/arm_dyncom_trans.cpp b/src/core/arm/dyncom/arm_dyncom_trans.cpp
index 780638638..9cd6c0dea 100644
--- a/src/core/arm/dyncom/arm_dyncom_trans.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_trans.cpp
@@ -185,7 +185,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index) {
inst_cream->opcode_1 = BITS(inst, 20, 23);
inst_cream->inst = inst;
- LOG_TRACE(Core_ARM11, "inst %x index %x", inst, index);
+ LOG_TRACE(Core_ARM, "inst %x index %x", inst, index);
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 05:51:47 +0100