diff options
Diffstat (limited to 'src/core')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_dec.cpp | 8 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 21 |
2 files changed, 15 insertions, 14 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp index 12181d0ec..411850f0f 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.cpp +++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp @@ -190,12 +190,12 @@ const ISEITEM arm_instruction[] = { { "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 }, { "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 }, { "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 }, - { "swi", 1, 0, 24, 27, 0x0000000f }, - { "bbl", 1, 0, 25, 27, 0x00000005 }, { "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 }, { "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 }, { "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 }, { "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 }, + { "swi", 1, 0, 24, 27, 0x0000000f }, + { "bbl", 1, 0, 25, 27, 0x00000005 }, }; const ISEITEM arm_exclusion_code[] = { @@ -383,12 +383,12 @@ const ISEITEM arm_exclusion_code[] = { { "cdp", 0, 0, 0 }, { "stc", 0, 0, 0 }, { "ldc", 0, 0, 0 }, - { "swi", 0, 0, 0 }, - { "bbl", 0, 0, 0 }, { "ldrexd", 0, ARMV6K, 0 }, { "strexd", 0, ARMV6K, 0 }, { "ldrexh", 0, ARMV6K, 0 }, { "strexh", 0, ARMV6K, 0 }, + { "swi", 0, 0, 0 }, + { "bbl", 0, 0, 0 }, { "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4] { "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3] diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 8c52bdb72..8de46294b 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -3544,12 +3544,12 @@ const transop_fp_t arm_instruction_trans[] = { INTERPRETER_TRANSLATE(cdp), INTERPRETER_TRANSLATE(stc), INTERPRETER_TRANSLATE(ldc), - INTERPRETER_TRANSLATE(swi), - INTERPRETER_TRANSLATE(bbl), INTERPRETER_TRANSLATE(ldrexd), INTERPRETER_TRANSLATE(strexd), INTERPRETER_TRANSLATE(ldrexh), INTERPRETER_TRANSLATE(strexh), + INTERPRETER_TRANSLATE(swi), + INTERPRETER_TRANSLATE(bbl), // All the thumb instructions should be placed the end of table INTERPRETER_TRANSLATE(b_2_thumb), @@ -3920,12 +3920,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { case 180: goto CDP_INST; \ case 181: goto STC_INST; \ case 182: goto LDC_INST; \ - case 183: goto SWI_INST; \ - case 184: goto BBL_INST; \ - case 185: goto LDREXD_INST; \ - case 186: goto STREXD_INST; \ - case 187: goto LDREXH_INST; \ - case 188: goto STREXH_INST; \ + case 183: goto LDREXD_INST; \ + case 184: goto STREXD_INST; \ + case 185: goto LDREXH_INST; \ + case 186: goto STREXH_INST; \ + case 187: goto SWI_INST; \ + case 188: goto BBL_INST; \ case 189: goto B_2_THUMB ; \ case 190: goto B_COND_THUMB ; \ case 191: goto BL_1_THUMB ; \ @@ -3980,8 +3980,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { &&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST, &&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST, &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST, - &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&LDREXD_INST, - &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST,&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH, + &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST, &&LDREXD_INST, + &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST, &&SWI_INST,&&BBL_INST, + &&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH, &&INIT_INST_LENGTH,&&END }; #endif |