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-rw-r--r--src/video_core/command_processor.cpp212
-rw-r--r--src/video_core/regs.h2
-rw-r--r--src/video_core/regs_framebuffer.h7
-rw-r--r--src/video_core/regs_pipeline.h8
-rw-r--r--src/video_core/regs_rasterizer.h8
-rw-r--r--src/video_core/regs_texturing.h33
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer.cpp7
-rw-r--r--src/video_core/renderer_opengl/gl_rasterizer.h201
-rw-r--r--src/video_core/renderer_opengl/gl_shader_gen.cpp142
-rw-r--r--src/video_core/renderer_opengl/gl_shader_gen.h123
-rw-r--r--src/video_core/renderer_opengl/gl_shader_util.h11
-rw-r--r--src/video_core/shader/shader.h7
-rw-r--r--src/video_core/shader/shader_interpreter.cpp2
-rw-r--r--src/video_core/shader/shader_jit_x64.cpp2
-rw-r--r--src/video_core/shader/shader_jit_x64_compiler.cpp4
-rw-r--r--src/video_core/shader/shader_jit_x64_compiler.h14
-rw-r--r--src/video_core/swrasterizer/rasterizer.cpp29
-rw-r--r--src/video_core/swrasterizer/texturing.cpp3
18 files changed, 482 insertions, 333 deletions
diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index 2e32ff905..8d3f76bde 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -32,12 +32,13 @@ namespace Pica {
namespace CommandProcessor {
-static int float_regs_counter = 0;
+static int vs_float_regs_counter = 0;
+static u32 vs_uniform_write_buffer[4];
-static u32 uniform_write_buffer[4];
+static int gs_float_regs_counter = 0;
+static u32 gs_uniform_write_buffer[4];
static int default_attr_counter = 0;
-
static u32 default_attr_write_buffer[3];
// Expand a 4-bit mask to 4-byte mask, e.g. 0b0101 -> 0x00FF00FF
@@ -48,6 +49,97 @@ static const u32 expand_bits_to_bytes[] = {
MICROPROFILE_DEFINE(GPU_Drawing, "GPU", "Drawing", MP_RGB(50, 50, 240));
+static const char* GetShaderSetupTypeName(Shader::ShaderSetup& setup) {
+ if (&setup == &g_state.vs) {
+ return "vertex shader";
+ }
+ if (&setup == &g_state.gs) {
+ return "geometry shader";
+ }
+ return "unknown shader";
+}
+
+static void WriteUniformBoolReg(Shader::ShaderSetup& setup, u32 value) {
+ for (unsigned i = 0; i < setup.uniforms.b.size(); ++i)
+ setup.uniforms.b[i] = (value & (1 << i)) != 0;
+}
+
+static void WriteUniformIntReg(Shader::ShaderSetup& setup, unsigned index,
+ const Math::Vec4<u8>& values) {
+ ASSERT(index < setup.uniforms.i.size());
+ setup.uniforms.i[index] = values;
+ LOG_TRACE(HW_GPU, "Set %s integer uniform %d to %02x %02x %02x %02x",
+ GetShaderSetupTypeName(setup), index, values.x, values.y, values.z, values.w);
+}
+
+static void WriteUniformFloatReg(ShaderRegs& config, Shader::ShaderSetup& setup,
+ int& float_regs_counter, u32 uniform_write_buffer[4], u32 value) {
+ auto& uniform_setup = config.uniform_setup;
+
+ // TODO: Does actual hardware indeed keep an intermediate buffer or does
+ // it directly write the values?
+ uniform_write_buffer[float_regs_counter++] = value;
+
+ // Uniforms are written in a packed format such that four float24 values are encoded in
+ // three 32-bit numbers. We write to internal memory once a full such vector is
+ // written.
+ if ((float_regs_counter >= 4 && uniform_setup.IsFloat32()) ||
+ (float_regs_counter >= 3 && !uniform_setup.IsFloat32())) {
+ float_regs_counter = 0;
+
+ auto& uniform = setup.uniforms.f[uniform_setup.index];
+
+ if (uniform_setup.index >= 96) {
+ LOG_ERROR(HW_GPU, "Invalid %s float uniform index %d", GetShaderSetupTypeName(setup),
+ (int)uniform_setup.index);
+ } else {
+
+ // NOTE: The destination component order indeed is "backwards"
+ if (uniform_setup.IsFloat32()) {
+ for (auto i : {0, 1, 2, 3})
+ uniform[3 - i] = float24::FromFloat32(*(float*)(&uniform_write_buffer[i]));
+ } else {
+ // TODO: Untested
+ uniform.w = float24::FromRaw(uniform_write_buffer[0] >> 8);
+ uniform.z = float24::FromRaw(((uniform_write_buffer[0] & 0xFF) << 16) |
+ ((uniform_write_buffer[1] >> 16) & 0xFFFF));
+ uniform.y = float24::FromRaw(((uniform_write_buffer[1] & 0xFFFF) << 8) |
+ ((uniform_write_buffer[2] >> 24) & 0xFF));
+ uniform.x = float24::FromRaw(uniform_write_buffer[2] & 0xFFFFFF);
+ }
+
+ LOG_TRACE(HW_GPU, "Set %s float uniform %x to (%f %f %f %f)",
+ GetShaderSetupTypeName(setup), (int)uniform_setup.index,
+ uniform.x.ToFloat32(), uniform.y.ToFloat32(), uniform.z.ToFloat32(),
+ uniform.w.ToFloat32());
+
+ // TODO: Verify that this actually modifies the register!
+ uniform_setup.index.Assign(uniform_setup.index + 1);
+ }
+ }
+}
+
+static void WriteProgramCode(ShaderRegs& config, Shader::ShaderSetup& setup,
+ unsigned max_program_code_length, u32 value) {
+ if (config.program.offset >= max_program_code_length) {
+ LOG_ERROR(HW_GPU, "Invalid %s program offset %d", GetShaderSetupTypeName(setup),
+ (int)config.program.offset);
+ } else {
+ setup.program_code[config.program.offset] = value;
+ config.program.offset++;
+ }
+}
+
+static void WriteSwizzlePatterns(ShaderRegs& config, Shader::ShaderSetup& setup, u32 value) {
+ if (config.swizzle_patterns.offset >= setup.swizzle_data.size()) {
+ LOG_ERROR(HW_GPU, "Invalid %s swizzle pattern offset %d", GetShaderSetupTypeName(setup),
+ (int)config.swizzle_patterns.offset);
+ } else {
+ setup.swizzle_data[config.swizzle_patterns.offset] = value;
+ config.swizzle_patterns.offset++;
+ }
+}
+
static void WritePicaReg(u32 id, u32 value, u32 mask) {
auto& regs = g_state.regs;
@@ -330,21 +422,70 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
break;
}
- case PICA_REG_INDEX(vs.bool_uniforms):
- for (unsigned i = 0; i < 16; ++i)
- g_state.vs.uniforms.b[i] = (regs.vs.bool_uniforms.Value() & (1 << i)) != 0;
+ case PICA_REG_INDEX(gs.bool_uniforms):
+ WriteUniformBoolReg(g_state.gs, g_state.regs.gs.bool_uniforms.Value());
+ break;
+ case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[0], 0x281):
+ case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[1], 0x282):
+ case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[2], 0x283):
+ case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[3], 0x284): {
+ unsigned index = (id - PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[0], 0x281));
+ auto values = regs.gs.int_uniforms[index];
+ WriteUniformIntReg(g_state.gs, index,
+ Math::Vec4<u8>(values.x, values.y, values.z, values.w));
+ break;
+ }
+
+ case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[0], 0x291):
+ case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[1], 0x292):
+ case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[2], 0x293):
+ case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[3], 0x294):
+ case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[4], 0x295):
+ case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[5], 0x296):
+ case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[6], 0x297):
+ case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[7], 0x298): {
+ WriteUniformFloatReg(g_state.regs.gs, g_state.gs, gs_float_regs_counter,
+ gs_uniform_write_buffer, value);
+ break;
+ }
+
+ case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[0], 0x29c):
+ case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[1], 0x29d):
+ case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[2], 0x29e):
+ case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[3], 0x29f):
+ case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[4], 0x2a0):
+ case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[5], 0x2a1):
+ case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[6], 0x2a2):
+ case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[7], 0x2a3): {
+ WriteProgramCode(g_state.regs.gs, g_state.gs, 4096, value);
+ break;
+ }
+
+ case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[0], 0x2a6):
+ case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[1], 0x2a7):
+ case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[2], 0x2a8):
+ case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[3], 0x2a9):
+ case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[4], 0x2aa):
+ case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[5], 0x2ab):
+ case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[6], 0x2ac):
+ case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[7], 0x2ad): {
+ WriteSwizzlePatterns(g_state.regs.gs, g_state.gs, value);
+ break;
+ }
+
+ case PICA_REG_INDEX(vs.bool_uniforms):
+ WriteUniformBoolReg(g_state.vs, g_state.regs.vs.bool_uniforms.Value());
break;
case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1):
case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[1], 0x2b2):
case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[2], 0x2b3):
case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[3], 0x2b4): {
- int index = (id - PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1));
+ unsigned index = (id - PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1));
auto values = regs.vs.int_uniforms[index];
- g_state.vs.uniforms.i[index] = Math::Vec4<u8>(values.x, values.y, values.z, values.w);
- LOG_TRACE(HW_GPU, "Set integer uniform %d to %02x %02x %02x %02x", index, values.x.Value(),
- values.y.Value(), values.z.Value(), values.w.Value());
+ WriteUniformIntReg(g_state.vs, index,
+ Math::Vec4<u8>(values.x, values.y, values.z, values.w));
break;
}
@@ -356,51 +497,11 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[5], 0x2c6):
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[6], 0x2c7):
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[7], 0x2c8): {
- auto& uniform_setup = regs.vs.uniform_setup;
-
- // TODO: Does actual hardware indeed keep an intermediate buffer or does
- // it directly write the values?
- uniform_write_buffer[float_regs_counter++] = value;
-
- // Uniforms are written in a packed format such that four float24 values are encoded in
- // three 32-bit numbers. We write to internal memory once a full such vector is
- // written.
- if ((float_regs_counter >= 4 && uniform_setup.IsFloat32()) ||
- (float_regs_counter >= 3 && !uniform_setup.IsFloat32())) {
- float_regs_counter = 0;
-
- auto& uniform = g_state.vs.uniforms.f[uniform_setup.index];
-
- if (uniform_setup.index > 95) {
- LOG_ERROR(HW_GPU, "Invalid VS uniform index %d", (int)uniform_setup.index);
- break;
- }
-
- // NOTE: The destination component order indeed is "backwards"
- if (uniform_setup.IsFloat32()) {
- for (auto i : {0, 1, 2, 3})
- uniform[3 - i] = float24::FromFloat32(*(float*)(&uniform_write_buffer[i]));
- } else {
- // TODO: Untested
- uniform.w = float24::FromRaw(uniform_write_buffer[0] >> 8);
- uniform.z = float24::FromRaw(((uniform_write_buffer[0] & 0xFF) << 16) |
- ((uniform_write_buffer[1] >> 16) & 0xFFFF));
- uniform.y = float24::FromRaw(((uniform_write_buffer[1] & 0xFFFF) << 8) |
- ((uniform_write_buffer[2] >> 24) & 0xFF));
- uniform.x = float24::FromRaw(uniform_write_buffer[2] & 0xFFFFFF);
- }
-
- LOG_TRACE(HW_GPU, "Set uniform %x to (%f %f %f %f)", (int)uniform_setup.index,
- uniform.x.ToFloat32(), uniform.y.ToFloat32(), uniform.z.ToFloat32(),
- uniform.w.ToFloat32());
-
- // TODO: Verify that this actually modifies the register!
- uniform_setup.index.Assign(uniform_setup.index + 1);
- }
+ WriteUniformFloatReg(g_state.regs.vs, g_state.vs, vs_float_regs_counter,
+ vs_uniform_write_buffer, value);
break;
}
- // Load shader program code
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[0], 0x2cc):
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[1], 0x2cd):
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[2], 0x2ce):
@@ -409,12 +510,10 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[5], 0x2d1):
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[6], 0x2d2):
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[7], 0x2d3): {
- g_state.vs.program_code[regs.vs.program.offset] = value;
- regs.vs.program.offset++;
+ WriteProgramCode(g_state.regs.vs, g_state.vs, 512, value);
break;
}
- // Load swizzle pattern data
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[0], 0x2d6):
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[1], 0x2d7):
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[2], 0x2d8):
@@ -423,8 +522,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[5], 0x2db):
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[6], 0x2dc):
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[7], 0x2dd): {
- g_state.vs.swizzle_data[regs.vs.swizzle_patterns.offset] = value;
- regs.vs.swizzle_patterns.offset++;
+ WriteSwizzlePatterns(g_state.regs.vs, g_state.vs, value);
break;
}
diff --git a/src/video_core/regs.h b/src/video_core/regs.h
index 86826088b..1776dad89 100644
--- a/src/video_core/regs.h
+++ b/src/video_core/regs.h
@@ -93,7 +93,7 @@ ASSERT_REG_POSITION(rasterizer.viewport_corner, 0x68);
ASSERT_REG_POSITION(rasterizer.depthmap_enable, 0x6D);
ASSERT_REG_POSITION(texturing, 0x80);
-ASSERT_REG_POSITION(texturing.texture0_enable, 0x80);
+ASSERT_REG_POSITION(texturing.main_config, 0x80);
ASSERT_REG_POSITION(texturing.texture0, 0x81);
ASSERT_REG_POSITION(texturing.texture0_format, 0x8e);
ASSERT_REG_POSITION(texturing.fragment_lighting_enable, 0x8f);
diff --git a/src/video_core/regs_framebuffer.h b/src/video_core/regs_framebuffer.h
index 9ddc79243..a50bd4111 100644
--- a/src/video_core/regs_framebuffer.h
+++ b/src/video_core/regs_framebuffer.h
@@ -211,13 +211,14 @@ struct FramebufferRegs {
BitField<0, 2, u32> allow_depth_stencil_write; // 0 = disable, else enable
};
- DepthFormat depth_format; // TODO: Should be a BitField!
+ BitField<0, 2, DepthFormat> depth_format;
+
BitField<16, 3, ColorFormat> color_format;
INSERT_PADDING_WORDS(0x4);
- u32 depth_buffer_address;
- u32 color_buffer_address;
+ BitField<0, 28, u32> depth_buffer_address;
+ BitField<0, 28, u32> color_buffer_address;
union {
// Apparently, the framebuffer width is stored as expected,
diff --git a/src/video_core/regs_pipeline.h b/src/video_core/regs_pipeline.h
index 0a4ec6e1e..31c747d77 100644
--- a/src/video_core/regs_pipeline.h
+++ b/src/video_core/regs_pipeline.h
@@ -22,10 +22,10 @@ struct PipelineRegs {
};
struct {
- BitField<0, 29, u32> base_address;
+ BitField<1, 28, u32> base_address;
PAddr GetPhysicalBaseAddress() const {
- return base_address * 8;
+ return base_address * 16;
}
// Descriptor for internal vertex attributes
@@ -99,7 +99,7 @@ struct PipelineRegs {
// This e.g. allows to load different attributes from different memory locations
struct {
// Source attribute data offset from the base address
- u32 data_offset;
+ BitField<0, 28, u32> data_offset;
union {
BitField<0, 4, u32> comp0;
@@ -180,6 +180,8 @@ struct PipelineRegs {
// kicked off.
// 2) Games can configure these registers to provide a command list subroutine mechanism.
+ // TODO: verify the bit length of these two fields
+ // According to 3dbrew, the bit length of them are 21 and 29, respectively
BitField<0, 20, u32> size[2]; ///< Size (in bytes / 8) of each channel's command buffer
BitField<0, 28, u32> addr[2]; ///< Physical address / 8 of each channel's command buffer
u32 trigger[2]; ///< Triggers execution of the channel's command buffer when written to
diff --git a/src/video_core/regs_rasterizer.h b/src/video_core/regs_rasterizer.h
index a471a3b38..2874fd127 100644
--- a/src/video_core/regs_rasterizer.h
+++ b/src/video_core/regs_rasterizer.h
@@ -92,13 +92,13 @@ struct RasterizerRegs {
BitField<0, 2, ScissorMode> mode;
union {
- BitField<0, 16, u32> x1;
- BitField<16, 16, u32> y1;
+ BitField<0, 10, u32> x1;
+ BitField<16, 10, u32> y1;
};
union {
- BitField<0, 16, u32> x2;
- BitField<16, 16, u32> y2;
+ BitField<0, 10, u32> x2;
+ BitField<16, 10, u32> y2;
};
} scissor_test;
diff --git a/src/video_core/regs_texturing.h b/src/video_core/regs_texturing.h
index be8bc6826..3318812da 100644
--- a/src/video_core/regs_texturing.h
+++ b/src/video_core/regs_texturing.h
@@ -29,6 +29,11 @@ struct TexturingRegs {
ClampToBorder = 1,
Repeat = 2,
MirroredRepeat = 3,
+ // Mode 4-7 produces some weird result and may be just invalid:
+ // 4: Positive coord: clamp to edge; negative coord: repeat
+ // 5: Positive coord: clamp to border; negative coord: repeat
+ // 6: Repeat
+ // 7: Repeat
};
enum TextureFilter : u32 {
@@ -45,22 +50,22 @@ struct TexturingRegs {
} border_color;
union {
- BitField<0, 16, u32> height;
- BitField<16, 16, u32> width;
+ BitField<0, 11, u32> height;
+ BitField<16, 11, u32> width;
};
union {
BitField<1, 1, TextureFilter> mag_filter;
BitField<2, 1, TextureFilter> min_filter;
- BitField<8, 2, WrapMode> wrap_t;
- BitField<12, 2, WrapMode> wrap_s;
- BitField<28, 2, TextureType>
- type; ///< @note Only valid for texture 0 according to 3DBrew.
+ BitField<8, 3, WrapMode> wrap_t;
+ BitField<12, 3, WrapMode> wrap_s;
+ /// @note Only valid for texture 0 according to 3DBrew.
+ BitField<28, 3, TextureType> type;
};
INSERT_PADDING_WORDS(0x1);
- u32 address;
+ BitField<0, 28, u32> address;
PAddr GetPhysicalAddress() const {
return address * 8;
@@ -122,7 +127,11 @@ struct TexturingRegs {
BitField<0, 1, u32> texture0_enable;
BitField<1, 1, u32> texture1_enable;
BitField<2, 1, u32> texture2_enable;
- };
+ BitField<8, 2, u32> texture3_coordinates; // TODO: unimplemented
+ BitField<10, 1, u32> texture3_enable; // TODO: unimplemented
+ BitField<13, 1, u32> texture2_use_coord1;
+ BitField<16, 1, u32> clear_texture_cache; // TODO: unimplemented
+ } main_config;
TextureConfig texture0;
INSERT_PADDING_WORDS(0x8);
BitField<0, 4, TextureFormat> texture0_format;
@@ -142,9 +151,9 @@ struct TexturingRegs {
};
const std::array<FullTextureConfig, 3> GetTextures() const {
return {{
- {texture0_enable.ToBool(), texture0, texture0_format},
- {texture1_enable.ToBool(), texture1, texture1_format},
- {texture2_enable.ToBool(), texture2, texture2_format},
+ {main_config.texture0_enable.ToBool(), texture0, texture0_format},
+ {main_config.texture1_enable.ToBool(), texture1, texture1_format},
+ {main_config.texture2_enable.ToBool(), texture2, texture2_format},
}};
}
@@ -199,7 +208,7 @@ struct TexturingRegs {
Lerp = 4,
Subtract = 5,
Dot3_RGB = 6,
-
+ Dot3_RGBA = 7,
MultiplyThenAdd = 8,
AddThenMultiply = 9,
};
diff --git a/src/video_core/renderer_opengl/gl_rasterizer.cpp b/src/video_core/renderer_opengl/gl_rasterizer.cpp
index de1d5eba7..12ac9bbd9 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer.cpp
+++ b/src/video_core/renderer_opengl/gl_rasterizer.cpp
@@ -20,7 +20,6 @@
#include "video_core/regs_texturing.h"
#include "video_core/renderer_opengl/gl_rasterizer.h"
#include "video_core/renderer_opengl/gl_shader_gen.h"
-#include "video_core/renderer_opengl/gl_shader_util.h"
#include "video_core/renderer_opengl/pica_to_gl.h"
#include "video_core/renderer_opengl/renderer_opengl.h"
@@ -403,6 +402,10 @@ void RasterizerOpenGL::NotifyPicaRegisterChanged(u32 id) {
SyncLogicOp();
break;
+ case PICA_REG_INDEX(texturing.main_config):
+ shader_dirty = true;
+ break;
+
// Texture 0 type
case PICA_REG_INDEX(texturing.texture0.type):
shader_dirty = true;
@@ -1005,7 +1008,7 @@ void RasterizerOpenGL::SamplerInfo::SyncWithConfig(
}
void RasterizerOpenGL::SetShader() {
- PicaShaderConfig config = PicaShaderConfig::CurrentConfig();
+ auto config = GLShader::PicaShaderConfig::BuildFromRegs(Pica::g_state.regs);
std::unique_ptr<PicaShader> shader = std::make_unique<PicaShader>();
// Find (or generate) the GLSL shader for the current TEV state
diff --git a/src/video_core/renderer_opengl/gl_rasterizer.h b/src/video_core/renderer_opengl/gl_rasterizer.h
index ecf737438..3e1770d77 100644
--- a/src/video_core/renderer_opengl/gl_rasterizer.h
+++ b/src/video_core/renderer_opengl/gl_rasterizer.h
@@ -25,210 +25,13 @@
#include "video_core/regs_texturing.h"
#include "video_core/renderer_opengl/gl_rasterizer_cache.h"
#include "video_core/renderer_opengl/gl_resource_manager.h"
+#include "video_core/renderer_opengl/gl_shader_gen.h"
#include "video_core/renderer_opengl/gl_state.h"
#include "video_core/renderer_opengl/pica_to_gl.h"
#include "video_core/shader/shader.h"
struct ScreenInfo;
-/**
- * This struct contains all state used to generate the GLSL shader program that emulates the current
- * Pica register configuration. This struct is used as a cache key for generated GLSL shader
- * programs. The functions in gl_shader_gen.cpp should retrieve state from this struct only, not by
- * directly accessing Pica registers. This should reduce the risk of bugs in shader generation where
- * Pica state is not being captured in the shader cache key, thereby resulting in (what should be)
- * two separate shaders sharing the same key.
- *
- * We use a union because "implicitly-defined copy/move constructor for a union X copies the object
- * representation of X." and "implicitly-defined copy assignment operator for a union X copies the
- * object representation (3.9) of X." = Bytewise copy instead of memberwise copy. This is important
- * because the padding bytes are included in the hash and comparison between objects.
- */
-union PicaShaderConfig {
-
- /// Construct a PicaShaderConfig with the current Pica register configuration.
- static PicaShaderConfig CurrentConfig() {
- PicaShaderConfig res;
-
- auto& state = res.state;
- std::memset(&state, 0, sizeof(PicaShaderConfig::State));
-
- const auto& regs = Pica::g_state.regs;
-
- state.scissor_test_mode = regs.rasterizer.scissor_test.mode;
-
- state.depthmap_enable = regs.rasterizer.depthmap_enable;
-
- state.alpha_test_func = regs.framebuffer.output_merger.alpha_test.enable
- ? regs.framebuffer.output_merger.alpha_test.func.Value()
- : Pica::FramebufferRegs::CompareFunc::Always;
-
- state.texture0_type = regs.texturing.texture0.type;
-
- // Copy relevant tev stages fields.
- // We don't sync const_color here because of the high variance, it is a
- // shader uniform instead.
- const auto& tev_stages = regs.texturing.GetTevStages();
- DEBUG_ASSERT(state.tev_stages.size() == tev_stages.size());
- for (size_t i = 0; i < tev_stages.size(); i++) {
- const auto& tev_stage = tev_stages[i];
- state.tev_stages[i].sources_raw = tev_stage.sources_raw;
- state.tev_stages[i].modifiers_raw = tev_stage.modifiers_raw;
- state.tev_stages[i].ops_raw = tev_stage.ops_raw;
- state.tev_stages[i].scales_raw = tev_stage.scales_raw;
- }
-
- state.fog_mode = regs.texturing.fog_mode;
- state.fog_flip = regs.texturing.fog_flip != 0;
-
- state.combiner_buffer_input =
- regs.texturing.tev_combiner_buffer_input.update_mask_rgb.Value() |
- regs.texturing.tev_combiner_buffer_input.update_mask_a.Value() << 4;
-
- // Fragment lighting
-
- state.lighting.enable = !regs.lighting.disable;
- state.lighting.src_num = regs.lighting.max_light_index + 1;
-
- for (unsigned light_index = 0; light_index < state.lighting.src_num; ++light_index) {
- unsigned num = regs.lighting.light_enable.GetNum(light_index);
- const auto& light = regs.lighting.light[num];
- state.lighting.light[light_index].num = num;
- state.lighting.light[light_index].directional = light.config.directional != 0;
- state.lighting.light[light_index].two_sided_diffuse =
- light.config.two_sided_diffuse != 0;
- state.lighting.light[light_index].dist_atten_enable =
- !regs.lighting.IsDistAttenDisabled(num);
- }
-
- state.lighting.lut_d0.enable = regs.lighting.config1.disable_lut_d0 == 0;
- state.lighting.lut_d0.abs_input = regs.lighting.abs_lut_input.disable_d0 == 0;
- state.lighting.lut_d0.type = regs.lighting.lut_input.d0.Value();
- state.lighting.lut_d0.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.d0);
-
- state.lighting.lut_d1.enable = regs.lighting.config1.disable_lut_d1 == 0;
- state.lighting.lut_d1.abs_input = regs.lighting.abs_lut_input.disable_d1 == 0;
- state.lighting.lut_d1.type = regs.lighting.lut_input.d1.Value();
- state.lighting.lut_d1.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.d1);
-
- state.lighting.lut_fr.enable = regs.lighting.config1.disable_lut_fr == 0;
- state.lighting.lut_fr.abs_input = regs.lighting.abs_lut_input.disable_fr == 0;
- state.lighting.lut_fr.type = regs.lighting.lut_input.fr.Value();
- state.lighting.lut_fr.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.fr);
-
- state.lighting.lut_rr.enable = regs.lighting.config1.disable_lut_rr == 0;
- state.lighting.lut_rr.abs_input = regs.lighting.abs_lut_input.disable_rr == 0;
- state.lighting.lut_rr.type = regs.lighting.lut_input.rr.Value();
- state.lighting.lut_rr.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.rr);
-
- state.lighting.lut_rg.enable = regs.lighting.config1.disable_lut_rg == 0;
- state.lighting.lut_rg.abs_input = regs.lighting.abs_lut_input.disable_rg == 0;
- state.lighting.lut_rg.type = regs.lighting.lut_input.rg.Value();
- state.lighting.lut_rg.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.rg);
-
- state.lighting.lut_rb.enable = regs.lighting.config1.disable_lut_rb == 0;
- state.lighting.lut_rb.abs_input = regs.lighting.abs_lut_input.disable_rb == 0;
- state.lighting.lut_rb.type = regs.lighting.lut_input.rb.Value();
- state.lighting.lut_rb.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.rb);
-
- state.lighting.config = regs.lighting.config0.config;
- state.lighting.fresnel_selector = regs.lighting.config0.fresnel_selector;
- state.lighting.bump_mode = regs.lighting.config0.bump_mode;
- state.lighting.bump_selector = regs.lighting.config0.bump_selector;
- state.lighting.bump_renorm = regs.lighting.config0.disable_bump_renorm == 0;
- state.lighting.clamp_highlights = regs.lighting.config0.clamp_highlights != 0;
-
- return res;
- }
-
- bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
- return (stage_index < 4) && (state.combiner_buffer_input & (1 << stage_index));
- }
-
- bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
- return (stage_index < 4) && ((state.combiner_buffer_input >> 4) & (1 << stage_index));
- }
-
- bool operator==(const PicaShaderConfig& o) const {
- return std::memcmp(&state, &o.state, sizeof(PicaShaderConfig::State)) == 0;
- };
-
- // NOTE: MSVC15 (Update 2) doesn't think `delete`'d constructors and operators are TC.
- // This makes BitField not TC when used in a union or struct so we have to resort
- // to this ugly hack.
- // Once that bug is fixed we can use Pica::Regs::TevStageConfig here.
- // Doesn't include const_color because we don't sync it, see comment in CurrentConfig()
- struct TevStageConfigRaw {
- u32 sources_raw;
- u32 modifiers_raw;
- u32 ops_raw;
- u32 scales_raw;
- explicit operator Pica::TexturingRegs::TevStageConfig() const noexcept {
- Pica::TexturingRegs::TevStageConfig stage;
- stage.sources_raw = sources_raw;
- stage.modifiers_raw = modifiers_raw;
- stage.ops_raw = ops_raw;
- stage.const_color = 0;
- stage.scales_raw = scales_raw;
- return stage;
- }
- };
-
- struct State {
- Pica::FramebufferRegs::CompareFunc alpha_test_func;
- Pica::RasterizerRegs::ScissorMode scissor_test_mode;
- Pica::TexturingRegs::TextureConfig::TextureType texture0_type;
- std::array<TevStageConfigRaw, 6> tev_stages;
- u8 combiner_buffer_input;
-
- Pica::RasterizerRegs::DepthBuffering depthmap_enable;
- Pica::TexturingRegs::FogMode fog_mode;
- bool fog_flip;
-
- struct {
- struct {
- unsigned num;
- bool directional;
- bool two_sided_diffuse;
- bool dist_atten_enable;
- } light[8];
-
- bool enable;
- unsigned src_num;
- Pica::LightingRegs::LightingBumpMode bump_mode;
- unsigned bump_selector;
- bool bump_renorm;
- bool clamp_highlights;
-
- Pica::LightingRegs::LightingConfig config;
- Pica::LightingRegs::LightingFresnelSelector fresnel_selector;
-
- struct {
- bool enable;
- bool abs_input;
- Pica::LightingRegs::LightingLutInput type;
- float scale;
- } lut_d0, lut_d1, lut_fr, lut_rr, lut_rg, lut_rb;
- } lighting;
-
- } state;
-};
-#if (__GNUC__ >= 5) || defined(__clang__) || defined(_MSC_VER)
-static_assert(std::is_trivially_copyable<PicaShaderConfig::State>::value,
- "PicaShaderConfig::State must be trivially copyable");
-#endif
-
-namespace std {
-
-template <>
-struct hash<PicaShaderConfig> {
- size_t operator()(const PicaShaderConfig& k) const {
- return Common::ComputeHash64(&k.state, sizeof(PicaShaderConfig::State));
- }
-};
-
-} // namespace std
-
class RasterizerOpenGL : public VideoCore::RasterizerInterface {
public:
RasterizerOpenGL();
@@ -437,7 +240,7 @@ private:
std::vector<HardwareVertex> vertex_batch;
- std::unordered_map<PicaShaderConfig, std::unique_ptr<PicaShader>> shader_cache;
+ std::unordered_map<GLShader::PicaShaderConfig, std::unique_ptr<PicaShader>> shader_cache;
const PicaShader* current_shader = nullptr;
bool shader_dirty;
diff --git a/src/video_core/renderer_opengl/gl_shader_gen.cpp b/src/video_core/renderer_opengl/gl_shader_gen.cpp
index 7abdeba05..7b44dade8 100644
--- a/src/video_core/renderer_opengl/gl_shader_gen.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_gen.cpp
@@ -4,6 +4,7 @@
#include <array>
#include <cstddef>
+#include <cstring>
#include "common/assert.h"
#include "common/bit_field.h"
#include "common/logging/log.h"
@@ -23,6 +24,99 @@ using TevStageConfig = TexturingRegs::TevStageConfig;
namespace GLShader {
+PicaShaderConfig PicaShaderConfig::BuildFromRegs(const Pica::Regs& regs) {
+ PicaShaderConfig res;
+
+ auto& state = res.state;
+ std::memset(&state, 0, sizeof(PicaShaderConfig::State));
+
+ state.scissor_test_mode = regs.rasterizer.scissor_test.mode;
+
+ state.depthmap_enable = regs.rasterizer.depthmap_enable;
+
+ state.alpha_test_func = regs.framebuffer.output_merger.alpha_test.enable
+ ? regs.framebuffer.output_merger.alpha_test.func.Value()
+ : Pica::FramebufferRegs::CompareFunc::Always;
+
+ state.texture0_type = regs.texturing.texture0.type;
+
+ state.texture2_use_coord1 = regs.texturing.main_config.texture2_use_coord1 != 0;
+
+ // Copy relevant tev stages fields.
+ // We don't sync const_color here because of the high variance, it is a
+ // shader uniform instead.
+ const auto& tev_stages = regs.texturing.GetTevStages();
+ DEBUG_ASSERT(state.tev_stages.size() == tev_stages.size());
+ for (size_t i = 0; i < tev_stages.size(); i++) {
+ const auto& tev_stage = tev_stages[i];
+ state.tev_stages[i].sources_raw = tev_stage.sources_raw;
+ state.tev_stages[i].modifiers_raw = tev_stage.modifiers_raw;
+ state.tev_stages[i].ops_raw = tev_stage.ops_raw;
+ state.tev_stages[i].scales_raw = tev_stage.scales_raw;
+ }
+
+ state.fog_mode = regs.texturing.fog_mode;
+ state.fog_flip = regs.texturing.fog_flip != 0;
+
+ state.combiner_buffer_input = regs.texturing.tev_combiner_buffer_input.update_mask_rgb.Value() |
+ regs.texturing.tev_combiner_buffer_input.update_mask_a.Value()
+ << 4;
+
+ // Fragment lighting
+
+ state.lighting.enable = !regs.lighting.disable;
+ state.lighting.src_num = regs.lighting.max_light_index + 1;
+
+ for (unsigned light_index = 0; light_index < state.lighting.src_num; ++light_index) {
+ unsigned num = regs.lighting.light_enable.GetNum(light_index);
+ const auto& light = regs.lighting.light[num];
+ state.lighting.light[light_index].num = num;
+ state.lighting.light[light_index].directional = light.config.directional != 0;
+ state.lighting.light[light_index].two_sided_diffuse = light.config.two_sided_diffuse != 0;
+ state.lighting.light[light_index].dist_atten_enable =
+ !regs.lighting.IsDistAttenDisabled(num);
+ }
+
+ state.lighting.lut_d0.enable = regs.lighting.config1.disable_lut_d0 == 0;
+ state.lighting.lut_d0.abs_input = regs.lighting.abs_lut_input.disable_d0 == 0;
+ state.lighting.lut_d0.type = regs.lighting.lut_input.d0.Value();
+ state.lighting.lut_d0.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.d0);
+
+ state.lighting.lut_d1.enable = regs.lighting.config1.disable_lut_d1 == 0;
+ state.lighting.lut_d1.abs_input = regs.lighting.abs_lut_input.disable_d1 == 0;
+ state.lighting.lut_d1.type = regs.lighting.lut_input.d1.Value();
+ state.lighting.lut_d1.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.d1);
+
+ state.lighting.lut_fr.enable = regs.lighting.config1.disable_lut_fr == 0;
+ state.lighting.lut_fr.abs_input = regs.lighting.abs_lut_input.disable_fr == 0;
+ state.lighting.lut_fr.type = regs.lighting.lut_input.fr.Value();
+ state.lighting.lut_fr.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.fr);
+
+ state.lighting.lut_rr.enable = regs.lighting.config1.disable_lut_rr == 0;
+ state.lighting.lut_rr.abs_input = regs.lighting.abs_lut_input.disable_rr == 0;
+ state.lighting.lut_rr.type = regs.lighting.lut_input.rr.Value();
+ state.lighting.lut_rr.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.rr);
+
+ state.lighting.lut_rg.enable = regs.lighting.config1.disable_lut_rg == 0;
+ state.lighting.lut_rg.abs_input = regs.lighting.abs_lut_input.disable_rg == 0;
+ state.lighting.lut_rg.type = regs.lighting.lut_input.rg.Value();
+ state.lighting.lut_rg.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.rg);
+
+ state.lighting.lut_rb.enable = regs.lighting.config1.disable_lut_rb == 0;
+ state.lighting.lut_rb.abs_input = regs.lighting.abs_lut_input.disable_rb == 0;
+ state.lighting.lut_rb.type = regs.lighting.lut_input.rb.Value();
+ state.lighting.lut_rb.scale = regs.lighting.lut_scale.GetScale(regs.lighting.lut_scale.rb);
+
+ state.lighting.config = regs.lighting.config0.config;
+ state.lighting.fresnel_selector = regs.lighting.config0.fresnel_selector;
+ state.lighting.bump_mode = regs.lighting.config0.bump_mode;
+ state.lighting.bump_selector = regs.lighting.config0.bump_selector;
+ state.lighting.bump_renorm = regs.lighting.config0.disable_bump_renorm == 0;
+ state.lighting.clamp_highlights = regs.lighting.config0.clamp_highlights != 0;
+
+ return res;
+}
+
/// Detects if a TEV stage is configured to be skipped (to avoid generating unnecessary code)
static bool IsPassThroughTevStage(const TevStageConfig& stage) {
return (stage.color_op == TevStageConfig::Operation::Replace &&
@@ -34,6 +128,15 @@ static bool IsPassThroughTevStage(const TevStageConfig& stage) {
stage.GetColorMultiplier() == 1 && stage.GetAlphaMultiplier() == 1);
}
+static std::string TexCoord(const PicaShaderConfig& config, int texture_unit) {
+ if (texture_unit == 2 && config.state.texture2_use_coord1) {
+ return "texcoord[1]";
+ }
+ // TODO: if texture unit 3 (procedural texture) implementation also uses this function,
+ // config.state.texture3_coordinates should be repected here.
+ return "texcoord[" + std::to_string(texture_unit) + "]";
+}
+
/// Writes the specified TEV stage source component(s)
static void AppendSource(std::string& out, const PicaShaderConfig& config,
TevStageConfig::Source source, const std::string& index_name) {
@@ -70,7 +173,7 @@ static void AppendSource(std::string& out, const PicaShaderConfig& config,
out += "texture(tex[1], texcoord[1])";
break;
case Source::Texture2:
- out += "texture(tex[2], texcoord[2])";
+ out += "texture(tex[2], " + TexCoord(config, 2) + ")";
break;
case Source::PreviousBuffer:
out += "combiner_buffer";
@@ -214,8 +317,6 @@ static void AppendColorCombiner(std::string& out, TevStageConfig::Operation oper
out += variable_name + "[0] + " + variable_name + "[1] - vec3(0.5)";
break;
case Operation::Lerp:
- // TODO(bunnei): Verify if HW actually does this per-component, otherwise we can just use
- // builtin lerp
out += variable_name + "[0] * " + variable_name + "[2] + " + variable_name +
"[1] * (vec3(1.0) - " + variable_name + "[2])";
break;
@@ -230,6 +331,7 @@ static void AppendColorCombiner(std::string& out, TevStageConfig::Operation oper
variable_name + "[2]";
break;
case Operation::Dot3_RGB:
+ case Operation::Dot3_RGBA:
out += "vec3(dot(" + variable_name + "[0] - vec3(0.5), " + variable_name +
"[1] - vec3(0.5)) * 4.0)";
break;
@@ -329,17 +431,25 @@ static void WriteTevStage(std::string& out, const PicaShaderConfig& config, unsi
AppendColorCombiner(out, stage.color_op, "color_results_" + index_name);
out += ";\n";
- out += "float alpha_results_" + index_name + "[3] = float[3](";
- AppendAlphaModifier(out, config, stage.alpha_modifier1, stage.alpha_source1, index_name);
- out += ", ";
- AppendAlphaModifier(out, config, stage.alpha_modifier2, stage.alpha_source2, index_name);
- out += ", ";
- AppendAlphaModifier(out, config, stage.alpha_modifier3, stage.alpha_source3, index_name);
- out += ");\n";
-
- out += "float alpha_output_" + index_name + " = ";
- AppendAlphaCombiner(out, stage.alpha_op, "alpha_results_" + index_name);
- out += ";\n";
+ if (stage.color_op == TevStageConfig::Operation::Dot3_RGBA) {
+ // result of Dot3_RGBA operation is also placed to the alpha component
+ out += "float alpha_output_" + index_name + " = color_output_" + index_name + "[0];\n";
+ } else {
+ out += "float alpha_results_" + index_name + "[3] = float[3](";
+ AppendAlphaModifier(out, config, stage.alpha_modifier1, stage.alpha_source1,
+ index_name);
+ out += ", ";
+ AppendAlphaModifier(out, config, stage.alpha_modifier2, stage.alpha_source2,
+ index_name);
+ out += ", ";
+ AppendAlphaModifier(out, config, stage.alpha_modifier3, stage.alpha_source3,
+ index_name);
+ out += ");\n";
+
+ out += "float alpha_output_" + index_name + " = ";
+ AppendAlphaCombiner(out, stage.alpha_op, "alpha_results_" + index_name);
+ out += ";\n";
+ }
out += "last_tex_env_out = vec4("
"clamp(color_output_" +
@@ -374,8 +484,8 @@ static void WriteLighting(std::string& out, const PicaShaderConfig& config) {
// Bump mapping is enabled using a normal map, read perturbation vector from the selected
// texture
std::string bump_selector = std::to_string(lighting.bump_selector);
- out += "vec3 surface_normal = 2.0 * texture(tex[" + bump_selector + "], texcoord[" +
- bump_selector + "]).rgb - 1.0;\n";
+ out += "vec3 surface_normal = 2.0 * texture(tex[" + bump_selector + "], " +
+ TexCoord(config, lighting.bump_selector) + ").rgb - 1.0;\n";
// Recompute Z-component of perturbation if 'renorm' is enabled, this provides a higher
// precision result
diff --git a/src/video_core/renderer_opengl/gl_shader_gen.h b/src/video_core/renderer_opengl/gl_shader_gen.h
index bef3249cf..3fb046b76 100644
--- a/src/video_core/renderer_opengl/gl_shader_gen.h
+++ b/src/video_core/renderer_opengl/gl_shader_gen.h
@@ -4,12 +4,122 @@
#pragma once
+#include <array>
+#include <cstring>
+#include <functional>
#include <string>
-
-union PicaShaderConfig;
+#include <type_traits>
+#include "video_core/regs.h"
namespace GLShader {
+enum Attributes {
+ ATTRIBUTE_POSITION,
+ ATTRIBUTE_COLOR,
+ ATTRIBUTE_TEXCOORD0,
+ ATTRIBUTE_TEXCOORD1,
+ ATTRIBUTE_TEXCOORD2,
+ ATTRIBUTE_TEXCOORD0_W,
+ ATTRIBUTE_NORMQUAT,
+ ATTRIBUTE_VIEW,
+};
+
+/**
+ * This struct contains all state used to generate the GLSL shader program that emulates the current
+ * Pica register configuration. This struct is used as a cache key for generated GLSL shader
+ * programs. The functions in gl_shader_gen.cpp should retrieve state from this struct only, not by
+ * directly accessing Pica registers. This should reduce the risk of bugs in shader generation where
+ * Pica state is not being captured in the shader cache key, thereby resulting in (what should be)
+ * two separate shaders sharing the same key.
+ *
+ * We use a union because "implicitly-defined copy/move constructor for a union X copies the object
+ * representation of X." and "implicitly-defined copy assignment operator for a union X copies the
+ * object representation (3.9) of X." = Bytewise copy instead of memberwise copy. This is important
+ * because the padding bytes are included in the hash and comparison between objects.
+ */
+union PicaShaderConfig {
+
+ /// Construct a PicaShaderConfig with the given Pica register configuration.
+ static PicaShaderConfig BuildFromRegs(const Pica::Regs& regs);
+
+ bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
+ return (stage_index < 4) && (state.combiner_buffer_input & (1 << stage_index));
+ }
+
+ bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
+ return (stage_index < 4) && ((state.combiner_buffer_input >> 4) & (1 << stage_index));
+ }
+
+ bool operator==(const PicaShaderConfig& o) const {
+ return std::memcmp(&state, &o.state, sizeof(PicaShaderConfig::State)) == 0;
+ };
+
+ // NOTE: MSVC15 (Update 2) doesn't think `delete`'d constructors and operators are TC.
+ // This makes BitField not TC when used in a union or struct so we have to resort
+ // to this ugly hack.
+ // Once that bug is fixed we can use Pica::Regs::TevStageConfig here.
+ // Doesn't include const_color because we don't sync it, see comment in BuildFromRegs()
+ struct TevStageConfigRaw {
+ u32 sources_raw;
+ u32 modifiers_raw;
+ u32 ops_raw;
+ u32 scales_raw;
+ explicit operator Pica::TexturingRegs::TevStageConfig() const noexcept {
+ Pica::TexturingRegs::TevStageConfig stage;
+ stage.sources_raw = sources_raw;
+ stage.modifiers_raw = modifiers_raw;
+ stage.ops_raw = ops_raw;
+ stage.const_color = 0;
+ stage.scales_raw = scales_raw;
+ return stage;
+ }
+ };
+
+ struct State {
+ Pica::FramebufferRegs::CompareFunc alpha_test_func;
+ Pica::RasterizerRegs::ScissorMode scissor_test_mode;
+ Pica::TexturingRegs::TextureConfig::TextureType texture0_type;
+ bool texture2_use_coord1;
+ std::array<TevStageConfigRaw, 6> tev_stages;
+ u8 combiner_buffer_input;
+
+ Pica::RasterizerRegs::DepthBuffering depthmap_enable;
+ Pica::TexturingRegs::FogMode fog_mode;
+ bool fog_flip;
+
+ struct {
+ struct {
+ unsigned num;
+ bool directional;
+ bool two_sided_diffuse;
+ bool dist_atten_enable;
+ } light[8];
+
+ bool enable;
+ unsigned src_num;
+ Pica::LightingRegs::LightingBumpMode bump_mode;
+ unsigned bump_selector;
+ bool bump_renorm;
+ bool clamp_highlights;
+
+ Pica::LightingRegs::LightingConfig config;
+ Pica::LightingRegs::LightingFresnelSelector fresnel_selector;
+
+ struct {
+ bool enable;
+ bool abs_input;
+ Pica::LightingRegs::LightingLutInput type;
+ float scale;
+ } lut_d0, lut_d1, lut_fr, lut_rr, lut_rg, lut_rb;
+ } lighting;
+
+ } state;
+};
+#if (__GNUC__ >= 5) || defined(__clang__) || defined(_MSC_VER)
+static_assert(std::is_trivially_copyable<PicaShaderConfig::State>::value,
+ "PicaShaderConfig::State must be trivially copyable");
+#endif
+
/**
* Generates the GLSL vertex shader program source code for the current Pica state
* @returns String of the shader source code
@@ -25,3 +135,12 @@ std::string GenerateVertexShader();
std::string GenerateFragmentShader(const PicaShaderConfig& config);
} // namespace GLShader
+
+namespace std {
+template <>
+struct hash<GLShader::PicaShaderConfig> {
+ size_t operator()(const GLShader::PicaShaderConfig& k) const {
+ return Common::ComputeHash64(&k.state, sizeof(GLShader::PicaShaderConfig::State));
+ }
+};
+} // namespace std
diff --git a/src/video_core/renderer_opengl/gl_shader_util.h b/src/video_core/renderer_opengl/gl_shader_util.h
index f59912f79..c66e8acd3 100644
--- a/src/video_core/renderer_opengl/gl_shader_util.h
+++ b/src/video_core/renderer_opengl/gl_shader_util.h
@@ -8,17 +8,6 @@
namespace GLShader {
-enum Attributes {
- ATTRIBUTE_POSITION,
- ATTRIBUTE_COLOR,
- ATTRIBUTE_TEXCOORD0,
- ATTRIBUTE_TEXCOORD1,
- ATTRIBUTE_TEXCOORD2,
- ATTRIBUTE_TEXCOORD0_W,
- ATTRIBUTE_NORMQUAT,
- ATTRIBUTE_VIEW,
-};
-
/**
* Utility function to create and compile an OpenGL GLSL shader program (vertex + fragment shader)
* @param vertex_shader String of the GLSL vertex shader program
diff --git a/src/video_core/shader/shader.h b/src/video_core/shader/shader.h
index 38ea717ab..e156f6aef 100644
--- a/src/video_core/shader/shader.h
+++ b/src/video_core/shader/shader.h
@@ -24,6 +24,9 @@ namespace Pica {
namespace Shader {
+constexpr unsigned MAX_PROGRAM_CODE_LENGTH = 4096;
+constexpr unsigned MAX_SWIZZLE_DATA_LENGTH = 4096;
+
struct AttributeBuffer {
alignas(16) Math::Vec4<float24> attr[16];
};
@@ -144,8 +147,8 @@ struct ShaderSetup {
return offsetof(ShaderSetup, uniforms.i) + index * sizeof(Math::Vec4<u8>);
}
- std::array<u32, 1024> program_code;
- std::array<u32, 1024> swizzle_data;
+ std::array<u32, MAX_PROGRAM_CODE_LENGTH> program_code;
+ std::array<u32, MAX_SWIZZLE_DATA_LENGTH> swizzle_data;
/// Data private to ShaderEngines
struct EngineData {
diff --git a/src/video_core/shader/shader_interpreter.cpp b/src/video_core/shader/shader_interpreter.cpp
index f4d1c46c5..aa1cec81f 100644
--- a/src/video_core/shader/shader_interpreter.cpp
+++ b/src/video_core/shader/shader_interpreter.cpp
@@ -653,7 +653,7 @@ static void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData
}
void InterpreterEngine::SetupBatch(ShaderSetup& setup, unsigned int entry_point) {
- ASSERT(entry_point < 1024);
+ ASSERT(entry_point < MAX_PROGRAM_CODE_LENGTH);
setup.engine_data.entry_point = entry_point;
}
diff --git a/src/video_core/shader/shader_jit_x64.cpp b/src/video_core/shader/shader_jit_x64.cpp
index 0ee0dd9ef..73c21871c 100644
--- a/src/video_core/shader/shader_jit_x64.cpp
+++ b/src/video_core/shader/shader_jit_x64.cpp
@@ -15,7 +15,7 @@ JitX64Engine::JitX64Engine() = default;
JitX64Engine::~JitX64Engine() = default;
void JitX64Engine::SetupBatch(ShaderSetup& setup, unsigned int entry_point) {
- ASSERT(entry_point < 1024);
+ ASSERT(entry_point < MAX_PROGRAM_CODE_LENGTH);
setup.engine_data.entry_point = entry_point;
u64 code_hash = Common::ComputeHash64(&setup.program_code, sizeof(setup.program_code));
diff --git a/src/video_core/shader/shader_jit_x64_compiler.cpp b/src/video_core/shader/shader_jit_x64_compiler.cpp
index 2dbc8b147..5d9b6448c 100644
--- a/src/video_core/shader/shader_jit_x64_compiler.cpp
+++ b/src/video_core/shader/shader_jit_x64_compiler.cpp
@@ -834,8 +834,8 @@ void JitShader::FindReturnOffsets() {
std::sort(return_offsets.begin(), return_offsets.end());
}
-void JitShader::Compile(const std::array<u32, 1024>* program_code_,
- const std::array<u32, 1024>* swizzle_data_) {
+void JitShader::Compile(const std::array<u32, MAX_PROGRAM_CODE_LENGTH>* program_code_,
+ const std::array<u32, MAX_SWIZZLE_DATA_LENGTH>* swizzle_data_) {
program_code = program_code_;
swizzle_data = swizzle_data_;
diff --git a/src/video_core/shader/shader_jit_x64_compiler.h b/src/video_core/shader/shader_jit_x64_compiler.h
index f27675560..31af0ca48 100644
--- a/src/video_core/shader/shader_jit_x64_compiler.h
+++ b/src/video_core/shader/shader_jit_x64_compiler.h
@@ -22,8 +22,8 @@ namespace Pica {
namespace Shader {
-/// Memory allocated for each compiled shader (64Kb)
-constexpr size_t MAX_SHADER_SIZE = 1024 * 64;
+/// Memory allocated for each compiled shader
+constexpr size_t MAX_SHADER_SIZE = MAX_PROGRAM_CODE_LENGTH * 64;
/**
* This class implements the shader JIT compiler. It recompiles a Pica shader program into x86_64
@@ -37,8 +37,8 @@ public:
program(&setup, &state, instruction_labels[offset].getAddress());
}
- void Compile(const std::array<u32, 1024>* program_code,
- const std::array<u32, 1024>* swizzle_data);
+ void Compile(const std::array<u32, MAX_PROGRAM_CODE_LENGTH>* program_code,
+ const std::array<u32, MAX_SWIZZLE_DATA_LENGTH>* swizzle_data);
void Compile_ADD(Instruction instr);
void Compile_DP3(Instruction instr);
@@ -104,11 +104,11 @@ private:
*/
void FindReturnOffsets();
- const std::array<u32, 1024>* program_code = nullptr;
- const std::array<u32, 1024>* swizzle_data = nullptr;
+ const std::array<u32, MAX_PROGRAM_CODE_LENGTH>* program_code = nullptr;
+ const std::array<u32, MAX_SWIZZLE_DATA_LENGTH>* swizzle_data = nullptr;
/// Mapping of Pica VS instructions to pointers in the emitted code
- std::array<Xbyak::Label, 1024> instruction_labels;
+ std::array<Xbyak::Label, MAX_PROGRAM_CODE_LENGTH> instruction_labels;
/// Offsets in code where a return needs to be inserted
std::vector<unsigned> return_offsets;
diff --git a/src/video_core/swrasterizer/rasterizer.cpp b/src/video_core/swrasterizer/rasterizer.cpp
index 7557fcb89..20addf0bd 100644
--- a/src/video_core/swrasterizer/rasterizer.cpp
+++ b/src/video_core/swrasterizer/rasterizer.cpp
@@ -276,8 +276,10 @@ static void ProcessTriangleInternal(const Vertex& v0, const Vertex& v1, const Ve
DEBUG_ASSERT(0 != texture.config.address);
- float24 u = uv[i].u();
- float24 v = uv[i].v();
+ int coordinate_i =
+ (i == 2 && regs.texturing.main_config.texture2_use_coord1) ? 1 : i;
+ float24 u = uv[coordinate_i].u();
+ float24 v = uv[coordinate_i].v();
// Only unit 0 respects the texturing type (according to 3DBrew)
// TODO: Refactor so cubemaps and shadowmaps can be handled
@@ -403,13 +405,22 @@ static void ProcessTriangleInternal(const Vertex& v0, const Vertex& v1, const Ve
};
auto color_output = ColorCombine(tev_stage.color_op, color_result);
- // alpha combiner
- std::array<u8, 3> alpha_result = {{
- GetAlphaModifier(tev_stage.alpha_modifier1, GetSource(tev_stage.alpha_source1)),
- GetAlphaModifier(tev_stage.alpha_modifier2, GetSource(tev_stage.alpha_source2)),
- GetAlphaModifier(tev_stage.alpha_modifier3, GetSource(tev_stage.alpha_source3)),
- }};
- auto alpha_output = AlphaCombine(tev_stage.alpha_op, alpha_result);
+ u8 alpha_output;
+ if (tev_stage.color_op == TexturingRegs::TevStageConfig::Operation::Dot3_RGBA) {
+ // result of Dot3_RGBA operation is also placed to the alpha component
+ alpha_output = color_output.x;
+ } else {
+ // alpha combiner
+ std::array<u8, 3> alpha_result = {{
+ GetAlphaModifier(tev_stage.alpha_modifier1,
+ GetSource(tev_stage.alpha_source1)),
+ GetAlphaModifier(tev_stage.alpha_modifier2,
+ GetSource(tev_stage.alpha_source2)),
+ GetAlphaModifier(tev_stage.alpha_modifier3,
+ GetSource(tev_stage.alpha_source3)),
+ }};
+ alpha_output = AlphaCombine(tev_stage.alpha_op, alpha_result);
+ }
combiner_output[0] =
std::min((unsigned)255, color_output.r() * tev_stage.GetColorMultiplier());
diff --git a/src/video_core/swrasterizer/texturing.cpp b/src/video_core/swrasterizer/texturing.cpp
index eb18e4ba4..aeb6aeb8c 100644
--- a/src/video_core/swrasterizer/texturing.cpp
+++ b/src/video_core/swrasterizer/texturing.cpp
@@ -169,7 +169,8 @@ Math::Vec3<u8> ColorCombine(TevStageConfig::Operation op, const Math::Vec3<u8> i
result = (result * input[2].Cast<int>()) / 255;
return result.Cast<u8>();
}
- case Operation::Dot3_RGB: {
+ case Operation::Dot3_RGB:
+ case Operation::Dot3_RGBA: {
// Not fully accurate. Worst case scenario seems to yield a +/-3 error. Some HW results
// indicate that the per-component computation can't have a higher precision than 1/256,
// while dot3_rgb((0x80,g0,b0), (0x7F,g1,b1)) and dot3_rgb((0x80,g0,b0), (0x80,g1,b1)) give
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 05:49:22 +0100