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* externals: Update dynarmic to b2a4da5eMerryMage2021-04-111-0/+0
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* arm_dynarmic: Increase size of code cacheMerryMage2021-04-021-0/+0
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* externals: dynarmic: Update to latest rev. to increase code size.bunnei2021-04-011-0/+0
| | | | | - The current limits are being hit in yuzu with some games. - This should fix the slowdowns in newer updates for Super Smash Bros. Ultimate.
* externals: Update dynarmic to c28f13afMerryMage2021-03-271-0/+0
| | | | AVX-512 bugfixes
* external: Update dynarmicLioncash2021-03-081-0/+0
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* externals: Update dynarmic to latestlat9nq2021-02-181-0/+0
| | | | | Updates dynarmic to its latest commit. Includes a fix for argument limits while compiling with Clang 12.
* externals: Dynarmic: Update to latest to include A32 ISB hook.bunnei2021-01-301-0/+0
| | | | - Fixes perf. issues with Megadimension Neptunia VII.
* externals: Update dynarmic to 0f27368fMerryMage2021-01-271-0/+0
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* externals: Update dynarmic to 3806284cbMerryMage2021-01-021-0/+0
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* dynarmic: Add Unsafe_InaccurateNaN optimizationMerryMage2021-01-021-0/+0
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* externals: Update DynarmicReinUsesLisp2020-12-291-0/+0
| | | | | Keeps yuzu up to date with the latest changes and introduces a change needed for a lock-free optimization our side.
* dynarmic: Add unsafe optimizationsMerryMage2020-08-161-0/+0
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* configuration: Add settings to enable/disable specific CPU optimizationsMerryMage2020-07-111-0/+0
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* SVC: Implement 32-bits wrappers and update Dynarmic.Fernando Sahmkow2020-06-271-0/+0
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* ARM: Update Dynarmic and Setup A32 according to latest interface.Fernando Sahmkow2020-06-271-0/+0
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* Externals: Update Dynarmic.Fernando Sahmkow2020-06-271-0/+0
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* ARMInterface/Externals: Update dynarmic and fit to latest version.Fernando Sahmkow2020-06-271-0/+0
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* externals: Update dynarmic to e7166e8bMerryMage2020-04-291-0/+0
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* dynarmic: Add option to disable CPU JIT optimizationsMerryMage2020-04-201-0/+0
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* externals: Update to latest dynarmic.bunnei2020-04-171-0/+0
| | | | - Adds memory alignment fixes.
* core/memory + arm/dynarmic: Use a global offset within our arm page table.Markus Wick2020-01-011-0/+0
| | | | | | This saves us two x64 instructions per load/store instruction. TODO: Clean up our memory code. We can use this optimization here as well.
* externals: Update dynarmic to masterEthan2019-09-211-0/+0
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* externals: Update dynarmic to masterLioncash2019-05-071-0/+0
| | | | Better instruction support has been added since the last update.
* externals: Update dynarmic to 4e6848dMerryMage2018-09-301-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | 4e6848d A32/ir_emitter: Bugfix: ExceptionRaised was producing incorrect PC 41ba9fd value: Move ImmediateToU64() to be a part of Value's interface c6a6271 reg_alloc: Emit AVX instructions where able aedd32a abi: Emit AVX instructions where able f2d9337 a64_exclusive_monitor: Loosen memory ordering requirements 7ca709d travis: Make macOS builds use Xcode 10 14dd45e Fix VShift terminology 88554c4 emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftS16 ab4e316 emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftS64 0ea84f3 emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftS32 c77a2c5 emit_x64_vector: AVX512 implementation of EmitVectorLogicalVShiftU16() e9441fd emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftU64() 0e9c33c emit_x64_vector: AVX2 implementation of EmitVectorLogicalVShiftU32() 8f85274 emit_x64_vector: SSSE3 variant of EmitVectorCountLeadingZeros8() be05e75 Merge pull request #397 from VelocityRa/dec-shift-fix bc328fc decoders: Cast to correctly-sized type before shifting 9c3d2d1 a64_emit_x64: Lowercase PAGE_SIZE f538d29 emit_x64_vector_floating_point: SSE4.1 implementation of EmitFPVectorToFixed 1603a6e emit_x64_vector_floating_point: EmitFPVectorRoundInt: Use FCODE 2e1ccaf emit_x64_vector: AVX implementation for EmitVectorCountLeadingZeros8 555bfda emit_x64_vector: SSE implementation of EmitVectorCountLeadingZeros16 71c2589 externals: Update Xbyak to 5.73 1ec1b2f Squashed 'externals/xbyak/' changes from 1de435ed..42462ef9
* externals: Update dynarmic to 171d116MerryMage2018-09-191-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 171d116 A64: Implement SCVTF, UCVTF (vector, fixed-point), scalar variant f221bb0 emit_x64_floating_point: Reduce fallback LUT code in EmitFPToFixed eb123e2 A64: Implement FCVTZS, FCVTZU, UCVTF, SCVTF (vector, fixed-point), vector variant 487d37a A64: Implement UQSHL's vector immediate and register variants f698933 ir: Add opcodes for unsigned saturating left shifts 7148e66 A64/translate/impl: Make signatures consistent for unimplemented by-element SIMD variants fdde4ca A64: Implement BRK b1490db A64/imm: Add full range of comparison operators to Imm template 1ec40ef IR: Add fbits argument to FPVectorFrom{Signed,Unsigned}Fixed d6d5e98 A64: Implement SCVTF, UCVTF (scalar, fixed-point) 6513595 opcodes.inc: Align columns to a tabstop of 4 6b0d2b5 IR: Add fbits argument to FixedToFP-related opcodes c4b3831 A64: Implement SQSHL's vector immediate variant e0d8d2d A64: Implement SQSHL's vector register variant 5327625 ir: Add opcodes for left signed saturated shifts 9705252 branch: Make variables const where applicable 650946e move_wide: Make variables const where applicable 62b3a6d load_store_register_unprivileged: Make variables const where applicable 3add1c7 load_store_register_immediate: Place conditional bodies on their own line 2fc4088 load_store_load_literal: Make variables const where applicable b2c1462 data_processing_logical: Move datasize declarations after early-exit conditionals 028028f data_processing_conditional_select: Make variables const where applicable c66042d data_processing_addsub: Move datasize declarations after early-exit conditionals 6bc546e data_processing_bitfield: Move datasize variables after early-exit conditionals 2aad5fa A64: Implement CLS's vector variant 6c877ff emit_x64_vector: Make EmitVectorUnsignedSaturatedAccumulateSigned() internally linked 4b5926d perf_map: Use std::string_view instead of std::string for PerfMapRegister() 7445947 A64: Implement SQRDMULH (vector), vector variant 03b80f2 A64: Implement SQDMULL (vector), vector variant 4a2c596 IR: Add VectorSignedSaturatedDoublingMultiplyLong 59dc33e emit_x64_vector: Changes to VectorSignedSaturatedDoublingMultiply bbaebeb IR: Implement Vector{Signed,Unsigned}Multiply{16,32} baac5a8 backend_x64/a64_interface: Re-enable the constant folding pass e78ca19 emit_x64_vector_floating_point: Hardware FMA implementation for RSqrtStepFused 8a5ae9a emit_x64_vector_floating_point: Hardware FMA implementation of FPVectorRecipStepFused 39818f9 emit_x64_floating_point: Hardware FMA implementation of FPRSqrtStepFused 3d0a0b4 emit_x64_floating_point: Hardware FMA implementation of FPRecipStepFused{32,64} 2293dff emit_x64_vector: SSE implementation of VectorSignedSaturatedAccumulateUnsigned{8,16,32} 2047683 emit_x64_vector: Correct static asserts for < 64-bit type checks in saturated accumulate fallbacks 55e9e40 emit_x64_vector: EmitVectorSignedSaturatedAccumulateUnsigned64: SSE implementation 1076651 emit_x64_vector: Simplify fpsr_qc related code 4039030 A64: Implement CLZ's vector variant 0bb908f ir: Add opcodes for vector CLZ operations 3b13259 A64/translate: VectorZeroUpper for V(64) stores 1931d44 simd_two_register_misc: FNEG (vector) with Q == 0 had dirty upper a0790f0 emit_x64_vector: Remove unnecessary [[maybe_unused]] attributes b0e1eb5 A64: Implement USQADD's scalar and vector variants 28424c7 ir: Add opcodes form unsigned saturated accumulations of signed values 9923ea0 A64: Implement SUQADD's scalar and vector variants 4c0adbb ir: Add opcodes for signed saturated accumulations of unsigned values 799bfed A64: Implement SMLAL{2}, SMLSL{2}, UMLAL{2}, and UMLSL{2}'s vector by-element variants 94451ec A64: Implement UMULL{2}'s vector by-element variant 45867de A64: Implement SMULL{2}'s vector by-element variant 0235793 ir/value: Replace includes with forward declarations 450f721 ir/cond: Migrate to C++17 nested namespace specifiers e649988 CMakeLists: Add missing cond.h header to file listing d20e769 A64: Implement URSQRTE 4f3bde5 ir: Add opcodes for performing unsigned reciprocal square root estimates cfeeaec A64: Implement URECPE 622b60e ir: Add opcodes for unsigned reciprocal estimate d17599a Update Xbyak to 5.71 f7c26e9 Squashed 'externals/xbyak/' changes from 671fc805..1de435ed 8782b69 travis: Make macOS build with Xcode 9.4.1 b575b23 A64: Implement SQNEG's scalar and vector variant 06062a9 A64: Add opcodes for signed saturating negations 1c40579 emit_x64_vector: Simplify "position == 0" case for EmitVectorExtract() e335050 emit_x64_vector: Simplify "position == 0" case for EmitVectorExtractLower() 8b13421 A64: Implement SQDMULH's by-element scalar variant 9122a6e A64: Implement SQDMULH's by-element vector variant 176e60e backend/x64: Do not clear fast_dispatch_table if not enabled
* externals: Update dynarmic to 9594465MerryMage2018-09-071-0/+0
| | | | | | | | | | | | | | | | | | | 9594465 A64: Implement FastDispatchHint 2be95f2 A32: Implement FastDispatchHint 96f23ac ir/terminal: Add FastDispatchHint f5ca9e9 A64: Implement SQDMULH's scalar variant af8bea5 ir: Add opcodes for scalar signed saturated doubling multiplies fed4220 A64: Implement SQDMULH's vector variant 72eb6ad ir: Add opcodes for signed saturated doubling multiplies 0f8ae84 externals: Update catch to 2.4.0 235165b A64: Implement SQABS' scalar variant 1adca93 A64: Implement SQABS' vector variant. f978c44 ir: Add opcodes for signed saturated absolute values d895a84 emit_x64_floating_point: EmitFPToFixed: maxsd optimization c624fe3 emit_x64_floating_point: ZeroIfNaN: pxor -> xorps e987a84 IR: Simplify FP{Single,Double}ToFixed{U,S}{32,64} f1babc8 externals: Update catch to 2.3.0 a0c587a A32/decoder: Add missing <algorithm> includes
* externals: Update dynarmic to 0435ac2Lioncash2018-09-031-0/+0
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* externals: Update dynarmic to a42f301c.bunnei2018-08-211-0/+0
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* dynarmic: Update to 550d662MerryMage2018-08-161-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | 550d662 load_store_exclusive: Define s == t state to be Constraint_NONE 0b69381 A64/translate: Allow for unpredictable behaviour to be defined 6d236d4 system: Implement MRS CNTFRQ_EL0 6cbb6fb A32/testenv: Add missing headers 6729328 externals: Update xbyak to v5.67 1812bd2 Squashed 'externals/xbyak/' changes from 2794cde7..671fc805 9a95802 externals: Document subtrees 714a840 A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants 8cab459 A64: Implement UQADD/UQSUB's scalar variants 18a8151 ir: Add opcodes for unsigned saturating add and subtract a5660ee x64/reg_alloc: Use type alias for array returned by GetArgumentInfo() 29489b5 ir/value: Use type alias CoprocessorInfo for std::array<u8, 8> e23ba26 status_register_access: Add support for bits 0 and 1 of mask to MSR 55190bd fuzz_with_unicorn: Split utility functions into fuzz_util 23b049d A32/translate/load_store: Correct detection of writeback 7ec9f15 A32/translate: Add TranslateSingleInstruction efeecb4 A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode 08d1d19 A32/decoders: Split instruction list into include file 2d929cc tests: Refactor unicorn_emu to allow for A32 unicorn f672368 microinstruction: Improve assert messages 7ebff50 emit_x64_vector: EmitVectorNarrow16: AVX512 implementation edce230 emit_x64_vector: EmitVectorNarrow32: prefer pblendw to loading constant
* dynarmic: Update to 0118ee0MerryMage2018-08-101-0/+0
| | | | 0118ee0 emit_x64_vector: packusdw is SSE4.1
* externals: Update dynarmic to 4f96c63MerryMage2018-08-051-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4f96c63 emit_x64_vector_floating_point: Simplify FPVector{Min,Max} e15fdfe emit_x64_vector_floating_point: Simplify Get*Vector functions 734a00b emit_x64_floating_point: Remove EmitProcessNaNs fd45191 devirtualize: Replace DEVIRT macro with function template 67ba5d0 fuzz_with_unicorn: Remove FCVT_float from ignore list 66e6dd1 a32_emit_x64: std::move A32::UserConfig in the constructor b4890b6 emit_x64_floating_point: Use EmitPostProcessNaNs in EmitFPMulX 18b2943 emit_x64_floating_point: Remove unnecessary DenormalsAreZero from EmitFPSingleToDouble and EmitFPDoubleToSingle df1f81f emit_x64_floating_point: Simplify EmitFP{Min,Max}{,Numeric}{32,64} 21fb1c3 emit_x64_floating_point: Reduce NaN processing overhead f5c9f0f A64: Implement FMULX, scalar single/double variant 8f47773 IR: Implement FPMulX IR instruction 79e6440 fuzz_with_unicorn: Randomize SP 33c80e3 fuzz_with_unicorn: Randomize PC 8d41024 testenv: Make code_mem mobile a9fae0e emit_x64_vector: Vectorize 32-bit variants of paired min/max 8926a92 emit_x64_vector: Improve code emission of VectorGetElement* for index == 0 e20bd38 reg_alloc: Do a UseScratch if a Use destination is too small a19fa0e fuzz_with_unicorn: Randomize FPCR.AHP and FPCR.FZ16 775f368 emit_x64_floating_point: AVX implementation of ForceToDefaultNaN 71018a1 emit_x64_vector_floating_point: Prefer blendvp{s,d} to vblendvp{s,d} where possible 137f4b3 backend_x64: Remove all use of xmm0 e73d67a emit_x64_vector_floating_point: AVX implementation of ForceToDefaultNaN 43cca54 emit_x64_vector_floating_point: Reduce codesize of ForceToDefaultNaN 5dc40f4 emit_x64_vector_floating_point: Reduce codesize of EmitTwoOpVectorOperation 07622ee emit_x64_vector_floating_point: Correct FMA in FTZ mode 621c85b emit_x64_floating_point: DenormalsAreZero is redundant as hardware already does DAZ 3d0ebaa emit_x64_floating_point: FlushToZero is redundant as hardware already does FTZ f626ff8 backend_x64: Fix FPVectorMulAdd and FPMulAdd NaN handling with denormals adeb9d9 a32/fuzz_arm: Disable vfp tests 19ea70d fuzz_with_unicorn: Randomize FPCR.FZ 895db36 backend_x64: Fix bugs when FPCR.FZ=1 d7e2de2 fuzz_with_unicorn: Extract RandomFpcr function c858d6c fp/info: Deduplicate functions 5b88ec2 emit_x64_floating_point: Deduplicate EmitFPMulAdd implementation
* externals: Update dynarmic to 73d3efcMerryMage2018-07-301-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 73d3efc emit_x64_floating_point: Deduplicate code c9508c3 fuzz_with_unicorn: Randomize FPCR.DN 2970833 emit_x64_vector_floating_point: Fix FPVector{Max,Min} when FPCR.DN = 1 150764f emit_x64_floating_point: Fix FP{Max,Min} when FPCR.DN = 1 b7d209c IR: SSE4.1 implementation of FPVectorRoundInt 8cf8270 A64: Implement FRINT{N,M,P,Z,A,X,I} (vector), single/double variant 8f46c26 IR: Initial implementation of FPVectorRoundInt 97017bb A64: Implement SQADD and SQSUB, scalar variant ce58863 IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths e80f8ff a64_emit_x64: Bugfix EmitA64OrQC - Incorrect argument 1e4ec7e simd_three_same: Extract non-paired SMAX, SMIN, UMAX, UMIN code to a common function 6f9dc9b A64: Implement SMAXP, SMINP, UMAXP, UMINP 1dfb29f ir: Add opcodes for vector paired maximum and minimums 017b510 A64: Implement SMAXV, SMINV, UMAXV, and UMINV aae22ee ir: Add opcodes for performing scalar integral min/max 6ef3af3 A64: Implement PMULL{2} 2a4ce19 translate: Deduplicate GetDataSize() functions 0e01500 floating_point_{conditional}_compare: Deduplicate code 259237c common: Move all cryptographic function to common/crypto c5f1080 a32_emit_x64: BMI2 implementation of A32SetCpsr a23304a a32_emit_x64: Shorten EmitA32GetCpsr 57604d2 a32_emit_x64: Assert that memory layout assumption in EmitA32GetCpsr is valid 945fa48 A64: Implement PMUL 656a404 ir: Add opcode for performing polynomial multiplication 05143df A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant 34ce767 A64: Implement FCVTZS (vector, integer), single/double variant 0f9bc2d IR: Implement FPVectorTo{Signed,Unsigned}Fixed 0189e44 fp/info: Replace constant value generators with FPValue db16568 emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min} 31148bd emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs 4c3ca51 A64: Implement FMAX's vector single and double precision variants bf0f21c A64: Implement FMIN's vector single and double precision variants 76f0ca0 IR: Implement FPVector{Max,Min} 6c37c31 FPRecipEstimate: Move offset out of function 59546f3 microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits 3f6b03a A64: Implement FRECPS, vector/scalar single/double variants 2d2ca5e IR: Implement FPRecipStepFused, FPVectorRecipStepFused 5cb9f1d A64: Implement FRECPE, vector single/double variant c5a14ab IR: Implement FPVectorRecipEstimate 56f8a0b A64: Implement FRECPE, scalar single/double variant fde69b4 IR: Implement FPRecipEstimate 186e52c IR: Implement FPRecipEstimate cf2e1ae fp: Change FPUnpacked to a normalized representation
* externals: Update dynarmic to 98e2380MerryMage2018-07-251-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 98e2380 fuzz_with_unicorn: Disable testing of FDIV 041b7d5 block_of_code: Add ABI_PARAMS array 2a2371c A64: Implement MLA, MLS (by element), vector single/double variant 78c640a A64: Implement FMLS (vector), single/double variant b6b6993 emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly 4b9d12a emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused b1e3616 IR: Implement FPVectorNeg 4343612 A64: Implement FMLA (vector), single/double variant 93eeb25 IR: Implement FPVectorMulAdd 57e5c7e emit_x64_vector_floating_point: Standardize naming scheme bcb9e41 emit_x64_floating_point: Simplify indexers 83aa585 emit_x64_vector_floating_point: Simplify EmitVectorOperation* f4087c8 mp: rename mp.h to mp/function_info.h 1864090 emit_x64_vector: Slightly improve ArithmeticShiftRightByte e048441 emit_x64_vector: Simplify VectorShuffleImpl ff025e8 IR: Implement A64OrQC 6fac68d A64: Implement UQSHRN, UQRSHRN (vector) 5a8d9c3 emit_x64_vector: -0x80000000 isn't -0x80000000 759289e A64: Implement UQXTN (vector) 2a96281 emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison 0682353 A64: Implement SQXTN (vector) 6c5229e emit_x64_vector: packusdw reqiures SSE4.1 158d9b1 A64: Implement SQSHRUN, SQRSHRUN (vector) f886013 simd_shift_by_immediate: Simplify ShiftRight d9b59c6 A64: Implement SQXTUN 50fe28b microinstruction: Reorganize FPSCR related instruction queries d9d036a microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR() db96163 u128: Make Bit() a const-qualified member function f7052ae A64: Implement FRSQRTS (vector), single/double variant 0925ef6 A64: Implement FRSQRTE (vector), single/double variant f4cbbe3 A64: Implement FRSQRTS (scalar), single/double variant 4ef864e IR: Implement FPRSqrtStepFused 9dffeeb fp: Implement FPRSqrtStepFused aa04556 fp: Implement FPNeg cbde1c5 process_nan: Add two operand variant 1ec2663 A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant 027ddf9 emit_x64_floating_point: Fixup special NaN case in FMA FPMulAdd implementation 75a9f77 fp: Use a forward declaration in fused.h 1ee1630 u128: Implement comparison operators in terms of one another 3b77f48 tests: Print cpu info bed3cc0 u128: StickyLogicalShiftRight requires special-casing for amount == 64 15d04f4 A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant 7cfccdf A64: Implement FMUL (by element)'s scalar double/single-precision variant 7d2d62e (fpmuladd) emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64} a599eac fp: Implement FPMulAdd d70b90e process_nan: Add FPProcessNaNs3 38ef0e0 block_of_code: Add SysV ABI fifth and sixth parameters 8e2ff56 u128: Add StickyLogicalShiftRight 3b337df u128: Add Multiply64To128 8219075 u128: Add u128::Bit a574dcb u128: Add comparison operators 391d6d4 unpacked: Use ResidualErrorOnRightShift in FPRoundBase 5e0cf9c fp: Remove MantissaT 8c0a84c FPRSqrtEstimate: Improve documentation of RecipSqrtEstimate c41d855 FPRSqrtEstimate: Deduplicate array bounds 4cf055b A64: Implement FMAXV, FMINV, FMAXNMV, and FMINNMV bf24f0f FPRSqrtEstimate: Use forward declarations where applicable 206230e translate: Return by bool in helpers where applicable 346b725 Simplify fallback case for EmitVectorSetElement64() 2c34e1d emit_x64_floating_point: s/Esimate/Estimate/ 5213fb6 simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant 7ed089f IR: Implement FPRSqrtEstimate cd2e286 simd_vector_x_indexed_element: Implement FMUL (by element), vector variant
* externals: Update dynarmic to fc6b73bdMerryMage2018-07-221-0/+0
| | | | | | | | | | | | | | Resolves issues: * 128-bit exclusive writes on Windows * Non-updating CNTPCT_EL0 fc6b73 a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT 888c67 a64_emit_x64: Fix stack misalignment on Windows for 128-bit exclusive writes 352d53 emit_x64_aes: Eliminate extraneous usage of a scratch register in EmitAESInverseMixColumns() ab7fe7 A64: Implement SADDLV 09bd2b A64: Implement UADDLV 62e86d fp: Use forward declarations where applicable b3edb7 emit_x64_vector: Append 'v' prefix onto movq in AVX path
* externals: Update dynarmic to 7ea1241Lioncash2018-07-211-0/+0
| | | | | Resolves an issue with TPIDR setting being erroneously removed in the dead code pass.
* externals: Update dynarmic to 5a91c94.bunnei2018-07-191-0/+0
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* externals: Update dynarmic to dfdec79Lioncash2018-07-151-0/+0
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* externals: Update dynarmic to f7d11baa1Lioncash2018-07-071-0/+0
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* externals: Update dynarmicLioncash2018-05-231-0/+0
| | | | Updates dynarmic to revision 990a569b7a5f2518fe08682f5ebf8536e5388d66
* externals: Update dynarmicLioncash2018-04-281-0/+0
| | | | Just a basic update to keep it in sync
* externals: Update dynarmic to HEADLioncash2018-04-201-0/+0
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* dynarmic: Update to 9cc12d8MerryMage2018-03-291-0/+0
| | | | | | 9cc12d8 abi: Missing includes ac35ad5 emit_x64_floating_point: Near jump instead of short jump in FPMinNumberic{32,64} 6f03fdd A64: system: Use an enum class for MRS/MSR register encodings
* dynarmic: Update to 12a1020MerryMage2018-03-271-0/+0
| | | | | | | | | | | | | | | 12a1020 emit_X64_floating_point: Near jmp to end instead of short jmp 6278f83 emit_x64_vector: Fix typo in VectorShuffleImpl 25a0204 A64: Implement REV64 aa92e33 bit_util: Do nothing in RotateRight if the rotation amount is zero e537985 A64: Implement REV32 (vector) f62a258 ir: Add IR opcodes for emitting vector shuffles 36ac6ec emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64 20a59a9 A64: Implement REV16 (vector) b2f7bb0 CMakeLists: Add fp_util, macro_util and math_util headers fd21b58 A64: Implement EOR3 and BCAX a48c0bb travis: Use yuzu's unicorn fork 59e62e0 externals: Update catch to v2.2.1
* dynarmic: Update to 6b4c6b0MerryMage2018-02-211-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 6b4c6b0 impl: Update PC when raising exception 7a1313a A64: Implement FDIV (vector) b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL b277bf5 Correct FPSR and FPCR 7673933 A64: Implement USHL 8d0e558 A64: Implement UCVTF (vector, integer), scalar variant da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 7479684 A64: Implement system register TPIDR_EL0 0fd75fd A64: Implement system registers FPCR and FPSR 31e370c A64: Implement system register CNTPCT_EL0 9a88fd3 A64: Implement system register CTR_EL0 1d16896 A64: Implement NEG (vector) 3184edf IR: Add IR instruction ZeroVector 31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter 567eb1a A64: Implement FMINNM (scalar) c6d8fa1 A64: Implement FMAXNM (scalar) 616056d constant_pool: Add frame parameter a3747cb A64: Implement ADDP (scalar) 5cd5d9f reg_alloc: Only exchange GPRs dd0452a A64: Implement DUP (element), scalar variant e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar) 7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect 826dce2 travis: Switch unicorn repository 9605f28 a64/config: Allow NaN emulation accuracy to be set e9435bc a64_emit_x64: Add conf to A64EmitContext 30b596d fuzz_with_unicorn: Explicitly test floating point instructions be292a8 A64: Implement FSQRT (scalar) 3c42d48 backend_x64: Accurately handle NaNs 4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
* updated dynarmicFernandoS272018-02-171-0/+0
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* arm_dynarmic: Support direct page table accessMerryMage2018-02-121-0/+0
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* dynarmic: Fix bug due to Windows ABI mismatchMerryMage2018-02-091-0/+0
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* dynarmic: Update to 41ae12263MerryMage2018-02-091-0/+0
| | | | Changes: Primarily implementing more A64 instructions
* externals: Update dynarmicMerryMage2018-01-211-0/+0
| | | | | | | | | | | | | | | | | | | | | | | a6d17e A64: Implement AND (vector) 963453 tests/A64: Randomize vectors adcd34 tests/A64/unicorn: Print interrupt number when InterruptHook is hit 304c91 tests/A64: Allow RunTestInstance to start from an arbitrary offset d333b5 A64: Implement ADD (vector, vector) 1cf87a A64: Implement REV, REV32, and REV16 (#126) 9fc157 IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 50c181 reg_alloc: GetBitWidth: Add UNREACHABLE adccbf reg_alloc: Consider bitwidth of data and registers when emitting instructions 7b7f23 A64: Implement CSEL 2f8413 IR: Implement Conditional Select ebb3e8 A64/tests: Split unicorn sanity checking from other tests 5740a0 tests/A64: Single random instruction: Test branch instructions as well 0892b4 A64/translate/branch: bug: Read-after-write error in BLR e77bc2 A64: Implement SBFM, BFM, UBFM 0c37ca A64: Implement MOVN, MOVZ, MOVK b6bb59 travis: Print current test information e77207 fuzz_thumb: Off by one error a04ca2 ir/location_descriptor: Add missing <functional> header for std::hash 1e0f5c travis: Run A64 tests
* Update dynarmic to bc73004MerryMage2018-01-131-0/+0
| | | | | | | | | | | | | | | | | | bc73004 a64_merge_interpret_blocks: Remove debug output 4e656ed tests/A64: Randomize PSTATE.<NZCV> fd9530b A64: Optimization: Merge interpret blocks 3c9eb04 testenv: Use format constants 324f3fc tests/A64: Unicorn interface fixes 98ecbe7 tests/A64: Fuzz against unicorn b1d38e7 tests/A64: Move TestEnvironment to own header 5218ad9 A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate b1a8c39 A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31 64827fb a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers 1bfa04d emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 edadeea A64 inferface: Use two argument static_assert 9ab1304 A64: Add ExceptionRaised IR instruction 6843eed Update readme 7438d07 A64/translate: Add TranslateSingleInstruction function
* dynarmic: Update to 83afe435MerryMage2018-01-121-0/+0
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* arm_dynarmic: Implement coreMerryMage2018-01-121-0/+0
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* externals: Point dynarmic at a real commit.bunnei2018-01-041-0/+0
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* externals: Update dynarmic and xbyak.bunnei2017-10-251-0/+0
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* Merge remote-tracking branch 'upstream/master' into nxbunnei2017-10-101-0/+0
| | | | | | | | | | | | | | | | | # Conflicts: # src/core/CMakeLists.txt # src/core/arm/dynarmic/arm_dynarmic.cpp # src/core/arm/dyncom/arm_dyncom.cpp # src/core/hle/kernel/process.cpp # src/core/hle/kernel/thread.cpp # src/core/hle/kernel/thread.h # src/core/hle/kernel/vm_manager.cpp # src/core/loader/3dsx.cpp # src/core/loader/elf.cpp # src/core/loader/ncch.cpp # src/core/memory.cpp # src/core/memory.h # src/core/memory_setup.h
* Stop using reserved operator names (and/or/xor) with XbyakYuri Kunde Schlesner2017-06-171-0/+0
| | | | Also has the Dynarmic upgrade with the same change
* Update dynarmicYuri Kunde Schlesner2017-05-271-0/+0
| | | | | Updated to incorporate fix from MerryMage/dynarmic#106 which is required for using fmt in Citra.
* dynarmic: Update the submodule.Emmanuel Gil Peyrot2017-02-181-0/+0
| | | | | | This fixes a build issue on gcc 6 due to -Werror and a warning caused by boost::optional, see: https://github.com/MerryMage/dynarmic/issues/83
* arm_dynarmic: Update memory interfaceMerryMage2017-02-031-0/+0
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* arm_dynarmic: CP15 supportMerryMage2017-02-031-0/+0
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* arm_dynarmic: Provide MemoryReadCode callbackMerryMage2016-12-221-0/+0
| | | | Change of interface in dynarmic 36082087ded632079b16d24137fdd0c450ce82ea
* externals: Update DynarmicYuri Kunde Schlesner2016-12-151-0/+0
| | | | Required to be able to use Xbyak in Citra without header conflicts.
* Dynarmic: Update dynarmic to versionSubv2016-12-051-0/+0
| | | | | | | | | | | | | | | | | | | | | | | 54d051977f7a6af9c7596ba6a4e6eb467bd1e0bc dynarmic log: 54d0519 emit_x64: Use movdqa instead of movaps in EmitPackedSubU8 52e1445 Implement USUB8:33 2016 +0000 5c1aab1 Implement CLZ 1a1646d Implement UADD8 7cad694 IR: Implement new pseudo-operation GetGEFromOp 370f654 fuzz_arm: Add tests for parallel add/subtract (modulo) 25f21b5 emit_x64: Inline nzcv computation into EmitFPCompare32 and EmitFPCompare64 52fdec5 CMakeLists: Add support for LLVM on Windows cede5e4 emit_x64: Use xorps/xorpd when argument to TransferToFP32/TransferToFP64 is an immediate zero e166965 Implement VCMP2:33 2016 +0000 f2fe376 Support 64-bit immediates ff00b8c Document register allocator and return stack buffer optimization 95f34c6 reg_alloc: Remove unnecessary breaks after returns (#54) dc9707e externals: Update xbyak to 5.32 de1f831 microinstruction: Make use_count private (#53) 3621a92 reg_alloc: Register allocator related constraints belong with the rest of the register allocator
* dynarmic: Fix ABI violationMerryMage2016-11-301-0/+0
| | | | | | | Caused by not saving/restoring the x64 r15 register on entry/exit from JITted code. Closes #2224.
* Update dynarmic to the latest version (#2234)James Rowe2016-11-301-0/+0
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* dynarmic: Add new submodule.bunnei2016-09-151-0/+0
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