From 2d6c064e66bac4cb871aa26a12066441a8852008 Mon Sep 17 00:00:00 2001 From: ReinUsesLisp Date: Thu, 27 Dec 2018 16:50:36 -0300 Subject: shader_decode: Improve zero flag implementation --- src/video_core/shader/shader_ir.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src/video_core/shader/shader_ir.h') diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h index 0c8f4a265..47f460bcf 100644 --- a/src/video_core/shader/shader_ir.h +++ b/src/video_core/shader/shader_ir.h @@ -649,6 +649,11 @@ private: /// Sets a temporal. Internally it uses a post-RZ register void SetTemporal(BasicBlock& bb, u32 id, Node value); + /// Sets internal flags from a float + void SetInternalFlagsFromFloat(BasicBlock& bb, Node value, bool sets_cc = true); + /// Sets internal flags from an integer + void SetInternalFlagsFromInteger(BasicBlock& bb, Node value, bool sets_cc = true); + /// Conditionally absolute/negated float. Absolute is applied first Node GetOperandAbsNegFloat(Node value, bool absolute, bool negate); /// Conditionally saturates a float @@ -725,9 +730,9 @@ private: void WriteLogicOperation(BasicBlock& bb, Tegra::Shader::Register dest, Tegra::Shader::LogicOperation logic_op, Node op_a, Node op_b, Tegra::Shader::PredicateResultMode predicate_mode, - Tegra::Shader::Pred predicate); + Tegra::Shader::Pred predicate, bool sets_cc); void WriteLop3Instruction(BasicBlock& bb, Tegra::Shader::Register dest, Node op_a, Node op_b, - Node op_c, Node imm_lut); + Node op_c, Node imm_lut, bool sets_cc); template Node Operation(OperationCode code, const T*... operands) { -- cgit v1.2.3