From d03fc774756306aa8fd89abd5522c928b46336c7 Mon Sep 17 00:00:00 2001 From: Subv Date: Fri, 20 Apr 2018 09:04:54 -0500 Subject: ShaderGen: Register id 255 is special and is hardcoded to return 0 (SR_ZERO). --- src/video_core/engines/shader_bytecode.h | 3 +++ src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 2 ++ 2 files changed, 5 insertions(+) (limited to 'src') diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 7cd125f05..b0da805db 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -13,6 +13,9 @@ namespace Tegra { namespace Shader { struct Register { + // Register 255 is special cased to always be 0 + static constexpr size_t ZeroIndex = 255; + constexpr Register() = default; constexpr Register(u64 value) : value(value) {} diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index c23f590cd..6db0b7d39 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp @@ -220,6 +220,8 @@ private: /// Generates code representing a temporary (GPR) register. std::string GetRegister(const Register& reg, unsigned elem = 0) { + if (reg == Register::ZeroIndex) + return "0"; if (stage == Maxwell3D::Regs::ShaderStage::Fragment && reg < 4) { // GPRs 0-3 are output color for the fragment shader return std::string{"color."} + "rgba"[(reg + elem) & 3]; -- cgit v1.2.3