21 files changed, 5069 insertions, 0 deletions

diff --git a/private/ntos/ndis/aic5900/aic5900.h b/private/ntos/ndis/aic5900/aic5900.h
new file mode 100644
index 000000000..3df4dee4d
--- /dev/null
+++ b/private/ntos/ndis/aic5900/aic5900.h
@@ -0,0 +1,65 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\aic5900.h
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#ifndef	__AIC5900_H
+#define __AIC5900_H
+
+#include "ndis.h"
+#include "atm.h"
+
+#if BINARY_COMPATIBLE
+#include <pci.h>
+#endif
+
+#include "eeprom.h"
+#include "hw.h"
+#include "sw.h"
+#include "sar.h"
+#include "protos.h"
+#include "debug.h"
+#include <memmgr.h>
+
+//
+//	Module identifiers.
+//	
+#define	MODULE_DEBUG		0x00010000
+#define	MODULE_INIT			0x00020000
+#define	MODULE_INT			0x00030000
+#define	MODULE_RECEIVE		0x00040000
+#define	MODULE_REQUEST		0x00050000
+#define	MODULE_RESET		0x00060000
+#define	MODULE_SEND			0x00070000
+#define MODULE_VC			0x00080000
+#define MODULE_SUPPORT		0x00090000
+#define	MODULE_DATA			0x000a0000
+
+
+//
+//	Extern definitions for global data.
+//
+
+extern	NDIS_HANDLE	gWrapperHandle;
+extern	NDIS_STRING	gaRegistryParameterString[];
+
+
+#endif // __AIC5900_H
diff --git a/private/ntos/ndis/aic5900/aic5900.rc b/private/ntos/ndis/aic5900/aic5900.rc
new file mode 100644
index 000000000..5b4a29625
--- /dev/null
+++ b/private/ntos/ndis/aic5900/aic5900.rc
@@ -0,0 +1,39 @@
+#include <windows.h>
+#include <ntverp.h>
+
+/*-----------------------------------------------*/
+/* the following lines are specific to this file */
+/*-----------------------------------------------*/
+
+/* VER_FILETYPE, VER_FILESUBTYPE, VER_FILEDESCRIPTION_STR
+ * and VER_INTERNALNAME_STR must be defined before including COMMON.VER
+ * The strings don't need a '\0', since common.ver has them.
+ */
+#define	VER_FILETYPE	VFT_DRV
+/* possible values:		VFT_UNKNOWN
+				VFT_APP
+				VFT_DLL
+				VFT_DRV
+				VFT_FONT
+				VFT_VXD
+				VFT__LIB
+*/
+#define	VER_FILESUBTYPE	VFT2_DRV_NETWORK
+/* possible values		VFT2_UNKNOWN
+				VFT2_DRV_PRINTER
+				VFT2_DRV_KEYBOARD
+				VFT2_DRV_LANGUAGE
+				VFT2_DRV_DISPLAY
+				VFT2_DRV_MOUSE
+				VFT2_DRV_NETWORK
+				VFT2_DRV_SYSTEM
+				VFT2_DRV_INSTALLABLE
+				VFT2_DRV_SOUND
+				VFT2_DRV_COMM
+*/
+#define VER_FILEDESCRIPTION_STR     "Microsoft Corp. DEC ATM Driver"
+#define VER_INTERNALNAME_STR        "OTTO.SYS"
+#define VER_ORIGINALFILENAME_STR    "OTTO.SYS"
+
+#include "common.ver"
+
diff --git a/private/ntos/ndis/aic5900/data.c b/private/ntos/ndis/aic5900/data.c
new file mode 100644
index 000000000..91eb3cd94
--- /dev/null
+++ b/private/ntos/ndis/aic5900/data.c
@@ -0,0 +1,38 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\data.c
+
+Abstract:
+
+	This file contains global definitions.
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#include "aic5900.h"
+
+#define	MODULE_NUMBER	MODULE_DATA
+
+NDIS_HANDLE		gWrapperHandle = NULL;
+NDIS_STRING		gaRegistryParameterString[Aic5900MaxRegistryEntry] =
+{
+	NDIS_STRING_CONST("BusNumber"),
+	NDIS_STRING_CONST("SlotNumber"),
+	NDIS_STRING_CONST("VcHashTableSize")
+};
+
+
diff --git a/private/ntos/ndis/aic5900/debug.c b/private/ntos/ndis/aic5900/debug.c
new file mode 100644
index 000000000..897d67e91
--- /dev/null
+++ b/private/ntos/ndis/aic5900/debug.c
@@ -0,0 +1,221 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\debug.c
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#include "aic5900.h"
+
+//
+//  Define module number for debug code
+//
+#define MODULE_NUMBER	MODULE_DEBUG
+
+
+#if DBG
+
+ULONG	gAic5900DebugSystems = DBG_COMP_ALL;
+LONG	gAic5900DebugLevel = DBG_LEVEL_INFO;
+ULONG	gAic5900DebugInformationOffset;
+
+VOID
+dbgInitializeDebugInformation(
+	IN	PADAPTER_BLOCK	pAdapter
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+
+}
+
+
+VOID
+dbgDumpHardwareInformation(
+	IN	PHARDWARE_INFO	HwInfo
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	if ((DBG_LEVEL_INFO >= gAic5900DebugLevel) &&
+		((gAic5900DebugSystems & DBG_COMP_INIT) == DBG_COMP_INIT))
+	{
+		DbgPrint("FCodeImage: 0x%x\n", HwInfo->FCodeImage);
+		DbgPrint("NicModelNumber: 0x%x\n", HwInfo->NicModelNumber);
+		DbgPrint("RomVersionNumber: 0x%x\n", HwInfo->RomVersionNumber);
+
+		DbgPrint("rEpromOffset: 0x%x\n", HwInfo->rEpromOffset);
+		DbgPrint("rEpromSize: 0x%x\n", HwInfo->rEpromSize);
+		DbgPrint("rEprom: 0x%x\n", HwInfo->rEprom);
+
+		DbgPrint("rwEpromOffset: 0x%x\n", HwInfo->rwEpromOffset);
+		DbgPrint("rwEpromSize: 0x%x\n", HwInfo->rwEpromSize);
+		DbgPrint("rwEprom: 0x%x\n", HwInfo->rwEprom);
+
+		DbgPrint("PhyOffset: 0x%x\n", HwInfo->PhyOffset);
+		DbgPrint("PhySize: 0x%x\n", HwInfo->PhySize);
+		DbgPrint("Phy: 0x%x\n", HwInfo->Phy);
+
+		DbgPrint("ExternalOffset: 0x%x\n", HwInfo->ExternalOffset);
+		DbgPrint("ExternalSize: 0x%x\n", HwInfo->ExternalSize);
+		DbgPrint("External: 0x%x\n", HwInfo->External);
+
+		DbgPrint("MidwayOffset: 0x%x\n", HwInfo->MidwayOffset);
+		DbgPrint("MidwaySize: 0x%x\n", HwInfo->MidwaySize);
+		DbgPrint("Midway: 0x%x\n", HwInfo->Midway);
+
+		DbgPrint("PciCfgOffset: 0x%x\n", HwInfo->PciCfgOffset);
+		DbgPrint("PciCfgSize: 0x%x\n", HwInfo->PciCfgSize);
+		DbgPrint("PciConfigSpace: 0x%x\n", HwInfo->PciConfigSpace);
+
+		DbgPrint("SarRamOffset: 0x%x\n", HwInfo->SarRamOffset);
+		DbgPrint("SarRamSize: 0x%x\n", HwInfo->SarRamSize);
+		DbgPrint("SarRam: 0x%x\n", HwInfo->SarRam);
+
+		DbgPrint("PermanentAddress: %02x-%02x-%02x-%02x-%02x-%02x\n",
+			HwInfo->PermanentAddress[0],
+			HwInfo->PermanentAddress[1],
+			HwInfo->PermanentAddress[2],
+			HwInfo->PermanentAddress[3],
+			HwInfo->PermanentAddress[4],
+			HwInfo->PermanentAddress[5]);
+	}
+}
+
+VOID
+dbgDumpPciFCodeImage(
+	IN	PPCI_FCODE_IMAGE	PciFcodeImage
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	if ((DBG_LEVEL_INFO >= gAic5900DebugLevel) &&
+		((gAic5900DebugSystems & DBG_COMP_INIT) == DBG_COMP_INIT))
+	{
+		//
+		//	Dump the fcode header.
+		//
+		DbgPrint("PCI FCode Image\n");
+		DbgPrint(" FCodeHeader 0x%x\n", PciFcodeImage->FCodeHeader);
+		DbgPrint(" Name 0x%x\n", PciFcodeImage->Name);
+		DbgPrint(" Model 0x%x\n", PciFcodeImage->Model);
+		DbgPrint(" Intr 0x%x\n", PciFcodeImage->Intr);
+		DbgPrint(" RomVersionNumber 0x%x\n", PciFcodeImage->RomVersionNumber);
+		DbgPrint(" RomVersionString 0x%x\n", PciFcodeImage->RomVersionString);
+		DbgPrint(" RomDateString 0x%x\n", PciFcodeImage->RomDateString);
+		DbgPrint(" roEpromOffset 0x%x\n", PciFcodeImage->roEpromOffset);
+		DbgPrint(" roEpromSize 0x%x\n", PciFcodeImage->roEpromSize);
+		DbgPrint(" rwEpromOffset 0x%x\n", PciFcodeImage->rwEpromOffset);
+		DbgPrint(" rwEpromSize 0x%x\n", PciFcodeImage->rwEpromSize);
+		DbgPrint(" PhyOffset 0x%x\n", PciFcodeImage->PhyOffset);
+		DbgPrint(" PhySize 0x%x\n", PciFcodeImage->PhySize);
+		DbgPrint(" ExternalOffset 0x%x\n", PciFcodeImage->ExternalOffset);
+		DbgPrint(" ExternalSize 0x%x\n", PciFcodeImage->ExternalSize);
+		DbgPrint(" SarOffset 0x%x\n", PciFcodeImage->SarOffset);
+		DbgPrint(" SarSize 0x%x\n", PciFcodeImage->SarSize);
+		DbgPrint(" PciConfigOffset 0x%x\n", PciFcodeImage->PciConfigOffset);
+		DbgPrint(" PciConfigSize 0x%x\n", PciFcodeImage->PciConfigSize);
+		DbgPrint(" SarMemOffset 0x%x\n", PciFcodeImage->SarMemOffset);
+		DbgPrint(" SarMemSize 0x%x\n", PciFcodeImage->SarMemSize);
+	}
+}
+
+
+VOID
+dbgDumpPciCommonConfig(
+	IN PPCI_COMMON_CONFIG	PciCommonConfig
+	)
+/*++
+
+Routine Description:
+
+	This routine will dump the PCI config header.
+
+Arguments:
+
+	PciCommonConfig	-	 Pointer to memory block that contains the PCI header.
+
+Return Value:
+
+	None.
+
+--*/
+{
+	UINT	c;
+
+	if ((DBG_LEVEL_INFO >= gAic5900DebugLevel) &&
+		((gAic5900DebugSystems & DBG_COMP_INIT) == DBG_COMP_INIT))
+	{
+		//
+		//	Display the PCI config info.
+		//
+		DbgPrint("PCI->VendorID = 0x%x\n", PciCommonConfig->VendorID);
+		DbgPrint("PCI->DeviceID = 0x%x\n", PciCommonConfig->DeviceID);
+		DbgPrint("PCI->Command = 0x%x\n", PciCommonConfig->Command);
+		DbgPrint("PCI->Status = 0x%x\n", PciCommonConfig->Status);
+		DbgPrint("PCI->RevisionID = 0x%x\n", PciCommonConfig->RevisionID);
+		DbgPrint("PCI->ProgIf = 0x%x\n", PciCommonConfig->ProgIf);
+		DbgPrint("PCI->SubClass = 0x%x\n", PciCommonConfig->SubClass);
+		DbgPrint("PCI->BaseClass = 0x%x\n", PciCommonConfig->BaseClass);
+		DbgPrint("PCI->CacheLineSize = 0x%x\n", PciCommonConfig->CacheLineSize);
+		DbgPrint("PCI->LatencyTimer = 0x%x\n", PciCommonConfig->LatencyTimer);
+		DbgPrint("PCI->HeaderType = 0x%x\n", PciCommonConfig->HeaderType);
+		DbgPrint("PCI->BIST = 0x%x\n", PciCommonConfig->BIST);
+	
+		for (c = 0; c < PCI_TYPE0_ADDRESSES; c++)
+		{
+			DbgPrint("PCI->BaseAddresses[%u] = 0x%x\n", c, PciCommonConfig->u.type0.BaseAddresses[c]);
+		}
+	
+		DbgPrint("PCI->SubVendorID = 0x%x\n", PciCommonConfig->u.type0.SubVendorID);
+		DbgPrint("PCI->SubSystemID = 0x%x\n", PciCommonConfig->u.type0.SubSystemID);
+	
+		DbgPrint("PCI->ROMBaseAddress = 0x%x\n", PciCommonConfig->u.type0.ROMBaseAddress);
+		DbgPrint("PCI->Reserved2.1 = 0x%x\n", PciCommonConfig->u.type0.Reserved2[0]);
+		DbgPrint("PCI->Reserved2.2 = 0x%x\n", PciCommonConfig->u.type0.Reserved2[1]);
+		DbgPrint("PCI->InterruptLine = 0x%x\n", PciCommonConfig->u.type0.InterruptLine);
+		DbgPrint("PCI->InterruptPin = 0x%x\n", PciCommonConfig->u.type0.InterruptPin);
+		DbgPrint("PCI->MinimumGrant = 0x%x\n", PciCommonConfig->u.type0.MinimumGrant);
+		DbgPrint("PCI->MaximumLatency = 0x%x\n", PciCommonConfig->u.type0.MaximumLatency);
+   	}
+}
+
+
+#endif
diff --git a/private/ntos/ndis/aic5900/debug.h b/private/ntos/ndis/aic5900/debug.h
new file mode 100644
index 000000000..c66b0ff86
--- /dev/null
+++ b/private/ntos/ndis/aic5900/debug.h
@@ -0,0 +1,106 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\debug.h
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#ifndef __DEBUG_H
+#define __DEBUG_H
+
+#define	DBG_LEVEL_INFO			0x0000
+#define	DBG_LEVEL_LOG			0x0800
+#define	DBG_LEVEL_WARN			0x1000
+#define	DBG_LEVEL_ERR			0x2000
+#define	DBG_LEVEL_FATAL			0x3000
+
+#define	DBG_COMP_INIT			0x00000001
+#define	DBG_COMP_SEND			0x00000002
+#define	DBG_COMP_RECV			0x00000004
+#define DBG_COMP_REQUEST		0x00000008
+#define DBG_COMP_UNLOAD			0x00000010
+#define	DBG_COMP_LOCKS			0x00000020
+#define DBG_COMP_VC				0x00000040
+
+#define	DBG_COMP_ALL			0xFFFFFFFF
+
+#if DBG
+
+VOID
+dbgDumpHardwareInformation(
+	IN	PHARDWARE_INFO	HwInfo
+	);
+
+VOID
+dbgDumpPciFCodeImage(
+	IN	PPCI_FCODE_IMAGE	PciFcodeImage
+	);
+
+VOID
+dbgDumpPciCommonConfig(
+	IN	PPCI_COMMON_CONFIG	PciCommonConfig
+	);
+
+VOID
+dbgInitializeDebugInformation(
+	IN	PADAPTER_BLOCK	pAdapter
+	);
+
+extern	ULONG	gAic5900DebugSystems;
+extern	LONG	gAic5900DebugLevel;
+extern	ULONG	gAic5900DebugInformationOffset;
+
+#define DBGPRINT(Component, Level, Fmt)								\
+{																	\
+	if ((Level >= gAic5900DebugLevel) &&							\
+		((gAic5900DebugSystems & Component) == Component))			\
+	{																\
+		DbgPrint("***AIC5900*** (%x, %d) ",							\
+				MODULE_NUMBER >> 16, __LINE__);						\
+		DbgPrint Fmt;												\
+	}																\
+}
+
+#define DBGBREAK(Component, Level)												\
+{																				\
+	if ((Level >= gAic5900DebugLevel) && (gAic5900DebugSystems & Component))	\
+	{																			\
+		DbgPrint("***AIC5900*** DbgBreak @ %x, %d", MODULE_NUMBER, __LINE__);	\
+		DbgBreakPoint();														\
+	}																			\
+}
+
+#define IF_DBG(Component, Level)	if ((Level >= gAic5900DebugLevel) && (gAic5900DebugSystems & Component))
+
+#else
+
+#define	dbgDumpHardwareInformation(HwInfo)
+#define dbgDumpPciFCodeImage(PciFcodeImage)
+#define	dbgDumpPciCommonConfig(_PciCommonConfig)
+
+#define dbgInitializeDebugInformation(_Adapter)
+
+#define DBGPRINT(Component, Level, Fmt)
+#define DBGBREAK(Component, Level)
+
+#define IF_DBG(Component, Level)	if (FALSE)
+
+#endif
+
+#endif  //  __DEBUG_H
diff --git a/private/ntos/ndis/aic5900/dirs b/private/ntos/ndis/aic5900/dirs
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/private/ntos/ndis/aic5900/dirs
diff --git a/private/ntos/ndis/aic5900/eeprom.h b/private/ntos/ndis/aic5900/eeprom.h
new file mode 100644
index 000000000..35dfbd1b0
--- /dev/null
+++ b/private/ntos/ndis/aic5900/eeprom.h
@@ -0,0 +1,174 @@
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\eeprom.h
+
+Abstract:
+
+	AIC5900 PCI EEPROM information.
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#ifndef __EEPROM_H
+#define __EEPROM_H
+
+#define EEPROM_READ_BUFFER(pDst, pSrc, Length)								\
+{																			\
+	UINT	_c;																\
+																			\
+	for (_c = 0; _c < Length; _c++)											\
+	{																		\
+		NdisReadRegisterUchar((PUCHAR)(pSrc) + _c, (PUCHAR)(pDst) + _c);	\
+	}																		\
+}
+
+#define EEPROM_READ_UCHAR(Src, Dst)		NdisReadRegisterUchar((Src), (Dst))
+
+#define	EEPROM_READ_ULONG(Src, Dst)									\
+{																	\
+	NdisReadRegisterUchar((PUCHAR)(Src) + 0, (PUCHAR)(Dst) + 3);	\
+	NdisReadRegisterUchar((PUCHAR)(Src) + 1, (PUCHAR)(Dst) + 2);	\
+	NdisReadRegisterUchar((PUCHAR)(Src) + 2, (PUCHAR)(Dst) + 1);	\
+	NdisReadRegisterUchar((PUCHAR)(Src) + 3, (PUCHAR)(Dst) + 0);	\
+}
+
+#define	AIC_ULONG_TO_ULONG(Dst, Src)								\
+{																	\
+	*((PUCHAR)(Dst) + 3) = *((PUCHAR)(Src) + 0);					\
+	*((PUCHAR)(Dst) + 2) = *((PUCHAR)(Src) + 1);					\
+	*((PUCHAR)(Dst) + 1) = *((PUCHAR)(Src) + 2);					\
+	*((PUCHAR)(Dst) + 0) = *((PUCHAR)(Src) + 3);					\
+}
+
+
+//
+//	EEPROM manufacturer structure.
+//
+typedef struct EEPROM_MANUFACTURER_INFO
+{
+	UCHAR	MacAddress[6];
+	UCHAR	InverseMacAddress[6];
+	UCHAR	Padding[52];
+}
+	EEPROM_MANUFACTURER_INFO,
+	*PEEPROM_MANUFACTURER_INFO;
+
+
+
+//
+//	BUGBUG: Remove this structure if i don't use it anywhere.
+//
+//	Structure definitions
+//
+typedef struct PCI_ROM_BIOS_HEADER
+{
+	UCHAR	PciBiosSignature[2];	//	Literal 0x55AA
+	UCHAR	PciFCodeOffset[2];		//	Offset from the begining of
+									//	this header to where the FCode
+									//	image starts.  This item is
+									//	storred as little endian
+	UCHAR	Reserved[18];			//	PCI forum reserved space
+	UCHAR	PciDataOffset[2];		//	Offset from the begining of
+									//	this header to where the PCI
+									//	data structure image starts.
+									//	This item is storred as
+									//	little endian.
+}
+	PCI_ROM_BIOS_HEADER,
+	*PPCI_ROM_BIOS_HEADER;
+
+
+#define	FCODE_NAME					((ULONG)'atmo')
+
+//
+//	Offsets into the PCI_FCODE_IMAGE.
+//
+#define	FCODE_HEADER_LEN			0x08	//	FCode tokenizer crates this header
+#define	NAME_STRING_OFFSET			0x100	//	pascal string at this offset
+#define	MODEL_STRING_OFFSET			0x180	//	pascal string at this offset
+#define	INTERUPT_NUM_OFFSET			0x200	//	32-bit number at this offset
+#define	VERSION_NUM_OFFSET			0x280	//	pascal string at this offset
+#define	VERSION_STRING_OFFSET		0x300	//	pascal string at this offset
+#define	DATE_STRING_OFFSET			0x380	//	pascal string at this offset
+
+#define	EEPROM_R_ADDR_OFFSET		0x400	//	32-bit number at this offset
+#define	EEPROM_R_SIZE_OFFSET		0x40C	//	32-bit number at this offset
+
+#define	EEPROM_RW_ADDR_OFFSET		0x420	//	32-bit number at this offset
+#define	EEPROM_RW_SIZE_OFFSET		0x42C	//	32-bit number at this offset
+
+#define	PHY_REGS_ADDR_OFFSET		0x440	//	32-bit number at this offset
+#define	PHY_REGS_SIZE_OFFSET		0x44C	//	32-bit number at this offset
+
+#define	EXTERN_REGS_ADDR_OFFSET		0x460	//	32-bit number at this offset
+#define	EXTERN_REGS_SIZE_OFFSET		0x46C	//	32-bit number at this offset
+
+#define	ORION_SAR_REGS_ADDR_OFFSET	0x480	//	32-bit number at this offset
+#define	ORION_SAR_REGS_SIZE_OFFSET	0x48C	//	32-bit number at this offset
+
+#define	ORION_PCI_REGS_ADDR_OFFSET	0x4A0	//	32-bit number at this offset
+#define	ORION_PCI_REGS_SIZE_OFFSET	0x4AC	//	32-bit number at this offset
+
+#define	SRAM_ADDR_OFFSET			0x4C0	//	32-bit number at this offset
+#define	SRAM_SIZE_OFFSET			0x4CC	//	32-bit number at this offset
+
+#define	FCODE_SIZE					0x64B
+
+//
+//	Format of the PCI FCode.
+//
+typedef struct PCI_FCODE_IMAGE
+{
+	UCHAR	FCodeHeader[NAME_STRING_OFFSET];
+	
+	UCHAR	Name[MODEL_STRING_OFFSET - NAME_STRING_OFFSET];
+	
+	UCHAR	Model[INTERUPT_NUM_OFFSET - MODEL_STRING_OFFSET];
+	
+	UCHAR	Intr[VERSION_NUM_OFFSET - INTERUPT_NUM_OFFSET];
+	
+	UCHAR	RomVersionNumber[VERSION_STRING_OFFSET - VERSION_NUM_OFFSET];
+	
+	UCHAR	RomVersionString[DATE_STRING_OFFSET - VERSION_STRING_OFFSET];
+	
+	UCHAR	RomDateString[EEPROM_R_ADDR_OFFSET - DATE_STRING_OFFSET];
+	
+	UCHAR	roEpromOffset[EEPROM_R_SIZE_OFFSET - EEPROM_R_ADDR_OFFSET];
+	UCHAR	roEpromSize[EEPROM_RW_ADDR_OFFSET - EEPROM_R_SIZE_OFFSET];
+	
+	UCHAR	rwEpromOffset[EEPROM_RW_SIZE_OFFSET - EEPROM_RW_ADDR_OFFSET];
+	UCHAR	rwEpromSize[PHY_REGS_ADDR_OFFSET - EEPROM_RW_SIZE_OFFSET];
+	
+	UCHAR	PhyOffset[PHY_REGS_SIZE_OFFSET - PHY_REGS_ADDR_OFFSET];
+	UCHAR	PhySize[EXTERN_REGS_ADDR_OFFSET - PHY_REGS_SIZE_OFFSET];
+	
+	UCHAR	ExternalOffset[EXTERN_REGS_SIZE_OFFSET - EXTERN_REGS_ADDR_OFFSET];
+	UCHAR	ExternalSize[ORION_SAR_REGS_ADDR_OFFSET - EXTERN_REGS_SIZE_OFFSET];
+	
+	UCHAR	SarOffset[ORION_SAR_REGS_SIZE_OFFSET - ORION_SAR_REGS_ADDR_OFFSET];
+	UCHAR	SarSize[ORION_PCI_REGS_ADDR_OFFSET - ORION_SAR_REGS_SIZE_OFFSET];
+	
+	UCHAR	PciConfigOffset[ORION_PCI_REGS_SIZE_OFFSET - ORION_PCI_REGS_ADDR_OFFSET];
+	UCHAR	PciConfigSize[SRAM_ADDR_OFFSET - ORION_PCI_REGS_SIZE_OFFSET];
+	
+	UCHAR	SarMemOffset[SRAM_SIZE_OFFSET - SRAM_ADDR_OFFSET];
+	UCHAR	SarMemSize[FCODE_SIZE - SRAM_SIZE_OFFSET];
+}
+	PCI_FCODE_IMAGE,
+	*PPCI_FCODE_IMAGE;
+
+
+#endif // __EEPROM_H
diff --git a/private/ntos/ndis/aic5900/hw.h b/private/ntos/ndis/aic5900/hw.h
new file mode 100644
index 000000000..6347266e9
--- /dev/null
+++ b/private/ntos/ndis/aic5900/hw.h
@@ -0,0 +1,502 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\hw.h
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#ifndef __HW_H
+#define __HW_H
+
+//
+//	New types and forward pointers...
+//
+typedef struct 	_HARDWARE_INFO			HARDWARE_INFO, *PHARDWARE_INFO;
+typedef struct	_ADAPTER_BLOCK			ADAPTER_BLOCK, *PADAPTER_BLOCK;
+typedef struct	_VC_BLOCK				VC_BLOCK, *PVC_BLOCK;
+
+typedef struct	_XMIT_SEG_CHANNEL		XMIT_SEG_CHANNEL, *PXMIT_SEG_CHANNEL;
+typedef struct	_SAR_INFO				SAR_INFO, *PSAR_INFO;
+
+typedef struct	_MIDWAY_XMIT_REGISTERS	MIDWAY_XMIT_REGISTERS, *PMIDWAY_XMIT_REGISTERS;
+typedef struct	_MIDWAY_REGISTERS		MIDWAY_REGISTERS, *PMIDWAY_REGISTERS;
+
+typedef	volatile ULONG		HWUL, *PHWUL;
+typedef	volatile UCHAR		HWUC, *PHWUC;
+
+#define BIT(x)				(1 << (x))
+
+
+//
+//	VC range supported by the aic5900
+//
+#define	MAX_VCS				1024
+#define MIN_VCS				0
+
+//
+//	NIC Cell clock rate.
+//
+//
+//
+#define	CELL_CLOCK_25MHZ	(25000000)
+#define	CELL_CLOCK_16MHZ	(16000000)
+
+//
+//	PCI id's
+//
+#define	ADAPTEC_PCI_VENDOR_ID				0x9004
+#define AIC5900_PCI_DEVICE_ID				0x5900
+
+//
+//	Adaptec ATM adapter models supported.
+//
+#define ANA_5910        5
+#define ANA_5930        7
+#define ANA_5940        8
+
+#define ANA_INVALID		(UINT)-1
+
+
+//
+//
+//
+//
+#define	ATM_ADDRESS_LENGTH		6
+
+#define PCI_DEVICE_SPECIFIC_OFFSET	0x40
+
+typedef	union	_PCI_DEVICE_CONFIG
+{
+	struct
+	{
+		UCHAR	SoftwareReset:1;
+		UCHAR	EnableInterrupt:1;
+		UCHAR	TargetSwapBytes:1;
+		UCHAR	MasterSwapBytes:1;
+		UCHAR	EnableIncrement:1;
+		UCHAR	SoftwareInterrupt:1;
+		UCHAR	TestDMA:1;
+		UCHAR	Reserved:1;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_CONFIG,
+	*PPCI_DEVICE_CONFIG;
+
+typedef	union	_PCI_DEVICE_STATUS
+{
+	struct
+	{
+		UCHAR	VoltageSense:1;
+		UCHAR	IllegalByteEnable:1;
+		UCHAR	IllegalWrite:1;
+		UCHAR	IllegalOverlap:1;
+		UCHAR	IllegalDescriptor:1;
+		UCHAR	Reserved:3;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_STATUS,
+	*PPCI_DEVICE_STATUS;
+
+typedef	union	_PCI_DEVICE_INTERRUPT_STATUS
+{
+	struct
+	{
+		UCHAR	DprInt:1;
+		UCHAR	reserved:2;
+		UCHAR	StaInt:1;
+		UCHAR	RtaInt:1;
+		UCHAR	RmaInt:1;
+		UCHAR	SseInt:1;
+		UCHAR	DpeInt:1;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_INTERRUPT_STATUS,
+	*PPCI_DEVICE_INTERRUPT_STATUS;
+
+typedef	union	_PCI_DEVICE_ENABLE_PCI_INTERRUPT
+{
+	struct
+	{
+		UCHAR	EnableDprInt:1;
+		UCHAR	reserved:2;
+		UCHAR	EnableStaInt:1;
+		UCHAR	EnableRtaInt:1;
+		UCHAR	EnableRmaInt:1;
+		UCHAR	EnableSseInt:1;
+		UCHAR	EnableDpeInt:1;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_ENABLE_PCI_INTERRUPT,
+	*PPCI_DEVICE_ENABLE_PCI_INTERRUPT;
+
+typedef	union	_PCI_DEVICE_GENERAL_PURPOSE_IO_REGISTERS
+{
+	struct
+	{
+		UCHAR	GPIOREG0:1;
+		UCHAR	GPIOREG1:1;
+		UCHAR	GPIOREG2:1;
+		UCHAR	GPIOREG3:1;
+		UCHAR	reserved:4;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_GENERAL_PURPOSE_IO_REGISTERS,
+	*PPCI_DEVICE_GENERAL_PURPOSE_IO_REGISTERS;
+
+typedef	union	_PCI_DEVICE_GENERAL_PURPOSE_IOCTL
+{
+	struct
+	{
+		UCHAR	GPIOCTL0:1;
+		UCHAR	GPIOCTL1:1;
+		UCHAR	GPIOCTL2:1;
+		UCHAR	GPIOCTL3:1;
+		UCHAR	reserved:4;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_GENERAL_PURPOSE_IOCTL,
+	*PPCI_DEVICE_GENERAL_PURPOSE_IOCTL;
+
+typedef	union	_PCI_DEVICE_DMA_CONTROL
+{
+	struct
+	{
+		UCHAR	StopOnPerr:1;
+		UCHAR	DualAddressCycleEnable:1;
+		UCHAR	CacheThresholdEnable:1;
+		UCHAR	MemoryReadCmdEnable:1;
+		UCHAR	Reserved:4;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_DMA_CONTROL,
+	*PPCI_DEVICE_DMA_CONTROL;
+
+typedef	union	_PCI_DEVICE_DMA_STATUS
+{
+	struct
+	{
+		UCHAR	FifoEmpty:1;
+		UCHAR	FifoFull:1;
+		UCHAR	FifoThreshold:1;
+		UCHAR	HostDmaDone:1;
+		UCHAR	FifoCacheThreshold:1;
+		UCHAR	Reserved:3;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_DMA_STATUS,
+	*PPCI_DEVICE_DMA_STATUS;
+
+typedef	union	_PCI_DEVICE_DMA_DIAG
+{
+	struct
+	{
+		UCHAR	HostDmaEnable:1;
+		UCHAR	DataPathDirection:1;
+		UCHAR	Reserved:6;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_DMA_DIAG,
+	*PPCI_DEVICE_DMA_DIAG;
+
+typedef	union	_PCI_DEVICE_HOST_COUNT
+{
+	struct
+	{
+		ULONG	hcLowLow:8;
+		ULONG	hcLowHigh:8;
+		ULONG	hcHighLow:8;
+		ULONG	Reserved:8;
+	};
+
+	ULONG	reg;
+}
+	PCI_DEVICE_HOST_COUNT,
+	*PPCI_DEVICE_HOST_COUNT;
+
+typedef	union	_PCI_DEVICE_DATA_FIFO_READ_ADDRESS
+{
+	struct
+	{
+	   UCHAR	MasterFifoPointer:7;
+	   UCHAR	Reserved:1;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_DATA_FIFO_READ_ADDRESS,
+	*PPCI_DEVICE_DATA_FIFO_READ_ADDRESS;
+
+typedef	union	_PCI_DEVICE_DATA_FIFO_WRITE_ADDRESS
+{
+	struct
+	{
+		UCHAR	MasterFifoPointer:7;
+		UCHAR	Reserved:1;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_DATA_FIFO_WRITE_ADDRESS,
+	*PPCI_DEVICE_DATA_FIFO_WRITE_ADDRESS;
+
+typedef	union	_PCI_DEVICE_DATA_FIFO_THRESHOLD
+{
+	struct
+	{
+		UCHAR	Reserved0:2;
+		UCHAR	DFTHRSH:4;
+		UCHAR	Reserved1:2;
+	};
+
+	UCHAR	reg;
+}
+	PCI_DEVICE_DATA_FIFO_THRESHOLD,
+	*PPCI_DEVICE_DATA_FIFO_THRESHOLD;
+
+typedef	union	_PCI_DEVICE_LOW_HOST_ADDRESS
+{
+	struct
+	{
+		UCHAR	lhaLowLow;
+		UCHAR	lhaLowHigh;
+		UCHAR	lhaHighLow;
+		UCHAR	lhaHighHigh;
+	};
+
+	ULONG	reg;
+}
+	PCI_DEVICE_LOW_HOST_ADDRESS,
+	*PPCI_DEVICE_LOW_HOST_ADDRESS;
+
+typedef	union	_PCI_DEVICE_HIGH_HOST_ADDRESS
+{
+	struct
+	{
+		ULONG	hhaLowLow:8;
+		ULONG	hhaLowHigh:8;
+		ULONG	hhaHighLow:8;
+		ULONG	hhaHighHigh:8;
+	};
+
+	ULONG	reg;
+}
+	PCI_DEVICE_HIGH_HOST_ADDRESS,
+	*PPCI_DEVICE_HIGH_HOST_ADDRESS;
+
+typedef	union	_PCI_DEVICE_FIFO_DATA_REGISTER
+{
+	struct
+	{
+		ULONG	dfrLowLow:8;
+		ULONG	dfrLowHigh:8;
+		ULONG	dfrHighLow:8;
+		ULONG	dfrHighHigh:8;
+	};
+
+	ULONG	reg;
+}
+	PCI_DEVICE_FIFO_DATA_REGISTER,
+	*PPCI_DEVICE_FIFO_DATA_REGISTER;
+
+typedef	union	_PCI_DEVICE_DATA_ADDRESS
+{
+	struct
+	{
+		ULONG	daLowLow:8;
+		ULONG	daLowHigh:8;
+		ULONG	daHighLow:8;
+		ULONG	daHighHigh:8;
+	};
+
+	ULONG	reg;
+}
+	PCI_DEVICE_DATA_ADDRESS,
+	*PPCI_DEVICE_DATA_ADDRESS;
+
+typedef	union	_PCI_DEVICE_DATA_PORT
+{
+	struct
+	{
+		ULONG	dpLowLow:8;
+		ULONG	dpLowHigh:8;
+		ULONG	dpHighLow:8;
+		ULONG	dpHighHigh:8;
+	};
+
+	ULONG	reg;
+}
+	PCI_DEVICE_DATA_PORT,
+	*PPCI_DEVICE_DATA_PORT;
+
+#define	PCI_DEVICE_CONFIG_OFFSET			0x40
+#define	PCI_DEVICE_STATUS_OFFSET			0x41
+#define	PCI_INTERRUPT_STATUS_OFFSET			0x44
+#define	PCI_ENABLE_INTERRUPT_OFFSET			0x45
+#define	PCI_GENERAL_PURPOSE_IO_PORT_OFFSET	0x46
+#define	PCI_GENERAL_PURPOSE_IOCTL_OFFSET	0x47
+#define	PCI_DMA_CONTROL_OFFSET				0x4C
+#define PCI_DMA_STATUS_OFFSET				0x4D
+#define PCI_DMA_DIAGNOSTIC_OFFSET			0x4E
+#define	PCI_HOST_COUNT0_OFFSET				0x50
+#define	PCI_HOST_COUNT1_OFFSET				0x51
+#define	PCI_HOST_COUNT2_OFFSET				0x52
+#define	PCI_DATA_FIFO_READ_ADDRESS_OFFSET	0x54
+#define PCI_DATA_FIFO_WRITE_ADDRESS_OFFSET	0x55
+#define	PCI_DATA_FIFO_THRESHOLD_OFFSET		0x56
+#define	PCI_LOW_HOST_ADDRESS0_OFFSET		0x58
+#define	PCI_LOW_HOST_ADDRESS1_OFFSET		0x59
+#define	PCI_LOW_HOST_ADDRESS2_OFFSET		0x5A
+#define	PCI_LOW_HOST_ADDRESS3_OFFSET		0x5B
+#define	PCI_HIGH_HOST_ADDRESS0_OFFSET		0x5C
+#define	PCI_HIGH_HOST_ADDRESS1_OFFSET		0x5D
+#define	PCI_HIGH_HOST_ADDRESS2_OFFSET		0x5E
+#define	PCI_HIGH_HOST_ADDRESS3_OFFSET		0x5F
+#define	PCI_FIFO_DATA_REGISTER0_OFFSET		0x60
+#define	PCI_FIFO_DATA_REGISTER1_OFFSET		0x61
+#define	PCI_FIFO_DATA_REGISTER2_OFFSET		0x62
+#define	PCI_FIFO_DATA_REGISTER3_OFFSET		0x63
+
+
+#define SET_PCI_DEV_CFG(_HwInfo, _reg)					NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DEVICE_CONFIG_OFFSET), (_reg))
+#define GET_PCI_DEV_CFG(_HwInfo, _reg)					NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DEVICE_CONFIG_OFFSET), (PUCHAR)(_reg))
+			
+
+#define SET_PCI_DEV_STATUS(_HwInfo, _reg)				NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DEVICE_STATUS_OFFSET), (_reg))
+#define GET_PCI_DEV_STATUS(_HwInfo, _reg)				NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DEVICE_STATUS_OFFSET), (PUCHAR)(_reg))
+		
+#define SET_PCI_DEV_INT_STATUS(_HwInfo, _reg)			NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_INTERRUPT_STATUS_OFFSET), (_reg))
+#define GET_PCI_DEV_INT_STATUS(_HwInfo, _reg)			NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_INTERRUPT_STATUS_OFFSET), (PUCHAR)(_reg))
+		
+#define SET_PCI_DEV_ENABLE_INT(_HwInfo, _reg)			NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_ENABLE_INTERRUPT_OFFSET), (_reg))
+#define GET_PCI_DEV_ENABLE_INT(_HwInfo, _reg)			NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_ENABLE_INTERRUPT_OFFSET), (PUCHAR)(_reg))
+		
+		
+#define SET_PCI_DEV_GP_IO_REG(_HwInfo, _reg)			NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_GENERAL_PURPOSE_IO_PORT_OFFSET), (_reg))
+#define GET_PCI_DEV_GP_IO_REG(_HwInfo, _reg)			NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_GENERAL_PURPOSE_IO_PORT_OFFSET), (PUCHAR)(_reg))
+		
+#define SET_PCI_DEV_GP_IOCTL(_HwInfo, _reg)				NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_GENERAL_PURPOSE_IOCTL_OFFSET), (_reg))
+#define GET_PCI_DEV_GP_IOCTL(_HwInfo, _reg)				NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_GENERAL_PURPOSE_IOCTL_OFFSET), (PUCHAR)(_reg))
+		
+#define SET_PCI_DEV_DMA_CONTROL(_HwInfo, _reg)			NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_CONTROL_OFFSET), (_reg))
+#define GET_PCI_DEV_DMA_CONTROL(_HwInfo, _reg)			NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_CONTROL_OFFSET), (PUCHAR)(_reg))
+		
+#define SET_PCI_DEV_DMA_STATUS(_HwInfo, _reg)			NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_STATUS_OFFSET), (_reg))
+#define GET_PCI_DEV_DMA_STATUS(_HwInfo, _reg)			NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_STATUS_OFFSET), (PUCHAR)(_reg))
+		
+		
+#define SET_PCI_DEV_DMA_DIAG(_HwInfo, _reg)				NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_DIAGNOSTIC_OFFSET), (_reg))
+#define GET_PCI_DEV_DMA_DIAG(_HwInfo, _reg)				NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_DIAGNOSTIC_OFFSET), (PUCHAR)(_reg))
+		
+#define SET_PCI_DEV_DATA_READ_ADDRESS(_HwInfo, _reg)	NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_READ_ADDRESS_OFFSET), (_reg))
+#define GET_PCI_DEV_DATA_READ_ADDRESS(_HwInfo, _reg)	NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_READ_ADDRESS_OFFSET), (PUCHAR)(_reg))
+
+#define SET_PCI_DEV_DATA_WRITE_ADDRESS(_HwInfo, _reg)	NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_WRITE_ADDRESS_OFFSET), (_reg))
+#define GET_PCI_DEV_DATA_WRITE_ADDRESS(_HwInfo, _reg)	NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_WRITE_ADDRESS_OFFSET), (PUCHAR)(_reg))
+
+#define SET_PCI_DEV_DATA_THRESHOLD(_HwInfo, _reg)		NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_THRESHOLD_OFFSET), (_reg))
+#define GET_PCI_DEV_DATA_THRESHOLD(_HwInfo, _reg)		NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_THRESHOLD_OFFSET), (PUCHAR)(_reg))
+
+
+//////////////////////////////////////////////////////////////////////////
+//
+//				SUNI REGISTER SET
+//
+//////////////////////////////////////////////////////////////////////////
+
+//
+//	SUNI Master Reset and Identify register.
+//
+#define	SUNI_MASTER_RESET_IDENTITY							0x00
+#define	SET_SUNI_MASTER_RESET_IDEN(_HwInfo, _value)			NdisWriteRegisterUchar(((_HwInfo)->Phy + SUNI_MASTER_RESET_IDENTITY), (_value))
+#define	GET_SUNI_MASTER_RESET_IDEN(_HwInfo, _value)			NdisReadRegisterUchar(((_HwInfo)->Phy + SUNI_MASTER_RESET_IDENTITY), (_value))
+	
+#define fSUNI_MRI_RESET										0x80
+
+//
+//	RACP Interrupt Enable/Status
+//
+#define	SUNI_RACP_INTERRUPT_ENABLE_STATUS					0x144
+#define	SET_SUNI_RACP_INT_ENABLE_STATUS(_HwInfo, _value)	NdisWriteRegisterUchar(((_HwInfo)->Phy + SUNI_RACP_INTERRUPT_ENABLE_STATUS), (_value))
+#define	GET_SUNI_RACP_INT_ENABLE_STATUS(_HwInfo, _value)	NdisReadRegisterUchar(((_HwInfo)->Phy + SUNI_RACP_INTERRUPT_ENABLE_STATUS), (_value))
+
+#define	fSUNI_RACP_IES_FUDRI								0x01
+#define	fSUNI_RACP_IES_FOVRI								0x02
+#define	fSUNI_RACP_IES_UHCSI								0x04
+#define	fSUNI_RACP_IES_CHCSI								0x08
+#define	fSUNI_RACP_IES_OOCDI								0x10
+#define	fSUNI_RACP_IES_FIFOE								0x20
+#define fSUNI_RACP_IES_HCSE									0x40
+#define	fSUNI_RACP_IES_OOCDE								0x80
+
+
+//
+//	Master Test
+//
+#define SUNI_MASTER_TEST									0x200
+#define	SET_SUNI_MASTER_TEST(_HwInfo, _value)				NdisWriteRegisterUchar(((_HwInfo)->Phy + SUNI_MASTER_TEST), (_value))
+#define GET_SUNI_MASTER_TEST(_HwInfo, _value)				NdisReadRegisterUchar(((_HwInfo)->Phy + SUNI_MASTER_TEST), (_value))
+
+//////////////////////////////////////////////////////////////////////////
+//
+//			IBM	25Mbp TC chipset
+//
+//////////////////////////////////////////////////////////////////////////
+
+#define	IBM_TC_STATUS									0x00
+#define SET_IBM_TC_STATUS(_HwInfo, _value)				NdisWriteRegisterUchar(((_HwInfo)->Phy + IBM_TC_STATUS), (_value))
+#define GET_IBM_TC_STATUS(_HwInfo, _value)				NdisReadRegisterUchar(((_HwInfo)->Phy + IBM_TC_STATUS), (_value))
+		
+#define	IBM_TC_MODE										0x00
+#define SET_IBM_TC_MODE(_HwInfo, _value)				NdisWriteRegisterUchar(((_HwInfo)->Phy + IBM_TC_MODE), (_value))
+#define GET_IBM_TC_MODE(_HwInfo, _value)				NdisReadRegisterUchar(((_HwInfo)->Phy + IBM_TC_MODE), (_value))
+
+#define	IBM_TC_FLUSH_RECEIVE_FIFO						0x00
+#define SET_IBM_TC_FLUSH_RECEIVE_FIFO(_HwInfo, _value)	NdisWriteRegisterUchar(((_HwInfo)->Phy + IBM_TC_FLUSH_RECEIVE_FIFO), (_value))
+#define GET_IBM_TC_FLUSH_RECEIVE_FIFO(_HwInfo, _value)	NdisReadRegisterUchar(((_HwInfo)->Phy + IBM_TC_FLUSH_RECEIVE_FIFO), (_value))
+
+#define	IBM_TC_SOFTWARE_RESET							0x00
+#define SET_IBM_TC_SOFTWARE_RESET(_HwInfo, _value)		NdisWriteRegisterUchar(((_HwInfo)->Phy + IBM_TC_SOFTWARE_RESET), (_value))
+#define GET_IBM_TC_SOFTWARE_RESET(_HwInfo, _value)		NdisReadRegisterUchar(((_HwInfo)->Phy + IBM_TC_SOFTWARE_RESET), (_value))
+
+#define	IBM_TC_MASK										0x00
+#define SET_IBM_TC_MASK(_HwInfo, _value)				NdisWriteRegisterUchar(((_HwInfo)->Phy + IBM_TC_MASK), (_value))
+#define GET_IBM_TC_MASK(_HwInfo, _value)				NdisReadRegisterUchar(((_HwInfo)->Phy + IBM_TC_MASK), (_value))
+
+
+#endif // __HW_H
+
+
diff --git a/private/ntos/ndis/aic5900/init.c b/private/ntos/ndis/aic5900/init.c
new file mode 100644
index 000000000..5c497d026
--- /dev/null
+++ b/private/ntos/ndis/aic5900/init.c
@@ -0,0 +1,1534 @@
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\init.c
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#include "aic5900.h"
+
+#define	MODULE_NUMBER	MODULE_INIT
+
+#pragma NDIS_INIT_FUNCTION(DriverEntry)
+
+NTSTATUS
+DriverEntry(
+	IN	PDRIVER_OBJECT	DriverObject,
+	IN	PUNICODE_STRING	RegistryPath
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	NDIS_STATUS						Status;
+	NDIS_MINIPORT_CHARACTERISTICS	Aic5900Chars;
+	NDIS_HANDLE						hWrapper;
+
+	//
+	//	Initialize the wrapper.
+	//
+	NdisMInitializeWrapper(
+		&hWrapper,
+		DriverObject,
+		RegistryPath,
+		NULL);
+
+	NdisZeroMemory(&Aic5900Chars, sizeof(Aic5900Chars));
+
+	//
+	//	Initialize the miniport characteristics.
+	//
+	Aic5900Chars.MajorNdisVersion = AIC5900_NDIS_MAJOR_VERSION;
+	Aic5900Chars.MinorNdisVersion = AIC5900_NDIS_MINOR_VERSION;
+	Aic5900Chars.CheckForHangHandler = Aic5900CheckForHang;
+	Aic5900Chars.DisableInterruptHandler = Aic5900DisableInterrupt;
+	Aic5900Chars.EnableInterruptHandler = Aic5900EnableInterrupt;
+	Aic5900Chars.HaltHandler = Aic5900Halt;
+	Aic5900Chars.HandleInterruptHandler = Aic5900HandleInterrupt;
+	Aic5900Chars.InitializeHandler = Aic5900Initialize;
+	Aic5900Chars.ISRHandler = Aic5900ISR;
+	Aic5900Chars.ReconfigureHandler = NULL;
+	Aic5900Chars.ResetHandler = Aic5900Reset;
+
+	Aic5900Chars.ReturnPacketHandler = Aic5900ReturnPackets;
+	Aic5900Chars.AllocateCompleteHandler = Aic5900AllocateComplete;
+	Aic5900Chars.SetInformationHandler = Aic5900SetInformation;
+	Aic5900Chars.QueryInformationHandler = Aic5900QueryInformation;
+
+	Aic5900Chars.CoSendPacketsHandler = Aic5900SendPackets;
+
+	Aic5900Chars.CoCreateVcHandler = Aic5900CreateVc;
+	Aic5900Chars.CoDeleteVcHandler = Aic5900DeleteVc;
+	Aic5900Chars.CoActivateVcHandler = Aic5900ActivateVc;
+	Aic5900Chars.CoDeactivateVcHandler = Aic5900DeactivateVc;
+	Aic5900Chars.CoRequestHandler = Aic5900Request;
+
+	//
+	//	Register the miniport with NDIS.
+	//
+	Status = NdisMRegisterMiniport(
+				hWrapper,
+				&Aic5900Chars,
+				sizeof(Aic5900Chars));
+	if (NDIS_STATUS_SUCCESS == Status)
+	{
+		//
+		//	Save the handle to the wrapper.
+		//	
+		gWrapperHandle = hWrapper;
+	}
+#if DBG
+	else
+	{
+		DbgPrint("NdisMRegisterMiniport failed! Status: 0x%x\n", Status);
+	}
+#endif
+
+
+	return(Status);
+}
+
+
+NDIS_STATUS
+aic5900ReadConfigurationInformation(
+	IN	NDIS_HANDLE					ConfigurationHandle,
+	IN	PAIC5900_REGISTRY_PARAMETER	pRegistryParameter
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	NDIS_STATUS						Status;
+	NDIS_HANDLE						ConfigHandle;
+	PNDIS_CONFIGURATION_PARAMETER	pConfigParameter;
+	UINT							c;
+
+	//
+	//	Open the configuration section of the registry for this adapter.
+	//
+	NdisOpenConfiguration(&Status, &ConfigHandle, ConfigurationHandle);
+	if (NDIS_STATUS_SUCCESS != Status)
+	{
+		DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+			("Unable to open the Aic5900's Parameters registry key\n"));
+
+		return(Status);
+	}
+
+	//
+	//	Read in the registry parameters.
+	//
+	for (c = 0; c < Aic5900MaxRegistryEntry; c++)
+	{
+		NdisReadConfiguration(
+			&Status,
+			&pConfigParameter,
+			ConfigHandle,
+			&gaRegistryParameterString[c],
+			NdisParameterHexInteger);
+		if (NDIS_STATUS_SUCCESS == Status)
+		{
+			pRegistryParameter[c].fPresent = TRUE;
+			pRegistryParameter[c].Value = pConfigParameter->ParameterData.IntegerData;
+
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
+				("Read registry parameter: %u = 0x%x\n", c, pRegistryParameter[c].Value));
+		}
+
+	}
+
+	//
+	//	Close the configuration handle.
+	//
+	NdisCloseConfiguration(ConfigHandle);
+
+	return(NDIS_STATUS_SUCCESS);
+}
+
+NDIS_STATUS
+aic5900ReadPciConfiguration(
+	IN	PADAPTER_BLOCK	pAdapter
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	PPCI_COMMON_CONFIG				PciCommonConfig;
+	PHARDWARE_INFO					pHwInfo = pAdapter->HardwareInfo;
+	PNDIS_RESOURCE_LIST  			ResourceList;
+	PCM_PARTIAL_RESOURCE_DESCRIPTOR	Resource;
+	NDIS_STATUS						Status;
+	UINT							c;
+	UINT							Temp;
+
+	//
+	//	Allocate memory for the pci common config space.
+	//
+	ALLOCATE_MEMORY(
+		&Status,
+		&pHwInfo->PciCommonConfig,
+		PCI_COMMON_HDR_LENGTH);
+	if (NULL == pHwInfo->PciCommonConfig)
+	{
+		DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+			("aic5900ReadPciConfiguration() failed to allocate memory for PCI Common Config.\n"));
+
+		return(NDIS_STATUS_RESOURCES);
+	}
+
+	PciCommonConfig = pHwInfo->PciCommonConfig;
+
+	//
+	//	Read the board id.  This is a combination of the vendor id and
+	//	the device id.
+	//
+	Temp = NdisReadPciSlotInformation(
+				pAdapter->MiniportAdapterHandle,
+				pHwInfo->SlotNumber,
+				0,
+				PciCommonConfig,
+				PCI_COMMON_HDR_LENGTH);
+	if (Temp != PCI_COMMON_HDR_LENGTH)
+	{
+		DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+			("Unable to read PCI configuration header\n"));
+
+		return(NDIS_STATUS_FAILURE);
+	}
+
+	//
+	//	Verify vendor & device id's.
+	//
+	if ((ADAPTEC_PCI_VENDOR_ID != PciCommonConfig->VendorID) ||
+		(AIC5900_PCI_DEVICE_ID != PciCommonConfig->DeviceID))
+	{
+		return(NDIS_STATUS_FAILURE);
+	}
+
+	//
+	//	Set the command word in pci space.
+	//
+	PciCommonConfig->Command = 	PCI_ENABLE_MEMORY_SPACE |
+								PCI_ENABLE_BUS_MASTER |
+								PCI_ENABLE_WRITE_AND_INVALIDATE |
+								PCI_ENABLE_SERR;
+
+	NdisWritePciSlotInformation(
+		pAdapter->MiniportAdapterHandle,
+		pHwInfo->SlotNumber,
+		FIELD_OFFSET(PCI_COMMON_CONFIG, Command),
+		&PciCommonConfig->Command,
+		sizeof(PciCommonConfig->Command));
+
+	NdisReadPciSlotInformation(
+		pAdapter->MiniportAdapterHandle,
+		pHwInfo->SlotNumber,
+		0,
+		PciCommonConfig,
+		PCI_COMMON_HDR_LENGTH);
+
+	PciCommonConfig->u.type0.BaseAddresses[0] &= 0xFFFFFFF0;
+
+	//
+	//	For noisy debug dump what we find in the PCI space.
+	//
+	dbgDumpPciCommonConfig(PciCommonConfig);
+
+	//
+	//	Assign the pci resources.
+	//
+	Status = NdisMPciAssignResources(
+				pAdapter->MiniportAdapterHandle,
+				pHwInfo->SlotNumber,
+				&ResourceList);
+	if (NDIS_STATUS_SUCCESS != Status)
+	{
+		DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+			("NdisMPciAssignResoures() failed: 0x%x\n", Status));
+
+		return(Status);
+	}
+
+	//
+	//	Walk the resource list to get the adapters configuration
+	//	information.
+	//
+	for (c = 0; c < ResourceList->Count; c++)
+	{
+		Resource = &ResourceList->PartialDescriptors[c];
+		switch (Resource->Type)
+		{
+			case CmResourceTypeInterrupt:
+				//
+				//	Save the interrupt number with our adapter block.
+				//
+				pHwInfo->InterruptLevel = Resource->u.Interrupt.Level;
+				pHwInfo->InterruptVector = Resource->u.Interrupt.Vector;
+
+				DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
+					("Configured to use interrupt Level: %u interrupt vector: %u\n", pHwInfo->InterruptLevel, pHwInfo->InterruptVector));
+
+				break;
+
+			case CmResourceTypeMemory:
+
+				//
+				//	Save the memory mapped base physical address and it's length.
+				//
+				pHwInfo->PhysicalIoSpace = Resource->u.Memory.Start;
+				pHwInfo->IoSpaceLength = Resource->u.Memory.Length;
+
+				DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
+					("Configured to use mapped memory memory 0x%x:0x%x of length 0x%x\n",
+						NdisGetPhysicalAddressHigh(pHwInfo->PhysicalIoSpace),
+						NdisGetPhysicalAddressLow(pHwInfo->PhysicalIoSpace),
+						pHwInfo->IoSpaceLength));
+
+				break;
+
+			case CmResourceTypePort:
+
+				//
+				//	Save the port.
+				//
+				pHwInfo->InitialPort = NdisGetPhysicalAddressLow(Resource->u.Port.Start);
+				pHwInfo->NumberOfPorts = Resource->u.Port.Length;
+
+				DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
+					("Configured to use port memory 0x%x of length 0x%x\n",
+						pHwInfo->InitialPort,
+						pHwInfo->NumberOfPorts));
+
+				break;
+		}
+	}
+
+	return(NDIS_STATUS_SUCCESS);
+}
+
+NDIS_STATUS
+aic5900GetNicModelNumberFromString(
+	IN	PHARDWARE_INFO	pHwInfo
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	ULONG		NicModel;
+	NDIS_STATUS	Status = NDIS_STATUS_SUCCESS;
+
+	AIC_ULONG_TO_ULONG(&NicModel, (PULONG)(&pHwInfo->FCodeImage->Model[5]));
+
+	//
+	//	Compare the second DWORD in the NicModelString
+	//
+	switch (NicModel)
+	{
+		case '5910':
+			pHwInfo->NicModelNumber = ANA_5910;
+
+			//
+			//	This is a 25Mbps adapter and has a 16MHz cell clock.
+			//
+			pHwInfo->CellClockRate = CELL_CLOCK_16MHZ;
+
+			break;
+
+		case '5930':
+			pHwInfo->NicModelNumber = ANA_5930;
+
+			//
+			//	This is a 155Mbps adapter and has a 25MHz cell clock.
+			//
+			pHwInfo->CellClockRate = CELL_CLOCK_25MHZ;
+
+			break;
+
+		case '5940':
+			pHwInfo->NicModelNumber = ANA_5940;
+
+			//
+			//	This is a 155Mbps adapter and has a 25MHz cell clock.
+			//
+			pHwInfo->CellClockRate = CELL_CLOCK_25MHZ;
+
+			break;
+
+		default:
+
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Invalid NIC Model String!\n"));
+
+			pHwInfo->NicModelNumber = ANA_INVALID;
+
+			Status = NDIS_STATUS_FAILURE;
+			break;
+	}
+
+	return(Status);
+}
+
+
+NDIS_STATUS
+aic5900ReadEepromInformation(
+	IN	PADAPTER_BLOCK	pAdapter
+	)
+/*++
+
+Routine Description:
+
+	This routine will map the EEPROM address into memory and read the offsets for the other
+	information that will be needed.
+
+Arguments:
+
+	pAdapter	-	Pointer to the adapter block to save the information.
+
+Return Value:
+
+	NDIS_STATUS_SUCCESS if everthing went ok.
+	NDIS_STATUS_FAILURE otherwise.
+
+--*/
+{
+	NDIS_PHYSICAL_ADDRESS	PhysicalAddress;
+	NDIS_STATUS				Status;
+	PHARDWARE_INFO			pHwInfo;
+
+	PPCI_FCODE_IMAGE		pFCode;
+	PPCI_FCODE_IMAGE		pFCodeImage;
+
+	PUCHAR					EepromBase = NULL;
+	UCHAR					HighByte;
+	UCHAR					LowByte;
+
+	USHORT					FCodeImageOffset;
+	ULONG					FCodeName;
+
+	do
+	{
+		//
+		//	Initialize the hardware info.
+		//
+		pHwInfo = pAdapter->HardwareInfo;
+
+		//
+		//	Map the first part of the EEPROM to read the
+		//	configuration information.
+		//
+		PhysicalAddress = pHwInfo->PhysicalIoSpace;
+
+		Status = NdisMMapIoSpace(
+					&EepromBase,
+					pAdapter->MiniportAdapterHandle,
+					PhysicalAddress,
+					FCODE_SIZE);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Failed to map the PCI FCode I/O space into memory\n"));
+			break;
+		}
+	
+		//
+		//	Get the offset to the Fcode image.
+		//
+		EEPROM_READ_UCHAR(EepromBase + 3, &HighByte);
+		EEPROM_READ_UCHAR(EepromBase + 2, &LowByte);
+		FCodeImageOffset = (USHORT)((HighByte << 8) + LowByte);
+
+		if (0xFFFF == FCodeImageOffset)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Invalid data read from the EEPROM.\n"));
+			Status = NDIS_STATUS_ADAPTER_NOT_FOUND;
+			break;
+		}
+
+		pFCode = (PPCI_FCODE_IMAGE)(EepromBase + FCodeImageOffset);
+
+		ALLOCATE_MEMORY(&Status, &pHwInfo->FCodeImage, FCODE_SIZE);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Failed to allocate memory for the eeprom image\n"));
+			break;
+		}
+
+		EEPROM_READ_BUFFER(pHwInfo->FCodeImage, pFCode, FCODE_SIZE);
+
+		pFCodeImage = pHwInfo->FCodeImage;
+
+		//
+		//	For debug this will get dumped.
+		//
+		dbgDumpPciFCodeImage(pFCodeImage);
+
+		//
+		//	Check the name parameter in the fcode image.
+		//	We add 1 since this name is in PASCAL format (the first byte
+		//	is the length of the string)....
+		//
+		AIC_ULONG_TO_ULONG(&FCodeName, (PULONG)(&pFCodeImage->Name[1]));
+		if (FCodeName != FCODE_NAME)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Invalid name in FCode Image\n"));
+
+			Status = NDIS_STATUS_ADAPTER_NOT_FOUND;
+			break;
+		}
+
+		//
+		//	Get the model number for the NIC.
+		//
+		Status = aic5900GetNicModelNumberFromString(pHwInfo);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			Status = NDIS_STATUS_ADAPTER_NOT_FOUND;
+			break;
+		}
+
+		//
+		//	Get the ROM version number.
+		//
+		AIC_ULONG_TO_ULONG(&pHwInfo->RomVersionNumber, &pFCodeImage->RomVersionNumber);
+
+		//
+		//	Get EPROM offset and size and map in.
+		//
+		AIC_ULONG_TO_ULONG(&pHwInfo->rEpromOffset, &pFCodeImage->roEpromOffset);
+		AIC_ULONG_TO_ULONG(&pHwInfo->rEpromSize, &pFCodeImage->roEpromSize);
+
+		NdisSetPhysicalAddressLow(
+			PhysicalAddress,
+			NdisGetPhysicalAddressLow(pHwInfo->PhysicalIoSpace) +
+			pHwInfo->rEpromOffset);
+
+		Status = NdisMMapIoSpace(
+					&pHwInfo->rEprom,
+					pAdapter->MiniportAdapterHandle,
+					PhysicalAddress,
+					pHwInfo->rEpromSize);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			break;
+		}
+
+		//
+		//	Get R/W EPROM offset and size and map in.
+		//
+		AIC_ULONG_TO_ULONG(&pHwInfo->rwEpromOffset, &pFCodeImage->rwEpromOffset);
+		AIC_ULONG_TO_ULONG(&pHwInfo->rwEpromSize, &pFCodeImage->rwEpromSize);
+
+		NdisSetPhysicalAddressLow(
+			PhysicalAddress,
+			NdisGetPhysicalAddressLow(pHwInfo->PhysicalIoSpace) +
+			pHwInfo->rwEpromOffset);
+
+		Status = NdisMMapIoSpace(
+					&pHwInfo->rwEprom,
+					pAdapter->MiniportAdapterHandle,
+					PhysicalAddress,
+					pHwInfo->rwEpromSize);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			break;
+		}
+
+		//
+		//	Get PHY offset and size and map in.
+		//
+		AIC_ULONG_TO_ULONG(&pHwInfo->PhyOffset, &pFCodeImage->PhyOffset);
+		AIC_ULONG_TO_ULONG(&pHwInfo->PhySize, &pFCodeImage->PhySize);
+
+		NdisSetPhysicalAddressLow(
+			PhysicalAddress,
+			NdisGetPhysicalAddressLow(pHwInfo->PhysicalIoSpace) +
+			pHwInfo->PhyOffset);
+
+		Status = NdisMMapIoSpace(
+					(PVOID *)&pHwInfo->Phy,
+					pAdapter->MiniportAdapterHandle,
+					PhysicalAddress,
+					pHwInfo->PhySize);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			break;
+		}
+
+		//
+		//	Get EXTERNAL offset and size and map in.
+		//
+		AIC_ULONG_TO_ULONG(&pHwInfo->ExternalOffset, &pFCodeImage->ExternalOffset);
+		AIC_ULONG_TO_ULONG(&pHwInfo->ExternalSize, &pFCodeImage->ExternalSize);
+
+		NdisSetPhysicalAddressLow(
+			PhysicalAddress,
+			NdisGetPhysicalAddressLow(pHwInfo->PhysicalIoSpace) +
+			pHwInfo->ExternalOffset);
+
+		Status = NdisMMapIoSpace(
+					&pHwInfo->External,
+					pAdapter->MiniportAdapterHandle,
+					PhysicalAddress,
+					pHwInfo->ExternalSize);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			break;
+		}
+
+		//
+		//	Get SAR offset and size and map in.
+		//
+		AIC_ULONG_TO_ULONG(&pHwInfo->MidwayOffset, &pFCodeImage->SarOffset);
+		AIC_ULONG_TO_ULONG(&pHwInfo->MidwaySize, &pFCodeImage->SarSize);
+
+		NdisSetPhysicalAddressLow(
+			PhysicalAddress,
+			NdisGetPhysicalAddressLow(pHwInfo->PhysicalIoSpace) +
+			pHwInfo->MidwayOffset);
+
+		Status = NdisMMapIoSpace(
+					(PVOID *)&pHwInfo->Midway,
+					pAdapter->MiniportAdapterHandle,
+					PhysicalAddress,
+					pHwInfo->MidwaySize);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			break;
+		}
+
+		//
+		//	Get PCI Config offset and size and map in.
+		//
+		AIC_ULONG_TO_ULONG(&pHwInfo->PciCfgOffset, &pFCodeImage->PciConfigOffset);
+		AIC_ULONG_TO_ULONG(&pHwInfo->PciCfgSize, &pFCodeImage->PciConfigSize);
+
+		NdisSetPhysicalAddressLow(
+			PhysicalAddress,
+			NdisGetPhysicalAddressLow(pHwInfo->PhysicalIoSpace) +
+			pHwInfo->PciCfgOffset);
+
+		Status = NdisMMapIoSpace(
+					(PVOID *)&pHwInfo->PciConfigSpace,
+					pAdapter->MiniportAdapterHandle,
+					PhysicalAddress,
+					pHwInfo->PciCfgSize);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			break;
+		}
+
+		//
+		//	Get SAR RAM offset and size and map in.
+		//
+		AIC_ULONG_TO_ULONG(&pHwInfo->SarRamOffset, &pFCodeImage->SarMemOffset);
+		AIC_ULONG_TO_ULONG(&pHwInfo->SarRamSize, &pFCodeImage->SarMemSize);
+
+		NdisSetPhysicalAddressLow(
+			PhysicalAddress,
+			NdisGetPhysicalAddressLow(pHwInfo->PhysicalIoSpace) +
+			pHwInfo->SarRamOffset);
+
+		Status = NdisMMapIoSpace(
+					(PVOID *)&pHwInfo->SarRam,
+					pAdapter->MiniportAdapterHandle,
+					PhysicalAddress,
+					pHwInfo->SarRamSize);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			break;
+		}
+
+		//
+		//	Read in the manufacturer address for the nic.
+		//
+		EEPROM_READ_BUFFER(
+			pHwInfo->PermanentAddress,
+			(((PUCHAR)pHwInfo->rEprom) + pHwInfo->rEpromSize) - sizeof(EEPROM_MANUFACTURER_INFO),
+			ATM_ADDRESS_LENGTH);
+
+		//
+		//	Save the permanent address in the station address by default.
+		//
+		NdisMoveMemory(
+			pHwInfo->StationAddress,
+			pHwInfo->PermanentAddress,
+			ATM_ADDRESS_LENGTH);
+		
+		dbgDumpHardwareInformation(pHwInfo);
+	} while (FALSE);
+
+	if (EepromBase != NULL)
+	{
+		NdisMUnmapIoSpace(
+			pAdapter->MiniportAdapterHandle,
+			(PVOID)EepromBase,
+			FCODE_SIZE);
+	}
+
+	return(Status);
+}
+
+VOID
+aic5900FreeResources(
+	IN PADAPTER_BLOCK pAdapter
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	PHARDWARE_INFO	pHwInfo;
+	PVC_BLOCK		pVc;
+	PLIST_ENTRY		Link;
+
+	if (NULL != pAdapter)
+	{
+		if (NULL != pAdapter->HardwareInfo)
+		{
+			pHwInfo = pAdapter->HardwareInfo;
+
+			if (NULL != pHwInfo->PciCommonConfig)
+			{
+				FREE_MEMORY(pHwInfo->PciCommonConfig, PCI_COMMON_HDR_LENGTH);
+			}
+
+			if (NULL != pHwInfo->PortOffset)
+			{
+				NdisMDeregisterIoPortRange(
+					pAdapter->MiniportAdapterHandle,
+					pHwInfo->InitialPort,
+					pHwInfo->NumberOfPorts,
+					pHwInfo->PortOffset);
+			}
+		
+			if (NULL != pHwInfo->rEprom)
+			{
+				NdisMUnmapIoSpace(
+					pAdapter->MiniportAdapterHandle,
+					pHwInfo->rEprom,
+					pHwInfo->rEpromSize);
+			}
+		
+			if (NULL != pHwInfo->rwEprom)
+			{
+				NdisMUnmapIoSpace(
+					pAdapter->MiniportAdapterHandle,
+					pHwInfo->rwEprom,
+					pHwInfo->rwEpromSize);
+			}
+		
+			if (NULL != pHwInfo->Phy)
+			{
+				NdisMUnmapIoSpace(
+					pAdapter->MiniportAdapterHandle,
+					pHwInfo->Phy,
+					pHwInfo->PhySize);
+			}
+		
+			if (NULL != pHwInfo->External)
+			{
+				NdisMUnmapIoSpace(
+					pAdapter->MiniportAdapterHandle,
+					pHwInfo->External,
+					pHwInfo->ExternalSize);
+			}
+		
+			if (NULL != pHwInfo->Midway)
+			{
+				NdisMUnmapIoSpace(
+					pAdapter->MiniportAdapterHandle,
+					pHwInfo->Midway,
+					pHwInfo->MidwaySize);
+			}
+		
+			if (NULL != pHwInfo->PciConfigSpace)
+			{
+				NdisMUnmapIoSpace(
+					pAdapter->MiniportAdapterHandle,
+					pHwInfo->PciConfigSpace,
+					pHwInfo->PciCfgSize);
+			}
+		
+			if (NULL != pHwInfo->SarRam)
+			{
+				NdisMUnmapIoSpace(
+					pAdapter->MiniportAdapterHandle,
+					(PVOID)pHwInfo->SarRam,
+					pHwInfo->SarRamSize);
+			}
+		
+			if (NULL != pHwInfo->FCodeImage)
+			{
+				FREE_MEMORY(pHwInfo->FCodeImage, FCODE_SIZE);
+			}
+
+			if (HW_TEST_FLAG(pHwInfo, fHARDWARE_INFO_INTERRUPT_REGISTERED))
+			{
+				NdisMDeregisterInterrupt(&pHwInfo->Interrupt);
+			}
+
+			//
+			//	Free the spin lock for the hardware information.
+			//
+			NdisFreeSpinLock(&pHwInfo->Lock);
+
+			//
+			//	Free the memory used for the hardware information.
+			//
+			FREE_MEMORY(pHwInfo, sizeof(HARDWARE_INFO));
+		}
+
+		///
+		//	Clean up our list of active VCs.
+		///
+		while (!IsListEmpty(&pAdapter->ActiveVcList))
+		{
+			//
+			//	Remove the VC from the list, deactivate it and delete it.
+			//
+			Link = RemoveHeadList(&pAdapter->ActiveVcList);
+			pVc = CONTAINING_RECORD(Link, VC_BLOCK, Link);
+			Aic5900DeactivateVc((NDIS_HANDLE)pVc);
+			Aic5900DeleteVc((NDIS_HANDLE)pVc);
+		}
+
+		//
+		//	Walk our list of inactive VCs.
+		//
+		while (!IsListEmpty(&pAdapter->InactiveVcList))
+		{
+			//
+			//	Remove the VC from the list and delete it.
+			//
+			Link = RemoveHeadList(&pAdapter->InactiveVcList);
+			pVc = CONTAINING_RECORD(Link, VC_BLOCK, Link);
+			Aic5900DeleteVc((NDIS_HANDLE)pVc);
+		}
+
+		//
+		//	Free up the spin lock for the adapter block.
+		//
+		NdisFreeSpinLock(&pAdapter->Lock);
+
+		//
+		//	Free the memory allocated for the adapter block.
+		//
+		FREE_MEMORY(pAdapter, sizeof(ADAPTER_BLOCK));
+	}
+}
+
+
+NDIS_STATUS
+aic5900InitPciRegisters(
+	IN	PADAPTER_BLOCK	pAdapter
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	PHARDWARE_INFO					pHwInfo = pAdapter->HardwareInfo;
+	PCI_DEVICE_CONFIG				regConfig;
+	PCI_DEVICE_ENABLE_PCI_INTERRUPT	regEnableInt;
+	PCI_DEVICE_DMA_CONTROL			regDmaControl;
+
+	//
+	//	Reset the ORION
+	//
+	GET_PCI_DEV_CFG(pHwInfo, &regConfig);
+	regConfig.SoftwareReset = 1;
+	SET_PCI_DEV_CFG(pHwInfo, regConfig.reg);
+
+	//
+	//	Program the interrupt enable register.
+	//
+	GET_PCI_DEV_ENABLE_INT(pHwInfo, &regEnableInt);
+	regEnableInt.EnableDpeInt = 0;
+	regEnableInt.EnableSseInt = 1;
+	regEnableInt.EnableStaInt = 1;
+	regEnableInt.EnableRmaInt = 1;
+	regEnableInt.EnableRtaInt = 1;
+	regEnableInt.EnableDprInt = 1;
+	SET_PCI_DEV_ENABLE_INT(pHwInfo, regEnableInt.reg);
+
+	//
+	//	Program the PCI device config register.
+	//
+	GET_PCI_DEV_CFG(pHwInfo, &regConfig);
+	regConfig.MasterSwapBytes = 1;
+	regConfig.EnableInterrupt = 1;
+	SET_PCI_DEV_CFG(pHwInfo, regConfig.reg);
+
+	//
+	//	Program the DMA control register.
+	//
+	GET_PCI_DEV_DMA_CONTROL(pHwInfo, &regDmaControl);
+	regDmaControl.CacheThresholdEnable = 1;
+	SET_PCI_DEV_DMA_CONTROL(pHwInfo, regDmaControl.reg);
+
+	return(NDIS_STATUS_SUCCESS);
+}
+
+NDIS_STATUS
+aic5900InitPhyRegisters(
+	IN	PADAPTER_BLOCK	pAdapter
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	PHARDWARE_INFO	pHwInfo = pAdapter->HardwareInfo;
+	NDIS_STATUS	Status = NDIS_STATUS_SUCCESS;
+
+	switch (pAdapter->HardwareInfo->NicModelNumber)
+	{
+		case ANA_5910:
+
+			//
+			//	Reset the IBM TC and PDM chips.  The host can reset TC
+			//	and PDM chips by first writing a word to the Software Reset
+			//	register and then reading it back.
+			//
+			//	Reset clears the STATUS register and flushes the TC receive
+			//	FIFO.
+			//
+			SET_IBM_TC_SOFTWARE_RESET(pHwInfo, 0);
+
+			//
+			//	Enable TC overrun and cell error interrupts.
+			//
+			SET_IBM_TC_MASK(pHwInfo, 0x04);
+
+			break;
+
+		case ANA_5940:
+		case ANA_5930:
+
+			//
+			//	Set and clear the reset bit for the phy.
+			//
+			SET_SUNI_MASTER_RESET_IDEN(pHwInfo, fSUNI_MRI_RESET);
+			SET_SUNI_MASTER_RESET_IDEN(pHwInfo, 0);
+
+			//
+			//	Clear the SUNI test mode.
+			//
+			SET_SUNI_MASTER_TEST(pHwInfo, 0);
+
+			//
+			//	Enable SUNI RACP interrupts.
+			//
+			SET_SUNI_RACP_INT_ENABLE_STATUS(pHwInfo, (fSUNI_RACP_IES_FIFOE | fSUNI_RACP_IES_HCSE));
+
+			break;
+
+		default:
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
+					("aic5900InitPhyRegisters: Unknown adapter model 0x%x\n", pAdapter->HardwareInfo->NicModelNumber));
+
+			Status = NDIS_STATUS_ADAPTER_NOT_FOUND;
+
+			break;
+	}
+
+	return(Status);
+}
+
+NDIS_STATUS
+aic5900InitSarRegisters(
+	IN PADAPTER_BLOCK pAdapter
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	NDIS_STATUS			Status = NDIS_STATUS_SUCCESS;
+	PSAR_INFO			pSar;
+	PHARDWARE_INFO		pHwInfo = pAdapter->HardwareInfo;
+	PXMIT_SEG_CHANNEL	pCurrent;
+	ULONG				RamOffset;
+	UINT				c;
+
+	do
+	{
+		//
+		//	Allocate memory for the sar.
+		//
+		ALLOCATE_MEMORY(&Status, &pSar, sizeof(SAR_INFO));
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			break;
+		}
+	
+		ZERO_MEMORY(pSar, sizeof(SAR_INFO));
+	
+		NdisAllocateSpinLock(&pSar->lockFreeXmitSegment);
+	
+		//
+		//	Initialize the VCI table, DMA receive and transmit queues,
+		//	the service list, and everything else in the SAR ram.
+		//
+		for (c = 0; c < pHwInfo->SarRamSize / 4; c++)
+		{
+			NdisWriteRegisterUlong(pHwInfo->SarRam + c, 0);
+		}
+	
+		//
+		//	Initialize the memory manager for our sar ram....
+		//
+		Status = Aic5900InitializeRamInfo(&pHwInfo->hRamInfo, pHwInfo->SarRamSize);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Unable to initialize the memory manager for the adapter memory\n"));
+
+			break;
+		}
+	
+		//
+		//	Allocate memory for the VCI table.
+		//	NOTE:
+		//		We don't need to save the ram offset since this is always
+		//		at offset 0.
+		//
+		Status = Aic5900AllocateRam(
+					&RamOffset,
+					pHwInfo->hRamInfo,
+					sizeof(MIDWAY_VCI_TABLE_ENTRY) * MAX_VCS);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_VC, DBG_LEVEL_ERR,
+				("Unable to allocate the VCI table in adapter ram\n"));
+
+			break;
+		}
+	
+		ASSERT(MIDWAY_VCI_TABLE_OFFSET == RamOffset);
+
+		//
+		//	Allocate memory for the receive DMA queue.
+		//	NOTE:
+		//		We don't need to save the RAM offset since this is always at
+		//		offset 0x4000.
+		//
+		Status = Aic5900AllocateRam(
+					&RamOffset,
+					pHwInfo->hRamInfo,
+					sizeof(MIDWAY_DMA_DESC) * MIDWAY_DMA_QUEUE_SIZE);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Unable to allocate the receive queue from the adapter ram\n"));
+
+			break;
+		}
+
+		ASSERT(MIDWAY_RECEIVE_DMA_QUEUE_OFFSET == RamOffset);
+
+		//
+		//	Allocate memory for the transmit DMA queue.
+		//	NOTE:
+		//		We don't need to save the RAM offset since this is always at
+		//		offset 0x5000.
+		//
+		Status = Aic5900AllocateRam(
+					&RamOffset,
+					pHwInfo->hRamInfo,
+					sizeof(MIDWAY_DMA_DESC) * MIDWAY_DMA_QUEUE_SIZE);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Unable to allocate the transmit queue from the adapter ram\n"));
+
+			break;
+		}
+
+		ASSERT(MIDWAY_TRANSMIT_DMA_QUEUE_OFFSET == RamOffset);
+
+		//
+		//	Allocate memory for the service queue.
+		//	NOTE:
+		//		We don't need to save the RAM offset since this is always at
+		//		offset 0x6000.
+		//
+		Status = Aic5900AllocateRam(
+					&RamOffset,
+					pHwInfo->hRamInfo,
+					sizeof(MIDWAY_SERVICE_LIST) * MIDWAY_SERVICE_QUEUE_SIZE);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Unable to allocate the service queue\n"));
+
+			break;
+		}
+
+		ASSERT(MIDWAY_SERVICE_QUEUE_OFFSET == RamOffset);
+	
+		//
+		//	Get a block of nic ram for the transmit channel.
+		//
+		Status = Aic5900AllocateRam(&RamOffset, pHwInfo->hRamInfo, BLOCK_16K);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Unable to allocate adapter memory for the UBR channel\n"));
+
+			break;
+		}
+
+		//
+		//	Setup the UBR (best effort) channel.
+		//
+		pCurrent = &pSar->XmitSegChannel[0];
+		pSar->ubrXmitChannel = pCurrent;
+	
+		NdisZeroMemory(pCurrent, sizeof(XMIT_SEG_CHANNEL));
+	
+		NdisAllocateSpinLock(&pCurrent->lock);
+		pCurrent->Adapter = pAdapter;
+		pCurrent->MidwayChannelNumber = MIDWAY_XMIT_SEG_CHANNEL_UBR;
+
+		pCurrent->MidwayInitRegs.XmitPlace.Size =
+					CONVERT_BYTE_SIZE_TO_MIDWAY_SIZE(BLOCK_16K / 4);
+		pCurrent->MidwayInitRegs.XmitPlace.Location =
+					CONVERT_BYTE_OFFSET_TO_MIDWAY_LOCATION(RamOffset);
+		pCurrent->MidwayInitRegs.XmitReadPointer.Register = 0;
+		pCurrent->MidwayInitRegs.XmitDescriptorStart.Register = 0;
+	
+		pCurrent->MidwayTransmitRegs =
+			&pHwInfo->Midway->TransmitRegisters[MIDWAY_XMIT_SEG_CHANNEL_UBR];
+	
+		pCurrent->SegmentSize = BLOCK_SIZE_16k / 4;
+		pCurrent->Segment = (HWUL *)&pHwInfo->SarRam[RamOffset / 4];
+		pCurrent->SegmentReadPointer = 0;
+		pCurrent->SegmentWritePointer = 0;
+		pCurrent->SegmentRoom = BLOCK_SIZE_16k / 4;
+		pCurrent->XmitPduBytes = 0;
+	
+		InitializeListHead(&pCurrent->SegmentWaitQ);
+		InitializeListHead(&pCurrent->TransmitWaitQ);
+	
+		for (c = 1, pCurrent = &pSar->XmitSegChannel[c];
+			 c < MIDWAY_MAX_SEGMENT_CHANNELS;
+			 c++, pCurrent++)
+		{
+			NdisZeroMemory(pCurrent, sizeof(XMIT_SEG_CHANNEL));
+			NdisAllocateSpinLock(&pCurrent->lock);
+	
+			pCurrent->Adapter = pAdapter;
+			pCurrent->MidwayChannelNumber = c;
+	
+			//
+			//	Place the segment channel on the free queue.
+			//	
+			pCurrent->Next = pSar->FreeXmitSegChannel;
+			pSar->FreeXmitSegChannel = pCurrent;
+	
+			//
+			//	Get a pointer to the midway transmit registers.
+			//
+			pCurrent->MidwayTransmitRegs =
+						&pHwInfo->Midway->TransmitRegisters[c];
+	
+			//
+			//	Initialize the queues.
+			//
+			InitializeListHead(&pCurrent->SegmentWaitQ);
+			InitializeListHead(&pCurrent->TransmitWaitQ);
+		}
+	
+		//
+		//	Initialize the Midway Master Control register.
+		//
+		pSar->MidwayMasterControl = (MID_REG_MC_S_DMA_ENABLE |
+									 MID_REG_MC_S_XMT_ENABLE |
+									 MID_REG_MC_S_RCV_ENABLE |
+									 MID_REG_MC_S_XMT_LOCK_MODE);
+		pHwInfo->Midway->MCS = pSar->MidwayMasterControl;
+	
+		//
+		//	Initialize the UBR transmit channel.
+		//
+		pHwInfo->Midway->TransmitRegisters[MIDWAY_XMIT_SEG_CHANNEL_UBR].XmitPlace.Register =
+			pSar->ubrXmitChannel->MidwayInitRegs.XmitPlace.Register;
+	
+		pHwInfo->Midway->TransmitRegisters[MIDWAY_XMIT_SEG_CHANNEL_UBR].XmitReadPointer.Register =
+			pSar->ubrXmitChannel->MidwayInitRegs.XmitReadPointer.Register;
+	
+		pHwInfo->Midway->TransmitRegisters[MIDWAY_XMIT_SEG_CHANNEL_UBR].XmitDescriptorStart.Register =
+			pSar->ubrXmitChannel->MidwayInitRegs.XmitDescriptorStart.Register;
+	
+		pHwInfo->InterruptMask = MID_REG_INT_PCI 				|
+								 MID_REG_INT_XMT_COMPLETE_7 	|
+								 MID_REG_INT_XMT_COMPLETE_6 	|
+								 MID_REG_INT_XMT_COMPLETE_5 	|
+								 MID_REG_INT_XMT_COMPLETE_4 	|
+								 MID_REG_INT_XMT_COMPLETE_3 	|
+								 MID_REG_INT_XMT_COMPLETE_2 	|
+								 MID_REG_INT_XMT_COMPLETE_1 	|
+								 MID_REG_INT_XMT_COMPLETE_0 	|
+								 MID_REG_INT_XMT_DMA_OVFL 		|
+								 MID_REG_INT_XMT_IDEN_MISMTCH 	|
+								 MID_REG_INT_DMA_ERR_ACK 		|
+								 MID_REG_INT_RCV_DMA_COMPLETE 	|
+								 MID_REG_INT_XMT_DMA_COMPLETE 	|
+								 MID_REG_INT_SERVICE 			|
+								 MID_REG_INT_SUNI_INT;
+	
+		pHwInfo->Midway->IE = pHwInfo->InterruptMask;
+
+		Status = NDIS_STATUS_SUCCESS;
+	} while (FALSE);
+
+	//
+	//	If we failed somewhere above then we need to cleanup....
+	//
+	if (NDIS_STATUS_SUCCESS != Status)
+	{
+		if (NULL != pHwInfo->hRamInfo)
+		{
+			Aic5900UnloadRamInfo(pHwInfo->hRamInfo);
+		}
+	
+		if (NULL != pSar)
+		{
+			NdisFreeSpinLock(&pSar->lockFreeXmitSegment);
+			FREE_MEMORY(pSar, sizeof(SAR_INFO));
+		}
+	}
+
+	return(Status);
+}
+
+
+NDIS_STATUS
+Aic5900Initialize(
+	OUT	PNDIS_STATUS	OpenErrorStatus,
+	OUT PUINT			SelectedMediumIndex,
+	IN	PNDIS_MEDIUM	MediumArray,
+	IN	UINT			MediumArraySize,
+	IN	NDIS_HANDLE		MiniportAdapterHandle,
+	IN	NDIS_HANDLE		ConfigurationHandle
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	UINT							c;
+	PADAPTER_BLOCK					pAdapter;
+	PHARDWARE_INFO					pHwInfo;
+	NDIS_STATUS						Status;
+	PAIC5900_REGISTRY_PARAMETER		pRegistryParameter;
+
+	do
+	{
+		//
+		//	Initialize for clean-up.
+		//
+		pAdapter = NULL;
+
+		//
+		//	Do we support any of the given media types?
+		//
+		for (c = 0; c < MediumArraySize; c++)
+		{
+			if (MediumArray[c] == NdisMediumAtm)
+			{
+				break;
+			}
+		}
+	
+		//
+		//	If we went through the whole media list without finding
+		//	a supported media type let the wrapper know.
+		//
+		if (c == MediumArraySize)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Media not supported by version of ndis\n"));
+
+			Status = NDIS_STATUS_UNSUPPORTED_MEDIA;
+
+			break;
+		}
+	
+		*SelectedMediumIndex = c;
+
+		//
+		//	Allocate memory for the registry parameters.
+		//
+		ALLOCATE_MEMORY(
+			&Status,
+			&pRegistryParameter,
+			sizeof(AIC5900_REGISTRY_PARAMETER) * Aic5900MaxRegistryEntry);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_COMP_ERR,
+				("Unable to allocate memroy for the registry parameters\n"));
+
+			break;
+		}
+	
+		ZERO_MEMORY(
+			pRegistryParameter,
+			sizeof(AIC5900_REGISTRY_PARAMETER) * Aic5900MaxRegistryEntry);
+
+		//
+		//	Fill in some default registry values.
+		//
+		pRegistryParameter[Aic5900VcHashTableSize].Value = 13;
+
+		//
+		//	Read our parameters out of the registry.
+		//
+		Status = aic5900ReadConfigurationInformation(
+						pRegistryParameter,
+						ConfigurationHandle);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Failed to read the configuration information from the registry\n"));
+
+			break;
+		}
+
+		//
+		//	Allocate memory for our adapter block and initialize it.
+		//
+		ALLOCATE_MEMORY(
+			&Status,
+			&pAdapter,
+			sizeof(ADAPTER_BLOCK) +
+			(pRegistryParameter[Aic5900VcHashTableSize].Value * sizeof(ULONG)));
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Failed to allocate memory for the adapter block\n"));
+			break;
+		}
+
+		ZERO_MEMORY(pAdapter, sizeof(ADAPTER_BLOCK));
+	
+		pAdapter->MiniportAdapterHandle = MiniportAdapterHandle;
+
+		NdisAllocateSpinLock(&pAdapter->Lock);
+
+		//
+		//	Spin lock and other odd allocations/initializations.
+		//
+		InitializeListHead(&pAdapter->ActiveVcList);
+		InitializeListHead(&pAdapter->InactiveVcList);
+
+		//
+		//	Allocate memory for the hardware information.
+		//
+		ALLOCATE_MEMORY(&Status, &pAdapter->HardwareInfo, sizeof(HARDWARE_INFO));
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Failed to allocate memory for the hardware information\n"));
+
+			break;
+		}
+
+		ZERO_MEMORY(pAdapter->HardwareInfo, sizeof(HARDWARE_INFO));
+		
+		pHwInfo = pAdapter->HardwareInfo;
+
+		NdisAllocateSpinLock(&pHwInfo->Lock);
+
+		//
+		//	Get the registry parameters.
+		//
+		ASSERT(pRegistryParameter[Aic5900BusNumber].fPresent);
+		pHwInfo->BusNumber = pRegistryParameter[Aic5900BusNumber].Value;
+
+		ASSERT(pRegistryParameter[Aic5900SlotNumber].fPresent);
+		pHwInfo->SlotNumber = pRegistryParameter[Aic5900SlotNumber].Value;
+
+		//
+		//	Set the atributes for the adapter.
+		//
+		NdisMSetAttributes(
+			MiniportAdapterHandle,
+			(NDIS_HANDLE)pAdapter,
+			TRUE,
+			NdisInterfacePci);
+
+		//
+		//	Assign the PCI resources.
+		//
+		Status = aic5900ReadPciConfiguration(pAdapter);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Failed to read the PCI configuration information\n"));
+			break;
+		}
+
+		//
+		//	Register the Port addresses.
+		//
+		Status = NdisMRegisterIoPortRange(
+					&pHwInfo->PortOffset,
+					pAdapter->MiniportAdapterHandle,
+					pHwInfo->InitialPort,
+					pHwInfo->NumberOfPorts);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Failed to register the I/O port range\n"));
+			break;
+		}
+
+		//
+		//	Get the EEPROM parameters
+		//
+		Status = aic5900ReadEepromInformation(pAdapter);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Failed to read the EEPROM information from the adapter\n"));
+			break;										
+		}
+
+		//
+		//	Register the interrupt.
+		//
+		Status = NdisMRegisterInterrupt(
+					&pHwInfo->Interrupt,
+					pAdapter->MiniportAdapterHandle,
+					pHwInfo->InterruptVector,
+					pHwInfo->InterruptLevel,
+					TRUE,
+					TRUE,
+					NdisInterruptLevelSensitive);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+				("Failed to register the interrupt with ndis\n"));
+			break;
+		}
+
+		//
+		//	Initialize the PCI device/configuration registers.
+		//
+		Status = aic5900InitPciRegisters(pAdapter);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+					("Failed to initialize the PCI Device/Configuration registers\n"));
+
+			break;
+		}
+
+		Status = aic5900InitPhyRegisters(pAdapter);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+					("Failed to initialize the PHY registers\n"));
+
+			break;
+		}
+
+		//
+		//	Initialize the SAR
+		//
+		Status = aic5900InitSarRegisters(pAdapter);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
+					("Failed to initialize the SAR registers\n"));
+
+			break;
+		}
+
+		//
+		//	Return success.
+		//
+		Status = NDIS_STATUS_SUCCESS;
+
+	} while (FALSE);
+
+	//
+	//	Should we clean up?
+	//
+	if (NDIS_STATUS_SUCCESS != Status)
+	{
+		aic5900FreeResources(pAdapter);
+	}
+
+	return(Status);
+}
+	
diff --git a/private/ntos/ndis/aic5900/int.c b/private/ntos/ndis/aic5900/int.c
new file mode 100644
index 000000000..d01953356
--- /dev/null
+++ b/private/ntos/ndis/aic5900/int.c
@@ -0,0 +1,100 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\int.c
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#include "aic5900.h"
+
+#define	MODULE_NUMBER	MODULE_INT
+
+VOID
+Aic5900EnableInterrupt(
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	
+}
+
+VOID
+Aic5900DisableInterrupt(
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	
+}
+
+VOID
+Aic5900ISR(
+	OUT	PBOOLEAN	InterruptRecognized,
+	OUT	PBOOLEAN	QueueDpc,
+	IN	PVOID		Context
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	*InterruptRecognized = TRUE;
+	*QueueDpc = FALSE;
+}
+
+VOID
+Aic5900HandleInterrupt(
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	
+}
+
+
+
diff --git a/private/ntos/ndis/aic5900/makefile b/private/ntos/ndis/aic5900/makefile
new file mode 100644
index 000000000..6ee4f43fa
--- /dev/null
+++ b/private/ntos/ndis/aic5900/makefile
@@ -0,0 +1,6 @@
+#
+# DO NOT EDIT THIS FILE!!!  Edit .\sources. if you want to add a new source
+# file to this component.  This file merely indirects to the real make file
+# that is shared by all the components of NT OS/2
+#
+!INCLUDE $(NTMAKEENV)\makefile.def
diff --git a/private/ntos/ndis/aic5900/memmgr.h b/private/ntos/ndis/aic5900/memmgr.h
new file mode 100644
index 000000000..963503f6f
--- /dev/null
+++ b/private/ntos/ndis/aic5900/memmgr.h
@@ -0,0 +1,72 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\memmgr.h
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#ifndef __MEMMGR_H
+#define __MEMMGR_H
+
+//
+//	RAM memory block supported.
+//
+#define	BLOCK_1K		1024
+#define	BLOCK_2K		2048
+#define	BLOCK_4K		4096
+#define	BLOCK_8K		8192
+#define	BLOCK_16K		16384
+#define	BLOCK_32K		32768
+#define	BLOCK_64K		65536
+#define	BLOCK_128K		131072
+
+//
+//	One memory map range.
+//
+#define	MAP_RANGE		BLOCK_32K
+
+NDIS_STATUS
+Aic5900InitializeRamInfo(
+	OUT	NDIS_HANDLE	*hRamInfo,
+	IN	ULONG		MaxRamSize
+	);
+
+VOID
+Aic5900UnloadRamInfo(
+	IN	NDIS_HANDLE	hRamInfo
+	);
+
+NDIS_STATUS
+Aic5900AllocateRam(
+	OUT	PULONG		pRamOffset,
+	IN	NDIS_HANDLE	hRamInfo,
+	IN	ULONG		SizeNeeded
+	);
+
+VOID
+Aic5900FreeRam(
+	IN	NDIS_HANDLE	hRamInfo,
+	IN	ULONG		RamOffset,
+	IN	ULONG		RamSize
+	);
+
+
+
+
+#endif // __MEMMGR_H
diff --git a/private/ntos/ndis/aic5900/protos.h b/private/ntos/ndis/aic5900/protos.h
new file mode 100644
index 000000000..ca0c446ef
--- /dev/null
+++ b/private/ntos/ndis/aic5900/protos.h
@@ -0,0 +1,182 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\protos.h
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#ifndef __PROTOS_H
+#define __PROTOS_H
+
+NTSTATUS
+DriverEntry(
+	IN	PDRIVER_OBJECT	DriverObject,
+	IN	PUNICODE_STRING	RegistryPath
+	);
+
+NDIS_STATUS
+Aic5900Initialize(
+	OUT	PNDIS_STATUS	OpenErrorStatus,
+	OUT PUINT			SelectedMediumIndex,
+	IN	PNDIS_MEDIUM	MediumArray,
+	IN	UINT			MediumArraySize,
+	IN	NDIS_HANDLE		MiniportAdapterHandle,
+	IN	NDIS_HANDLE		ConfigurationHandle
+	);
+
+VOID
+Aic5900EnableInterrupt(
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	);
+
+VOID
+Aic5900DisableInterrupt(
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	);
+
+VOID
+Aic5900ISR(
+	OUT	PBOOLEAN	InterruptRecognized,
+	OUT	PBOOLEAN	QueueDpc,
+	IN	PVOID		Context
+	);
+
+VOID
+Aic5900HandleInterrupt(
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	);
+
+NDIS_STATUS
+Aic5900ReturnPackets(
+    IN	NDIS_HANDLE		MiniportAdapterContext,
+    IN	PNDIS_PACKET	Packet
+    );
+
+VOID
+Aic5900AllocateComplete(
+    IN	NDIS_HANDLE				MiniportAdapterContext,
+    IN	PVOID					VirtualAddress,
+    IN	PNDIS_PHYSICAL_ADDRESS	PhysicalAddress,
+	IN	ULONG					Length,
+	IN	PVOID					Context
+    );
+
+///
+//	PROTOTYPES FOR REQUEST CODE
+///
+NDIS_STATUS
+Aic5900SetInformation(
+	IN	NDIS_HANDLE	MiniportAdapterContext,
+	IN	NDIS_OID	Oid,
+	IN	PVOID		InformationBuffer,
+	IN	ULONG		InformationBufferLength,
+	OUT	PULONG		BytesRead,
+	OUT	PULONG		BytesNeeded
+	);
+
+NDIS_STATUS
+Aic5900QueryInformation(
+	IN	NDIS_HANDLE	MiniportAdapterContext,
+	IN	NDIS_OID	Oid,
+	IN	PVOID		InformationBuffer,
+	IN	ULONG		InformationBufferLength,
+	OUT	PULONG		BytesRead,
+	OUT	PULONG		BytesNeeded
+	);
+
+NDIS_STATUS
+Aic5900Request(
+	IN		NDIS_HANDLE		MiniportAdapterContext,
+	IN		NDIS_HANDLE		MiniportVcContext	OPTIONAL,
+	IN	OUT	PNDIS_REQUEST	NdisCoRequest
+	);
+
+///
+//	PROTOTYPES FOR RESET CODE
+///
+BOOLEAN
+Aic5900CheckForHang(
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	);
+
+NDIS_STATUS
+Aic5900Reset(
+	OUT	PBOOLEAN	AddressingReset,
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	);
+
+///
+//	PROTOTYPES FOR HALTING THE ADAPTER AND CLEANUP
+///
+
+VOID
+aic5900FreeResources(
+	IN PADAPTER_BLOCK pAdapter
+	);
+
+VOID
+Aic5900Halt(
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	);
+
+///
+//	PROTOTYPES FOR SEND PATH
+///
+VOID
+Aic5900SendPackets(
+	IN	NDIS_HANDLE		MiniportVcContext,
+	IN	PPNDIS_PACKET	PacketArray,
+	IN	UINT			NumberOfPackets
+	);
+
+
+///
+//	PROTOTYPES FOR VC Creation and Deletion
+///
+
+NDIS_STATUS
+Aic5900CreateVc(
+	IN	NDIS_HANDLE		MiniportAdapterContext,
+	IN	NDIS_HANDLE		NdisVcHandle,
+	OUT	PNDIS_HANDLE	MiniportVcContext
+	);
+
+NDIS_STATUS
+Aic5900DeleteVc(
+	IN	NDIS_HANDLE	MiniportVcContext
+	);
+
+NDIS_STATUS
+Aic5900ActivateVc(
+	IN	NDIS_HANDLE				MiniportVcContext,
+	IN	PCO_MEDIA_PARAMETERS	MediaParameters
+	);
+
+NDIS_STATUS
+Aic5900DeactivateVc(
+	IN	NDIS_HANDLE	MiniportVcContext
+	);
+
+VOID
+aic5900DeactivateVcComplete(
+	IN	PADAPTER_BLOCK	pAdapter,
+	IN	PVC_BLOCK		pVc
+	);
+
+#endif // __PROTOS_H
diff --git a/private/ntos/ndis/aic5900/receive.c b/private/ntos/ndis/aic5900/receive.c
new file mode 100644
index 000000000..c2a619461
--- /dev/null
+++ b/private/ntos/ndis/aic5900/receive.c
@@ -0,0 +1,68 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\receive.c
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#include "aic5900.h"
+
+#define	MODULE_NUMBER	MODULE_RECEIVE
+
+NDIS_STATUS
+Aic5900ReturnPackets(
+    IN	NDIS_HANDLE		MiniportAdapterContext,
+    IN	PNDIS_PACKET	Packet
+    )
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+
+	return(NDIS_STATUS_FAILURE);
+}
+
+
+VOID
+Aic5900AllocateComplete(
+    IN	NDIS_HANDLE				MiniportAdapterContext,
+    IN	PVOID					VirtualAddress,
+    IN	PNDIS_PHYSICAL_ADDRESS	PhysicalAddress,
+	IN	ULONG					Length,
+	IN	PVOID					Context
+    )
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+
+}
+
diff --git a/private/ntos/ndis/aic5900/request.c b/private/ntos/ndis/aic5900/request.c
new file mode 100644
index 000000000..5a6f394ca
--- /dev/null
+++ b/private/ntos/ndis/aic5900/request.c
@@ -0,0 +1,81 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\request.c
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#include "aic5900.h"
+
+#define	MODULE_NUMBER	MODULE_REQUEST
+
+NDIS_STATUS
+Aic5900SetInformation(
+	IN	NDIS_HANDLE	MiniportAdapterContext,
+	IN	NDIS_OID	Oid,
+	IN	PVOID		InformationBuffer,
+	IN	ULONG		InformationBufferLength,
+	OUT	PULONG		BytesRead,
+	OUT	PULONG		BytesNeeded
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	return(NDIS_STATUS_FAILURE);
+}
+
+NDIS_STATUS
+Aic5900QueryInformation(
+	IN	NDIS_HANDLE	MiniportAdapterContext,
+	IN	NDIS_OID	Oid,
+	IN	PVOID		InformationBuffer,
+	IN	ULONG		InformationBufferLength,
+	OUT	PULONG		BytesRead,
+	OUT	PULONG		BytesNeeded
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	return(NDIS_STATUS_FAILURE);
+}
+	
+NDIS_STATUS
+Aic5900Request(
+	IN		NDIS_HANDLE		MiniportAdapterContext,
+	IN		NDIS_HANDLE		MiniportVcContext	OPTIONAL,
+	IN	OUT	PNDIS_REQUEST	NdisCoRequest
+	)
+{
+	return(NDIS_STATUS_SUCCESS);
+}
+	
diff --git a/private/ntos/ndis/aic5900/reset.c b/private/ntos/ndis/aic5900/reset.c
new file mode 100644
index 000000000..4e581da94
--- /dev/null
+++ b/private/ntos/ndis/aic5900/reset.c
@@ -0,0 +1,79 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\reset.c
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#include "aic5900.h"
+
+#define	MODULE_NUMBER	MODULE_RESET
+
+BOOLEAN
+Aic5900CheckForHang(
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	return(FALSE);
+}
+
+NDIS_STATUS
+Aic5900Reset(
+	OUT	PBOOLEAN	AddressingReset,
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	return(NDIS_STATUS_FAILURE);
+}
+
+VOID
+Aic5900Halt(
+	IN	NDIS_HANDLE	MiniportAdapterContext
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	aic5900FreeResources((PADAPTER_BLOCK)MiniportAdapterContext);	
+}
+
diff --git a/private/ntos/ndis/aic5900/sar.h b/private/ntos/ndis/aic5900/sar.h
new file mode 100644
index 000000000..ff201ee35
--- /dev/null
+++ b/private/ntos/ndis/aic5900/sar.h
@@ -0,0 +1,781 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\sar.h
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#ifndef __SAR_H
+#define __SAR_H
+
+//
+//	MIDWAY macros.
+//
+#define MID_XMTREG_PLACE2SIZE(place)		((place >> 10) & 0x3)
+#define MID_XMTREG_PLACE2LOCATION(place)	(place & 0x3ff)
+#define	MIDWAY_MAX_SEGMENT_CHANNELS			8
+
+#define	MIDWAY_XMIT_SEG_CHANNEL_UBR			0
+
+#define	BLOCK_SIZE_1k	1024
+#define BLOCK_SIZE_2k	2048
+#define BLOCK_SIZE_4k	4096
+#define BLOCK_SIZE_8k	8192
+#define BLOCK_SIZE_16k	16384
+#define	BLOCK_SIZE_32k	32768
+#define BLOCK_SIZE_64k	65536
+#define BLOCK_SIZE_128k	131072
+
+#define	CONVERT_BYTE_OFFSET_TO_MIDWAY_LOCATION(_offset)	((_offset) >> 10)
+#define CONVERT_WORD_OFFSET_TO_MIDWAY_LOCATION(_offset)	((_offset) >> 8)
+
+#define	CONVERT_MIDWAY_LOCATION_TO_BYTE_OFFSET(_location)	((_location) << 10)
+#define	CONVERT_MIDWAY_LOCATION_TO_WORD_OFFSET(_location)	((_location) << 8)
+
+#define CONVERT_BYTE_SIZE_TO_MIDWAY_SIZE(_size)	CONVERT_WORD_SIZE_TO_MIDWAY_SIZE((_size) / 4)
+#define	CONVERT_WORD_SIZE_TO_MIDWAY_SIZE(_size)	\
+	((256 == (_size)) ? 0 :						\
+	 (512 == (_size)) ? 1 :						\
+	 (1024 == (_size)) ? 2 :					\
+	 (2048 == (_size)) ? 3 :					\
+	 (4096 == (_size)) ? 4 :					\
+	 (8192 == (_size)) ? 5 :					\
+	 (16384 == (_size)) ? 6 : 7)
+
+//
+//	This is the VC that all OAM cells are forced to go to.
+//
+#define	MIDWAY_OAM_VCI					3
+
+#define ATMHEADER_PTI_OAM_SEG			4
+#define ATMHEADER_PTI_OAM_END2END		5
+		
+#define MIDWAY_DMA_QUEUE_SIZE					512
+#define MIDWAY_SERVICE_QUEUE_SIZE				1024
+
+
+//
+//	These are always the same and are used for clarity in the driver code.
+//
+#define MIDWAY_VCI_TABLE_OFFSET				0
+#define MIDWAY_RECEIVE_DMA_QUEUE_OFFSET		0x4000
+#define MIDWAY_TRANSMIT_DMA_QUEUE_OFFSET	0x5000
+#define MIDWAY_SERVICE_QUEUE_OFFSET			0x6000
+
+//
+//	MIDWAY_XMIT_REGISTERS
+//
+//	Description:
+//		This is the data structure for the MIDWAY ATM transmit channel
+//		register set.
+//		This structure is defined seperately from the MIDWAY_REGS structure
+//		because there are 8 transmit engines that each have a set of registers.
+//		For a full description consult the Midway (SBUS) ASIC Specification.
+//
+//	Elements:
+//		xmt_place		-	Contains the Size/Location of the XMT segment
+//							memory for the queue.
+//		xmt_rdptr		-	Points to the next 32 bit word to be transfered to
+//							the PHY.  Maintained by Midway.
+//		xmt_descrstart	-	Points to the start of the Segmentation buffer
+//							(descriptor), currently being DMA'd into the
+//							segment memory queue.
+//
+struct	_MIDWAY_XMIT_REGISTERS
+{
+	union
+	{
+		struct _XmitPlace
+		{
+			HWUL	Location:11;
+			HWUL	Size:3;
+			HWUL	Reserved0: 18;
+		};
+
+		HWUL		Register;
+	}
+		XmitPlace;
+
+	union
+	{
+		struct _XmitReadPointer
+		{
+			HWUL	Pointer:15;
+			HWUL	Reserved0:17;
+		};
+
+		HWUL		Register;
+	}
+		XmitReadPointer;
+
+	union
+	{
+		struct _XmitDescriptorStart
+		{
+			HWUL	Pointer:15;
+			HWUL	Reserved0:17;
+		};
+
+		HWUL		Register;
+	}
+		XmitDescriptorStart;
+
+	HWUL	XmitUnused;
+};
+
+#define	MIDWAY_XMTREG_PLACE2SIZE(_place)	   	(((_place) >> 10) & 0x3)
+#define	MIDWAY_XMTREG_PLACE2LOCATION(_place)	((_place) & 0x3ff)
+
+//
+//	MIDWAY_REGISTERS
+//
+//	Description:
+//		This data structure defines the MIDWAY ATM ASIC register set.
+//		For a full description consult the Midway (SBUS) ASIC Specification.
+//		If you look carefully, the member names in this structure match
+//		the names used in the document.  Simply tack 'mid_reg_' on to the
+//		front of the names in the document.
+//
+//	Elements:
+//		ResetID				-   Midway Reset / ID
+//		ISA					-	Interrupt Status Acknowledge
+//		IS					-	Interrupt Status
+//		IE					-	Interrupt Enable
+//		MCS					-   Master Control/Status
+//		Statistics			-   Statistics
+//		ServiceList			-	Service List Write Pointer.
+//		DmaWriteRcv			-   RCV DMA write pointer
+//		DmaReadRcv			-   RCV DMA read pointer
+//		DmaWriteXmit		-   XMT DMA write pointer
+//		DmaReadXmit			-   XMT DMA read pointer
+//		Unused[3]			-
+//		TransmitRegisters	-	XMT channel registers
+//
+//	Note:
+//		The midway is a 32-bit only device. Make sure that all accesses
+//		to the registers are 32-bit accesses. The adapter will assist you
+//		in ensuring this by forcing bus errors if you attmept anything
+//		other than 32-bit accesses.
+//		the structures that come before the MIDWAY_REGISTERS are defined as
+//		a union of bit fields and a ULONG, this is so that the register can
+//		be easily constructed and then copied in a single 32-bit operation
+//		to the hardware register.
+//
+
+typedef struct _MIDWAY_REG_RESET_ID
+{
+	union
+	{
+		struct
+		{
+			HWUL	ConfigId1: 5;
+			HWUL 	ConV6: 1;
+			HWUL 	ConSuni: 1;
+			HWUL 	ConfigId2: 1;
+			HWUL 	MotherId: 3;
+			HWUL 	reserved0: 17;
+			HWUL 	SarId: 4;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_RESET_ID,
+	*PMIDWAY_REG_RESET_ID;
+
+typedef struct _MIDWAY_REG_ISA
+{
+	union
+	{
+		struct
+		{
+			HWUL 	StatusOverflow:1;
+			HWUL 	Suni:1;
+			HWUL 	Service:1;
+			HWUL 	XmitDmaComplete:1;
+			HWUL 	RcvDmaComplete:1;
+			HWUL 	DmaErrorAck:1;
+			HWUL 	Reserved0:1;
+			HWUL 	XmitIdenMismatch:1;
+			HWUL 	XmitDmaOverflow:1;
+			HWUL 	XmitComplete0:1;
+			HWUL 	XmitComplete1:1;
+			HWUL 	XmitComplete2:1;
+			HWUL 	XmitComplete3:1;
+			HWUL 	XmitComplete4:1;
+			HWUL 	XmitComplete5:1;
+			HWUL 	XmitComplete6:1;
+			HWUL 	XmitComplete7:1;
+			HWUL 	Pci:1;
+			HWUL 	Reserved1:14;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_ISA,
+	*PMIDWAY_REG_ISA;
+
+typedef struct _MIDWAY_REG_IS
+{
+	union
+	{
+		struct
+		{
+			HWUL    StatusOverflow:1;
+			HWUL    Suni:1;
+			HWUL    Service:1;
+			HWUL    XmitDmaComplete:1;
+			HWUL    RcvDmaComplete:1;
+			HWUL    DmaErrorAck:1;
+			HWUL    Reserved0:1;
+			HWUL    XmitIdenMismatch:1;
+			HWUL    XmitDmaOverflow:1;
+			HWUL    XmitComplete0:1;
+			HWUL    XmitComplete1:1;
+			HWUL    XmitComplete2:1;
+			HWUL    XmitComplete3:1;
+			HWUL    XmitComplete4:1;
+			HWUL    XmitComplete5:1;
+			HWUL    XmitComplete6:1;
+			HWUL    XmitComplete7:1;
+			HWUL    Pci: 1;
+			HWUL    Reserved1:14;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_IS,
+	*PMIDWAY_REG_IS;
+
+typedef struct _MIDWAY_REG_IE
+{
+	union
+	{
+		struct
+		{
+			HWUL    EnableStatusOverflow:1;
+			HWUL    EnableSuni:1;
+			HWUL    EnableService:1;
+			HWUL    EnableXmitDmaComplete:1;
+			HWUL	EnableRcvDmaComplete:1;
+			HWUL    EnableDmaErrorAck:1;
+			HWUL    Reserved0:1;
+			HWUL    EnableXmitIdenMismatch:1;
+			HWUL    EnableXmitDmaOverflow: 1;
+			HWUL    EnableXmitComplete0:1;
+			HWUL    EnableXmitComplete1:1;
+			HWUL    EnableXmitComplete2:1;
+			HWUL    EnableXmitComplete3:1;
+			HWUL    EnableXmitComplete4:1;
+			HWUL    EnableXmitComplete5:1;
+			HWUL    EnableXmitComplete6:1;
+			HWUL    EnableXmitComplete7:1;
+			HWUL    EnablePci:1;
+			HWUL    Reserved1:14;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_IE,
+	*PMIDWAY_REG_IE;
+
+typedef struct _MIDWAY_REG_MCS
+{
+	union
+	{
+		struct
+		{
+			HWUL	Wait500us:1;
+			HWUL	Wait1ms:1;
+			HWUL	RcvEnable:1;
+			HWUL	XmitEnable:1;
+			HWUL	DmaEnable:1;
+			HWUL	XmitLockMode:1;
+			HWUL	Wait2ms:1;
+			HWUL	Wait4ms:1;
+			HWUL	Reserved0:24;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_MCS,
+	*PMIDWAY_REG_MCS;
+
+typedef struct _MIDWAY_REG_STATISTICS
+{
+	union
+	{
+		struct
+		{
+			HWUL	OverflowTrash:16;
+			HWUL	VciTrash:16;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_STATISTICS,
+	*PMIDWAY_REG_STATISTICS;
+
+typedef struct _MIDWAY_REG_SERVICE_LIST
+{
+	union
+	{
+		struct
+		{
+			HWUL	WritePointer:10;
+			HWUL	Reserved0:22;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_SERVICE_LIST,
+	*PMIDWAY_REG_SERVICE_LIST;
+
+typedef struct	_MIDWAY_REG_DMA_WRITE_RCV
+{
+	union
+	{
+		struct
+		{
+			HWUL	Pointer:9;
+			HWUL	Reserved0: 23;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_DMA_WRITE_RCV,
+	*PMIDWAY_REG_DMA_WRITE_RCV;
+
+typedef struct _MIDWAY_REG_DMA_READ_RCV
+{
+	union
+	{
+		struct
+		{
+			HWUL	Pointer:9;
+			HWUL	Reserved0:23;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_DMA_READ_RCV,
+	*PMIDWAY_REG_DMA_READ_RCV;
+
+struct _MIDWAY_REG_DMA_WRITE_XMIT
+{
+	union
+	{
+		struct
+		{
+			HWUL	Pointer:9;
+			HWUL	Reserved0:23;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_DMA_WRITE_XMIT,
+	*PMIDWAY_REG_DMA_WRITE_XMIT;
+
+struct _MIDWAY_REG_DMA_READ_XMIT
+{
+	union
+	{
+		struct
+		{
+			HWUL	Pointer:9;
+			HWUL	Reserved0:23;
+		};
+
+		HWUL	Register;
+	};
+}
+	MIDWAY_REG_DMA_READ_XMIT,
+    *PMIDWAY_REG_DMA_READ_XMIT;
+
+struct _MIDWAY_REGISTERS
+{
+	HWUL	ResetId;
+	HWUL	ISA;
+	HWUL	IS;
+	HWUL	IE;
+	HWUL	MCS;
+	HWUL	Statistics;             	
+	HWUL	ServiceList;
+
+	HWUL	Reserved;
+	
+	HWUL	DmaWriteRcv;
+	HWUL	DmaReadRcv;
+	HWUL	DmaWriteXmit;
+	HWUL	DmaReadXmit;
+
+	HWUL	Unused[4];
+
+	MIDWAY_XMIT_REGISTERS	TransmitRegisters[MIDWAY_MAX_SEGMENT_CHANNELS];
+};
+
+
+//
+//	The following defines are used for the interrupt registers.
+//
+//	IS	-	If a bit is set then the interrupt is pending.
+//	ISA	-	If a bit is set then the interrupt is pending.
+//			When read, ALL bits are cleared.  Accept SUNI_INT &
+//			STAT_OVFL which require additionl action.  ??PCI_INT??
+//	IE	-	If a bit is set then the interrupt is enabled.
+//
+#define MID_REG_INT_PCI					BIT(17)
+#define MID_REG_INT_XMT_COMPLETE_7		BIT(16)
+#define MID_REG_INT_XMT_COMPLETE_6		BIT(15)
+#define MID_REG_INT_XMT_COMPLETE_5		BIT(14)
+#define MID_REG_INT_XMT_COMPLETE_4		BIT(13)
+#define MID_REG_INT_XMT_COMPLETE_3		BIT(12)
+#define MID_REG_INT_XMT_COMPLETE_2		BIT(11)
+#define MID_REG_INT_XMT_COMPLETE_1		BIT(10)
+#define MID_REG_INT_XMT_COMPLETE_0		BIT(9)
+#define MID_REG_INT_XMT_DMA_OVFL		BIT(8)
+#define MID_REG_INT_XMT_IDEN_MISMTCH	BIT(7)
+#define MID_REG_INT_DMA_ERR_ACK			BIT(5)
+#define MID_REG_INT_RCV_DMA_COMPLETE	BIT(4)
+#define MID_REG_INT_XMT_DMA_COMPLETE	BIT(3)
+#define MID_REG_INT_SERVICE				BIT(2)
+#define MID_REG_INT_SUNI_INT			BIT(1)
+#define MID_REG_INT_STAT_OVFL			BIT(0)
+
+#define	MID_REG_MC_S_WAIT_4_MS			bit(7)
+#define	MID_REG_MC_S_WAIT_2_MS			BIT(6)
+#define MID_REG_MC_S_XMT_LOCK_MODE		BIT(5)
+#define MID_REG_MC_S_DMA_ENABLE			BIT(4)
+#define MID_REG_MC_S_XMT_ENABLE			BIT(3)
+#define MID_REG_MC_S_RCV_ENABLE			BIT(2)
+#define MID_REG_MC_S_WAIT_1_MS			BIT(1)
+#define	MID_REG_MC_S_WAIT_500_US		BIT(0)
+
+
+#define MID_REG_STAT_VCI_TRASH(reg_value) ((reg_value >> 0x16) & 0xff)
+#define MID_REG_STAT_OVFL_TRASH(reg_value) (reg_value & 0xff)
+
+//
+//	Format for the Midway's service list.  This is simply a 1k queue,
+//	of VC's that need DMA servicing
+//
+typedef struct _MIDWAY_SERVICE_LIST
+{
+	union
+	{
+		struct
+		{
+			HWUL	VciNumber:10;
+			HWUL	Reserved;
+		};
+
+		HWUL		Register;
+	};
+}
+	MIDWAY_SERVICE_LIST,
+	*PMIDWAY_SERVICE_LIST;
+
+
+typedef struct _MIDWAY_DMA_DESC
+{
+	union
+	{
+		struct
+		{
+			//
+			//	This is used to skip a block of memory instead of performing
+			//	DMA transfers.
+			//
+			HWUL	JustKidding:1;
+
+			//
+			//	The End field is set by the host when setting up the descriptor
+			//	for the last DMA block of a PDU.  It must be set in the last
+			//	DMA_Descriptor for the VCI.
+			//
+			HWUL	End:1;
+
+			//
+			//	This is the VC that points to the Reassembly_queue with the
+			//	data to be DMA'd.
+			//
+			HWUL	Vci:10;
+
+			//
+			//	Number of bytes to be transfered.
+			//
+			HWUL	Count:18;
+
+			HWUL	Reserved:2;
+		};
+
+		HWUL		Register;
+	};
+
+	HWUL			LowHostAddress;
+}
+	MIDWAY_DMA_DESC,
+	*PMIDWAY_DMA_DESC;
+
+typedef	union	_VCI_TABLE_ENTRY_WORD_0
+{
+	struct
+	{
+		//
+		//	This identifies whether or not the VCI is currently in the
+		//	Service_list.
+		//
+		HWUL	InService:1;
+
+		HWUL	Reserved:14;
+
+		//
+		//	Specifies the size of the Reassembly_queue.
+		//
+		HWUL	Size:3;
+
+		//
+		//	This contains up to the 11 MSBs of the address location of the
+		//	corresponding Reassembly_queue in adapter memory.
+		//
+		HWUL	Location:11;
+
+		//
+		//	When set we will preserve OAM F5 cellson the given VCI and
+		//	direct them to VCI 3 (the OAM channel).  When clear the
+		//	OAM F5 cells that are received on this VCI will be trashed.
+		//
+		HWUL	PtiMode:1;
+
+		//
+		//	Indicates the operation mode of the VC:
+		//		00	=	Trash
+		//		01	=	non-AAL5
+		//		10	=	AAL5
+		//		11	=	Reserved
+		//
+		HWUL	Mode:2;
+	};
+
+	HWUL		Register;
+}
+	_VCI_TABLE_ENTRY_WORD_0,
+    *PVCI_TABLE_ENTRY_WORD_0;
+
+typedef union	_VCI_TABLE_ENTRY_WORD_1
+{
+	struct
+	{
+		//
+		//	Points to the last 32-bit word that was DMA'd to host memory
+		//	from the Reassembly_queue.
+		//
+		HWUL	ReadPtr:15;
+
+		HWUL	Reserved0:1;
+
+		//
+		//	Points to the start of the reassembly buffer descriptor
+		//	currently being reassembled in the Reassembly_queue, or
+		//	the next free location in adapter memory when the channel
+		//	is idle.
+		//
+		HWUL	DescStart:15;
+
+		HWUL	Reserved1:1;
+	};
+
+	HWUL		Register;
+}
+	VCI_TABLE_ENTRY_WORD_1,
+	*PVCI_TABLE_ENTRY_WORD_1;
+
+typedef union	_VCI_TABLE_ENTRY_WORD_2
+{
+	struct
+	{
+		//
+		//	Contains the temporary cell count for the PDU currently being
+		//	reassembled.
+		//
+		HWUL	CellCount:11;
+
+		HWUL	Reserved0:3;
+
+		//
+		//	Indicates the current state of the VCI:
+		//		00	=	Idle
+		//		01	=	Reassembling
+		//		11	=	Trashing
+		//
+		HWUL	State:2;
+
+		//
+		//	Points to the next free 32-bit word which will be overwritten
+		//	by the next reassembled word in the Reassembly_queue.
+		//
+		HWUL	writeptr: 15;
+
+		HWUL	Reserved1: 1;
+	};
+
+	HWUL		Register;
+}
+	VCI_TABLE_ENTRY_WORD_2,
+	*PVCI_TABLE_ENTRY_WORD_2;
+
+typedef struct _MIDWAY_VCI_TABLE_ENTRY
+{
+	//
+	//	See the above structures for the definitions of these.
+	//
+	HWUL	Register0;
+	HWUL	Register1;
+	HWUL	Register2;
+
+	//
+	//	This last ULONG contains the temporary CRC value being calculated
+	//	by the PDU currently being reassembled.
+	//
+	HWUL	Register3;	
+}
+	MIDWAY_VCI_TABLE_ENTRY,
+	*PMIDWAY_VCI_TABLE_ENTRY;
+
+
+//
+//	Transmit Segmentation Channel.
+//
+//		This is allocated for each segmentation channel.  This has
+//		all the information about each channel, e.g. buffers, size, etc....
+//
+
+struct _XMIT_SEG_CHANNEL
+{
+	PXMIT_SEG_CHANNEL		Next;					//	Next pointer.
+	PADAPTER_BLOCK			Adapter;				//	Pointer to the adapter.
+
+	UINT					MidwayChannelNumber;
+
+	//
+	//	Copy of the Midway transmit registers. This is the initial set of
+	//	the transmit registers for the segmentation channel.
+	//
+	MIDWAY_XMIT_REGISTERS	MidwayInitRegs;
+
+	//
+	//	Pointer to the transmit registers.
+	//
+	PMIDWAY_XMIT_REGISTERS	MidwayTransmitRegs;
+
+	//
+	//	Size of the segment in 32-bit words.
+	//
+	UINT					SegmentSize;
+
+	//
+	//	Pointer to the segment memory on the nic.
+	//
+	HWUL					*Segment;
+
+	//
+	//	Host copy of the read pointer. This is used to determine how much
+	//	memory has been freed up when the transmit complete interrupt occurs.
+	//
+	UINT					SegmentReadPointer;
+
+	//
+	//	Host copy of the write pointer.  This is in size of words.
+	//
+	UINT					SegmentWritePointer;
+
+	//
+	//	The amount of free memory that is available in the transmit segment.
+	//
+	UINT					SegmentRoom;
+
+	//
+	//	Queue of transmit descriptors waiting for segment room.
+	//
+	LIST_ENTRY				SegmentWaitQ;
+
+	//
+	//	Queue of transmit descriptors waiting for transmit completion.
+	//	These have been handed to the DMA/XMIT engine and are awaiting
+	//	completion.
+	//
+	LIST_ENTRY				TransmitWaitQ;
+
+	//
+	//	Number of Bytes queued on the channel.
+	//
+	UINT					XmitPduBytes;
+
+	//
+	//	Flags for the transmit segmentation channel.
+	//
+	ULONG					flags;
+
+	//
+	//	Spin lock for this structure.
+	//
+	NDIS_SPIN_LOCK			lock;
+};
+
+#define	fXSC_XMIT_START_ACTIVE		0x00000001
+#define fXSC_CBR_ONLY				0x00000002
+
+//
+//	Contains information about the Segmentation and Reassembly unit.
+//
+struct _SAR_INFO
+{
+	//
+	//	Number of segmentation channels.
+	//
+	XMIT_SEG_CHANNEL	XmitSegChannel[MIDWAY_MAX_SEGMENT_CHANNELS];
+
+	//
+	//	Points to the free segmentation channel.
+	//
+	PXMIT_SEG_CHANNEL	FreeXmitSegChannel;
+	NDIS_SPIN_LOCK		lockFreeXmitSegment;
+
+	//
+	//	UBR transmit channel.
+	//
+	PXMIT_SEG_CHANNEL	ubrXmitChannel;
+
+	UINT				ReceiveServiceEntry;
+
+	UINT				MidwayMasterControl;
+};
+
+
+
+#endif // __SAR_H
diff --git a/private/ntos/ndis/aic5900/send.c b/private/ntos/ndis/aic5900/send.c
new file mode 100644
index 000000000..664d60866
--- /dev/null
+++ b/private/ntos/ndis/aic5900/send.c
@@ -0,0 +1,44 @@
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\send.c
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#include "aic5900.h"
+
+#define	MODULE_NUMBER	MODULE_SEND
+
+
+VOID
+Aic5900SendPackets(
+	IN	NDIS_HANDLE		MiniportVcContext,
+	IN	PPNDIS_PACKET	PacketArray,
+	IN	UINT			NumberOfPackets
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+}
diff --git a/private/ntos/ndis/aic5900/sources b/private/ntos/ndis/aic5900/sources
new file mode 100644
index 000000000..89ff408c2
--- /dev/null
+++ b/private/ntos/ndis/aic5900/sources
@@ -0,0 +1,54 @@
+!IF 0
+
+Copyright (c) 1989  Microsoft Corporation
+
+Module Name:
+
+    sources.
+
+Abstract:
+
+    This file specifies the target component being built and the list of
+    sources files needed to build that component.  Also specifies optional
+    compiler switches and libraries that are unique for the component being
+    built.
+
+
+Author:
+
+    Steve Wood (stevewo) 12-Apr-1990
+    Carol Fuss 13-July-1992   - Converted for the Netflx driver.
+
+NOTE:   Commented description of this file is in \nt\bak\bin\sources.tpl
+
+!ENDIF
+
+MAJORCOMP=ntos
+MINORCOMP=ndis
+
+TARGETNAME=aic5900
+TARGETPATH=$(BASEDIR)\public\sdk\lib
+TARGETTYPE=DRIVER
+
+TARGETLIBS=$(BASEDIR)\public\sdk\lib\*\ndis.lib lib\*\memmgr.lib
+
+C_DEFINES=$(C_DEFINES) -DNDIS_MINIPORT_DRIVER -DNDIS41_MINIPORT
+
+INCLUDES=..\..\inc
+
+MSC_WARNING_LEVEL=/W3 /WX
+
+RELATIVE_DEPTH=..\..
+
+SOURCES=init.c\
+        int.c\
+        receive.c\
+        request.c\
+        reset.c\
+        send.c\
+        vc.c\
+        debug.c\
+        data.c\
+        aic5900.rc
+
+
diff --git a/private/ntos/ndis/aic5900/sw.h b/private/ntos/ndis/aic5900/sw.h
new file mode 100644
index 000000000..4401ed2ab
--- /dev/null
+++ b/private/ntos/ndis/aic5900/sw.h
@@ -0,0 +1,330 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\sw.h
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#ifndef __SW_H
+#define __SW_H
+
+#define	AIC5900_NDIS_MAJOR_VERSION		4
+#define AIC5900_NDIS_MINOR_VERSION		1
+
+//
+//	This macro is used to convert big-endian to host format.
+//
+#define	GET_USHORT_2_USHORT(Dst, Src)						\
+	*((PUSHORT)(Dst)) = ((*((PUCHAR)(Src) + 0) << 8) +		\
+						 (*((PUCHAR)(Src) + 1)))
+
+#define	GET_ULONG_2_ULONG(Dst, Src)							\
+	*((PULONG)(Dst)) = ((*((PUCHAR)(Src) + 0) << 24) +		\
+						(*((PUCHAR)(Src) + 1) << 16) +		\
+						(*((PUCHAR)(Src) + 2) << 8)  +		\
+						(*((PUCHAR)(Src) + 3)))
+
+
+//
+//	Macros used to allocate and free memory.
+//
+#define ALLOCATE_MEMORY(_pStatus, _pAddress, _Length)			\
+{																\
+	NDIS_PHYSICAL_ADDRESS _HighestAddress;						\
+																\
+	NdisSetPhysicalAddressLow(_HighestAddress, 0xffffffff);		\
+	NdisSetPhysicalAddressHigh(_HighestAddress, 0xffffffff);	\
+																\
+	*(_pStatus) = NdisAllocateMemory(							\
+					(PVOID *)(_pAddress),						\
+					(UINT)(_Length),							\
+					0,											\
+					_HighestAddress);							\
+}
+
+#define FREE_MEMORY(_Address, _Length)							\
+{																\
+	NdisFreeMemory((PVOID)(_Address), (UINT)(_Length), 0);		\
+}
+
+#define	ZERO_MEMORY(_Address, _Length)							\
+{																\
+	NdisZeroMemory((_Address), (_Length));						\
+}
+
+//
+//	The following enumeration contains the possible registry parameters.
+//
+typedef enum _AIC5900_REGISTRY_ENTRY
+{
+	Aic5900BusNumber = 0,
+	Aic5900SlotNumber,
+	Aic5900VcHashTableSize,
+	Aic5900MaxRegistryEntry
+}
+	AIC5900_REGISTRY_ENTRY;
+
+
+//
+//	The following structure is used to keep track of registry
+//	parameters temporarily.
+//
+typedef struct	_AIC5900_REGISTRY_PARAMETER
+{
+	BOOLEAN	fPresent;
+	ULONG	Value;
+}
+	AIC5900_REGISTRY_PARAMETER,
+	*PAIC5900_REGISTRY_PARAMETER;
+
+typedef struct _HARDWARE_INFO
+{
+	//
+	//	Flags information on the HARDWARE_INFO structure.
+	//
+	ULONG			Flags;
+	NDIS_SPIN_LOCK	Lock;
+
+	//
+	//	Bus Information.
+	//
+	UINT	BusNumber;
+	UINT	SlotNumber;
+
+	//
+	//	Information from the PCI configuration information.
+	//
+	PPCI_COMMON_CONFIG		PciCommonConfig;
+
+	//
+	//	Interrupt information.
+	//
+	ULONG					InterruptLevel;
+	ULONG					InterruptVector;
+	NDIS_MINIPORT_INTERRUPT	Interrupt;
+	ULONG					InterruptMask;
+
+	//
+	//	I/O port information.
+	//
+	PVOID	PortOffset;
+	UINT	InitialPort;
+	ULONG	NumberOfPorts;
+
+	//
+	//	Memory mapped I/O space information.
+	//
+	PVOID					MappedIoSpace;
+	NDIS_PHYSICAL_ADDRESS	PhysicalIoSpace;
+	ULONG					IoSpaceLength;
+
+	PPCI_FCODE_IMAGE	FCodeImage;
+
+	UINT	NicModelNumber;			//	Model identifier.
+	UINT	RomVersionNumber;		//	Version number of the FCode.
+
+	ULONG	CellClockRate;			//	Rate of the cell clock.  This is used
+									//	in determining cell rate.
+
+	///
+	//	The following are I/O space memory offsets and sizes.
+	//	NOTE:
+	//		The following offsets are from the PciFCode pointer.
+	///
+
+	ULONG	rEpromOffset;		//	Offset of read-only EPROM info into I/O space.
+	ULONG	rEpromSize;			//	Size of read-only EPROM info.
+	PVOID	rEprom;				//	Mapped pointer to read-only EPROM info.
+
+	ULONG	rwEpromOffset;		//	Offset of read-write EPROM info into I/O space.
+	ULONG	rwEpromSize;		//	Size of read-only EPROM info.
+	PVOID	rwEprom;			//	Mapped pointer to read-write EPROM info.
+
+	ULONG	PhyOffset;			//	Offset of PHY registers into I/O space.
+	ULONG	PhySize;			//	Size of PHY reigsters.
+	PUCHAR	Phy;				//	Mapped pointer to the PHY registers.
+
+	ULONG	ExternalOffset;		//	Offset of EXTERNAL registers into I/O space.
+	ULONG	ExternalSize;		//	Size of EXTERNAL registers
+	PVOID	External;			//	Mapped pointer to EXTERNAL registers.
+
+	ULONG	MidwayOffset;		//	Offset of SAR registers into I/O space.
+	ULONG	MidwaySize;			//	Size of SAR registers.
+	PMIDWAY_REGISTERS	Midway;	//	Mapped pointer to the SAR registers.
+							
+	ULONG	PciCfgOffset;		//	Offset of PCI Config registers in I/O space.
+	ULONG	PciCfgSize;			//	Size of PCI Config registers.
+	PUCHAR	PciConfigSpace;		//	Mapped pointer to the PCI configuration space.
+
+	ULONG	SarRamOffset;		//	Offset of SAR Ram in I/O space.
+	ULONG	SarRamSize;			//	Size of SAR Ram.
+	PULONG	SarRam;				//	Mapped pointer to SAR Ram.
+
+	NDIS_HANDLE	hRamInfo;		//	Handle for the memory manager.
+
+	//
+	//	address of the adapter.
+	//
+	UCHAR	PermanentAddress[ATM_ADDRESS_LENGTH];
+	UCHAR	StationAddress[ATM_ADDRESS_LENGTH];
+};
+
+//
+//	Macros for flag manipulation.
+//
+#define	HW_TEST_FLAG(x, f)			((x)->Flags & (f))
+#define HW_SET_FLAG(x, f)			((x)->Flags |= (f))
+#define HW_CLEAR_FLAG(x, f)			((x)->Flags &= ~(f))
+
+
+//
+//	Flag definitions.
+//
+#define	fHARDWARE_INFO_INTERRUPT_REGISTERED		0x00000001
+
+typedef struct _ADAPTER_BLOCK
+{
+	//
+	//	Handle for use in calls into NDIS.
+	//
+	NDIS_HANDLE				MiniportAdapterHandle;
+
+	ULONG					References;
+	NDIS_SPIN_LOCK			Lock;
+
+	//
+	//	Flags describing the adapter state.
+	//
+	ULONG					Flags;
+
+	///
+	//	
+	///
+	PHARDWARE_INFO			HardwareInfo;
+
+	///
+	//	List of the Vc's
+	//
+	//	We maintain 2 lists of VCs. Those that have been activated
+	//	and thoes that are not.
+	///
+	LIST_ENTRY				InactiveVcList;
+	LIST_ENTRY				ActiveVcList;
+
+	//
+	//	The following cannot be moved!!!!
+	//	This is the hash list of a given VCI to it's PVC_BLOCK
+	//
+	PVC_BLOCK				VcHashList[1];
+};
+
+//
+//	Macros for adapter flag manipulation
+//
+#define	ADAPTER_SET_FLAG(_adapter, _f)			(_adapter)->Flags |= (_f)
+#define	ADAPTER_CLEAR_FLAG(_adapter, _f)		(_adapter)->Flags &= ~(_f)
+#define ADAPTER_TEST_FLAG(_adapter, _f)			(((_adapter)->Flags & (_f)) != (_f))
+
+//
+//	Flags for describing the Adapter state.
+//
+#define	fADAPTER_RESET_IN_PROGRESS		0x00000001
+
+
+typedef struct _VC_BLOCK
+{
+	LIST_ENTRY		Link;
+
+	PVC_BLOCK		NextVcHash;			// Pointer to the next VC in the hash list.
+
+	PADAPTER_BLOCK	Adapter;
+	PHARDWARE_INFO	HwInfo;
+	NDIS_HANDLE		NdisVcHandle;
+
+	ULONG			References;			//	Number of outstanding references
+										//	on this VC.
+
+	NDIS_SPIN_LOCK	Lock;				//	Protection for this structure.
+
+	ULONG			Flags;				//	Flags describing vc state.
+
+	//
+	//	ATM media parameters for this VC.
+	//
+	ULONG					MediaFlags;
+
+	ATM_VPIVCI				VpiVci;		//	VCI assigned to the VC.
+	ATM_AAL_TYPE			AALType;	//	AAL type supported by this VC.
+
+	//
+	//	The type of service for this VC.
+	//
+	ATM_SERVICE_CATEGORY	ServiceCategory;
+
+	//
+	//	
+	//
+	ULONG					AverageCellRate;
+	ULONG					PeakCellRate;
+	ULONG					BurstLengthCells;
+
+	//
+	//	Maximum length of the SDU...
+	//
+	ULONG					MaxSduSize;
+
+	ATM_MEDIA_PARAMETERS	MediaParameters;
+};
+
+//
+//	Macros for VC flag manipulation
+//
+#define	VC_SET_FLAG(_vc, _f)		(_vc)->Flags |= (_f)
+#define	VC_CLEAR_FLAG(_vc, _f)		(_vc)->Flags &= ~(_f)
+#define VC_TEST_FLAG(_vc, _f)		(((_vc)->Flags & (_f)) != (_f))
+
+//
+//	Flags describing VC state.
+//
+#define	fVC_ACTIVE					0x00000001
+#define fVC_DEACTIVATING			0x00000002
+#define	fVC_TRANSMIT				0x00000004
+#define fVC_RECEIVE					0x00000008
+
+
+//
+//
+//
+#define	aic5900ReferenceAdapter(_adapter)		(_adapter)->References++
+#define aic5900DereferenceAdapter(_adapter)		(_adapter)->References--
+
+#define aic5900ReferenceVc(_vc)					(_vc)->References++
+
+#define	aic5900DereferenceVc(_vc)						\
+{														\
+	(_vc)->References--;								\
+	if (((--(_vc)->References) == 0) &&					\
+		VC_TEST_FLAG((_vc), fVC_DEACTIVATING))			\
+	{													\
+		aic5900DeactivateVcComplete((_vc)->Adapter, (_vc));	\
+	}													\
+}
+
+#endif // __SW_H
+					
diff --git a/private/ntos/ndis/aic5900/vc.c b/private/ntos/ndis/aic5900/vc.c
new file mode 100644
index 000000000..4e048e97b
--- /dev/null
+++ b/private/ntos/ndis/aic5900/vc.c
@@ -0,0 +1,593 @@
+
+/*++
+
+Copyright (c) 1990-1995  Microsoft Corporation
+
+Module Name:
+
+	D:\nt\private\ntos\ndis\aic5900\vc.c
+
+Abstract:
+
+Author:
+
+	Kyle Brandon	(KyleB)		
+
+Environment:
+
+	Kernel mode
+
+Revision History:
+
+--*/
+
+#include "aic5900.h"
+
+#define MODULE_NUMBER	MODULE_VC
+
+NDIS_STATUS
+Aic5900CreateVc(
+	IN	NDIS_HANDLE				MiniportAdapterContext,
+	IN	NDIS_HANDLE				NdisVcHandle,
+	OUT	PNDIS_HANDLE			MiniportVcContext
+	)
+/*++
+
+Routine Description:
+
+	This is the NDIS 4.1 handler to create a VC.  This will allocate necessary
+	system resources for the VC.
+
+Arguments:
+
+	MiniportAdapterContext	-	Pointer to our ADAPTER_BLOCK.
+	NdisVcHandle			-	Handle that NDIS uses to identify the VC that
+								is about to be created.
+	MiniportVcContext		-	Storage to hold context information about
+								the newly created VC.
+
+Return Value:
+
+	NDIS_STATUS_SUCCESS if we successfully create the new VC.
+
+--*/
+{
+	PADAPTER_BLOCK	pAdapter = (PADAPTER_BLOCK)MiniportAdapterContext;
+	PVC_BLOCK		pVc;
+	NDIS_STATUS		Status;
+
+	DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
+		("==>Aic5900CreateVc\n"));
+
+	//
+	//	I'm paranoid.
+	//
+	MiniportVcContext = NULL;
+
+	//
+	//	Allocate memory for the VC.
+	//
+	ALLOCATE_MEMORY(&Status, &pVc, sizeof(VC_BLOCK));
+	if (NDIS_STATUS_SUCCESS != Status)
+	{
+		return(NDIS_STATUS_RESOURCES);
+	}
+
+	//
+	//	Initialize memory.
+	//
+	NdisZeroMemory(pVc, sizeof(VC_BLOCK));
+
+	//
+	//	Save a pointer to the adapter block with the vc.
+	//
+	pVc->Adapter = pAdapter;
+	pVc->NdisVcHandle = NdisVcHandle;
+	pVc->References = 1;
+
+	NdisAllocateSpinLock(&pVc->Lock);
+
+	NdisAcquireSpinLock(&pAdapter->Lock);
+
+	//
+	//	Add the VC to the adapter's inactive list.
+	//
+	InsertHeadList(&pAdapter->InactiveVcList, &pVc->Link);
+
+	//
+	//	This adapter has another reference...
+	//
+	pAdapter->References++;
+
+	NdisReleaseSpinLock(&pAdapter->Lock);
+
+	//
+	//	Return the pointer to the new VC as the context.
+	//
+	MiniportVcContext = (PNDIS_HANDLE)pVc;
+
+	DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
+		("<==Aic5900CreateVc\n"));
+
+	return(Status);
+}
+
+NDIS_STATUS
+Aic5900DeleteVc(
+	IN	NDIS_HANDLE	MiniportVcContext
+	)
+/*++
+
+Routine Description:
+
+	This is the NDIS 4.1 handler to delete a given VC. This routine will
+	free any resources that are associated with the VC.  For the VC to
+	be deleted it MUST be deactivated first.
+
+Arguments:
+
+	MiniportVcContext	-	Pointer to the VC_BLOCK describing the VC that
+							is to be deleted.
+
+Return Value:
+
+	NDIS_STATUS_SUCCESS if the VC is successfully deleted.
+
+--*/
+{
+	PVC_BLOCK		pVc = (PVC_BLOCK)MiniportVcContext;
+	PADAPTER_BLOCK	pAdapter = pVc->Adapter;
+
+	DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
+		("==>Aic5900DeleteVc\n"));
+
+	NdisAcquireSpinLock(&pAdapter->Lock);
+	NdisDprAcquireSpinLock(&pVc->Lock);
+
+	//
+	//	Verify that this VC is inactive.
+	//
+	if (VC_TEST_FLAG(pVc, (fVC_ACTIVE | fVC_DEACTIVATING)))
+	{
+		//
+		//	Cannot delete a VC that is still active.
+		//
+		NdisDprReleaseSpinLock(&pVc->Lock);
+		NdisReleaseSpinLock(&pAdapter->Lock);
+
+		return(NDIS_STATUS_FAILURE);
+	}
+
+	//
+	//	If a VC is deactive then it had better have only the creation
+	//	reference count on it!
+	//
+	ASSERT(1 == pVc->References);
+
+	//
+	//	Remove the VC from the inactive list.
+	//
+	RemoveEntryList(&pVc->Link);
+
+	NdisDprReleaseSpinLock(&pVc->Lock);
+	NdisReleaseSpinLock(&pAdapter->Lock);
+
+	//
+	//	Clean up the resources that were allocated on behalf of the
+	//	VC_BLOCK.
+	//
+	NdisFreeSpinLock(&pVc->Lock);
+
+	//
+	//	Free the memory that was taken by the vc.
+	//
+	FREE_MEMORY(pVc, sizeof(PVC_BLOCK));
+
+	DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
+		("<==Aic5900DeleteVc\n"));
+
+	return(NDIS_STATUS_SUCCESS);
+}
+
+NDIS_STATUS
+aic5900AllocateTransmitSegment(
+	IN	PADAPTER_BLOCK			pAdapter,
+	IN	PVC_BLOCK				pVc,
+	IN	PATM_MEDIA_PARAMETERS	pMediaParms
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	NDIS_STATUS	Status;
+
+	//
+	//	We do different things based upon the service category.
+	//
+	switch (pMediaParms->Transmit.ServiceCategory)
+	{
+		case ATM_SERVICE_CATEGORY_UBR:
+
+			break;
+
+		case ATM_SERVICE_CATEGORY_CBR:
+
+			break;
+
+		default:
+
+			Status = NDIS_STATUS_INVALID_DATA;
+
+			break;
+	}
+
+	return(Status);
+}
+
+
+NDIS_STATUS
+aic5900ValidateVpiVci(
+	IN	PADAPTER_BLOCK			pAdapter,
+	IN	PATM_MEDIA_PARAMETERS	pMediaParms
+	)
+/*++
+
+Routine Description:
+
+Arguments:
+
+Return Value:
+
+--*/
+{
+	PVC_BLOCK	pCurrentVc;
+	NDIS_STATUS	Status;
+	BOOLEAN		fInvalidVc = FALSE;
+
+	//
+	//	We only support VPI of 0!
+	//
+	if (pMediaParms->ConnectionId.Vpi != 0)
+	{
+		return(NDIS_STATUS_FAILURE);
+	}
+
+	if ((pMediaParms->ConnectionId.Vci < MIN_VCS) ||
+		(pMediaParms->ConnectionId.Vci > (MAX_VCS - 1)))
+	{
+		return(NDIS_STATUS_FAILURE);
+	}
+
+	//
+	//	See if we have a VC with the given VPI/VCI
+	//
+	pCurrentVc = CONTAINING_RECORD(&pAdapter->ActiveVcList.Flink, VC_BLOCK, Link);
+	while (pCurrentVc != (PVC_BLOCK)&pAdapter->ActiveVcList)
+	{
+		if ((pCurrentVc->VpiVci.Vpi == pMediaParms->ConnectionId.Vpi) &&
+			(pCurrentVc->VpiVci.Vci == pMediaParms->ConnectionId.Vci))
+		{
+			fInvalidVc = TRUE;
+			break;
+		}
+
+		pCurrentVc = (PVC_BLOCK)pCurrentVc->Link.Flink;
+	}
+
+	//
+	//	Did we find a VC with the given VPI/VCI.
+	//
+	if (fInvalidVc)
+	{
+		return(NDIS_STATUS_FAILURE);
+	}
+
+	return(NDIS_STATUS_SUCCESS);
+}
+
+NDIS_STATUS
+Aic5900ActivateVc(
+	IN	NDIS_HANDLE				MiniportVcContext,
+	IN	PCO_MEDIA_PARAMETERS	MediaParameters
+	)
+/*++
+
+Routine Description:
+
+	This is the NDIS 4.1 handler to activate a given VC.  This will allocate
+	hardware resources, e.g. QoS, for a VC that was already created.
+
+Arguments:
+
+	MiniportVcContext	-	Pointer to the VC_BLOCK representing the VC to
+							activate.
+	MediaParameters		-	ATM parameters (in our case) that are used to
+							describe the VC.
+
+Return Value:
+
+	NDIS_STATUS_SUCCESS	if the VC is successfully activated.
+
+--*/
+{
+	PVC_BLOCK				pVc = (PVC_BLOCK)MiniportVcContext;
+	PADAPTER_BLOCK			pAdapter = pVc->Adapter;
+	PATM_MEDIA_PARAMETERS	pMediaParms;
+	PVC_BLOCK				pTempVc;
+	NDIS_STATUS				Status = NDIS_STATUS_SUCCESS;
+
+	DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
+		("==>Aic5900ActivateVc"));
+
+	NdisDprAcquireSpinLock(&pVc->Lock);
+
+	do
+	{
+		//
+		//	If the VC is already active then we will need to
+		//	re-activate the VC with new parameters.....
+		//
+		if (VC_TEST_FLAG(pVc, fVC_ACTIVE))
+		{
+			//
+			//	Not ready for this yet....
+			//
+			DbgBreakPoint();
+		}
+
+		//
+		//	Are there any media specific parameters that we recognize?
+		//
+		if ((MediaParameters->MediaSpecific.ParamType != ATM_MEDIA_SPECIFIC) ||
+			(MediaParameters->MediaSpecific.Length != sizeof(ATM_MEDIA_PARAMETERS)))
+		{
+			DBGPRINT(DBG_COMP_VC, DBG_LEVEL_ERR,
+				("Invalid media parameters for vc creation\n"));
+	
+			Status = NDIS_STATUS_INVALID_DATA;
+
+			break;
+		}
+	
+		pMediaParms = (PATM_MEDIA_PARAMETERS)MediaParameters->MediaSpecific.Parameters;
+
+		//
+		//	Validate the VPI/VCI
+		//
+		Status = aic5900ValidateVpiVci(pAdapter, pMediaParms);
+		if (NDIS_STATUS_SUCCESS != Status)
+		{
+			break;
+		}
+
+		//
+		//	Save the VCI with our VC information.
+		//
+		pVc->VpiVci = pMediaParms->ConnectionId;
+
+		//
+		//	Check the AAL type.
+		//
+		if ((pMediaParms->AALType & (AAL_TYPE_AAL0 | AAL_TYPE_AAL5)) !=
+			(AAL_TYPE_AAL0 | AAL_TYPE_AAL5))
+		{
+			Status = NDIS_STATUS_INVALID_DATA;
+
+			break;
+		}
+
+		//
+		//	Save the AAL information with our VC.
+		//
+		pVc->AALType = pMediaParms->AALType;
+
+		//
+		//	Verify that we can support the given VC parameters.
+		//
+		if ((pVc->MediaFlags & TRANSMIT_VC) == TRANSMIT_VC)
+		{
+			VC_SET_FLAG(pVc, fVC_TRANSMIT);
+	
+			//
+			//	Allocate transmit resources.
+			//
+			Status = aic5900AllocateTransmitSegment(pAdapter, pVc, pMediaParms);
+			if (NDIS_STATUS_SUCCESS != Status)
+			{
+
+
+			}
+		}
+	
+		if ((pVc->MediaFlags & RECEIVE_VC) == RECEIVE_VC)
+		{
+			VC_SET_FLAG(pVc, fVC_RECEIVE);
+	
+			//
+			//	Allocate receive resources.
+			//
+
+		}
+	
+		VC_SET_FLAG(pVc, fVC_ACTIVE);
+
+	} while (FALSE);
+
+	NdisDprReleaseSpinLock(&pVc->Lock);
+	NdisReleaseSpinLock(&pAdapter->Lock);
+
+	DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
+		("<==Aic5900ActivateVc"));
+
+	return(Status);
+}
+
+NDIS_STATUS
+Aic5900DeactivateVc(
+	IN	NDIS_HANDLE	MiniportVcContext
+	)
+/*++
+
+Routine Description:
+
+	This is the NDIS 4.1 handler to deactivate a given VC.
+	This does not free any resources, but simply marks the VC as unusable.
+
+Arguments:
+
+	MiniportVcContext	-	Pointer to our VC_BLOCK that was allocated in
+							Aic5900CreateVc().
+
+Return Value:
+
+	NDIS_STATUS_SUCCESS if we successfully deactivate the VC.
+
+--*/
+{
+	PVC_BLOCK		pVc = (PVC_BLOCK)MiniportVcContext;
+	PADAPTER_BLOCK	pAdapter = pVc->Adapter;
+	NDIS_STATUS		Status = NDIS_STATUS_SUCCESS;
+
+	DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
+		("==>Aic5900DeactivateVc\n"));
+
+	NdisAcquireSpinLock(&pAdapter->Lock);
+
+	if (ADAPTER_TEST_FLAG(pAdapter, fADAPTER_RESET_IN_PROGRESS))
+	{
+		NdisReleaseSpinLock(&pAdapter->Lock);
+
+		return(NDIS_STATUS_RESET_IN_PROGRESS);
+	}
+
+	NdisDprAcquireSpinLock(&pVc->Lock);
+
+	do
+	{
+		if (!VC_TEST_FLAG(pVc, fVC_ACTIVE) ||
+			VC_TEST_FLAG(pVc, fVC_DEACTIVATING))
+		{
+			Status = NDIS_STATUS_FAILURE;
+			break;
+		}
+
+		//
+		//	Mark the VC.
+		//
+		VC_CLEAR_FLAG(pVc, fVC_ACTIVE);
+	
+		//
+		//	Can't deactivate a VC with outstanding references....
+		//
+		if (pVc->References > 1)
+		{
+			Status = NDIS_STATUS_PENDING;
+
+			break;
+		}
+
+		aic5900DeactivateVcComplete(pAdapter, pVc);
+	
+	} while (FALSE);
+
+	//
+	//	If we are pending the deactivation then mark the VC as
+	//	deactivating.
+	//
+	if (Status == NDIS_STATUS_PENDING)
+	{
+		VC_SET_FLAG(pVc, fVC_DEACTIVATING);
+	}
+
+	NdisDprReleaseSpinLock(&pVc->Lock);
+	NdisReleaseSpinLock(&pAdapter->Lock);
+
+	DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
+		("<==Aic5900DeactivateVc\n"));
+
+	return(NDIS_STATUS_SUCCESS);
+}
+
+VOID
+aic5900DeactivateVcComplete(
+	IN	PADAPTER_BLOCK	pAdapter,
+	IN	PVC_BLOCK		pVc
+	)
+/*++
+
+Routine Description:
+
+	This routine is called to complete the deactivation of the VC.
+	this does NOT call NdisMCoDeactivateVcComplete() it is simply a place
+	to put common code...
+
+Arguments:
+
+	pAdapter	-	Pointer to the ADAPTER_BLOCK owning the VC.
+	pVc			-	Pointer to the VC that is being deactivated.
+
+Return Value:
+
+
+Notes:
+
+	THIS ROUTINE MUST BE CALLED WITH BOTH THE ADAPTER_BLOCK AND THE VC'S
+	LOCKS ACQUIRED!!!!!
+
+--*/
+{
+	NDIS_STATUS	Status = NDIS_STATUS_SUCCESS;
+
+	DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
+		("==>DeactivateVcComplete\n"));
+
+	ASSERT(!VC_TEST_FLAG(pVc, fVC_ACTIVE));
+	ASSERT(pVc->References == 1);
+
+	//
+	//	Remove the VC from the active list and place it on the inactive list.
+	//
+	RemoveEntryList(&pVc->Link);
+	InsertHeadList(&pAdapter->InactiveVcList, &pVc->Link);
+
+	//
+	//	Free up an transmit resources...
+	//
+	if (VC_TEST_FLAG(pVc, fVC_TRANSMIT))
+	{
+
+	}
+
+	//
+	//	Free up any receive resources...
+	//
+	if (VC_TEST_FLAG(pVc, fVC_RECEIVE))
+	{
+
+
+	}
+
+	//
+	//	If this is a pending call then complete the deactivation back to
+	//	the call manager.
+	//
+	if (VC_TEST_FLAG(pVc, fVC_DEACTIVATING))
+	{
+		NdisDprReleaseSpinLock(&pVc->Lock);
+		NdisReleaseSpinLock(&pAdapter->Lock);
+
+		NdisMCoDeactivateVcComplete(Status, pVc->NdisVcHandle);
+
+		NdisAcquireSpinLock(&pAdapter->Lock);
+		NdisDprAcquireSpinLock(&pVc->Lock);
+	}
+
+	DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
+		("<==DeactivateVcComplete\n"));
+}