51 files changed, 1100 insertions, 0 deletions

diff --git a/private/ntos/nthals/halalp/alpha/28f008sa.c b/private/ntos/nthals/halalp/alpha/28f008sa.c
new file mode 100644
index 000000000..2865a2061
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/28f008sa.c
@@ -0,0 +1 @@
+#include "../halalpha/28f008sa.c"
diff --git a/private/ntos/nthals/halalp/alpha/29f040.c b/private/ntos/nthals/halalp/alpha/29f040.c
new file mode 100644
index 000000000..2c2b423af
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/29f040.c
@@ -0,0 +1 @@
+#include "../halalpha/29f040.c"
diff --git a/private/ntos/nthals/halalp/alpha/addrsup.c b/private/ntos/nthals/halalp/alpha/addrsup.c
new file mode 100644
index 000000000..b49efb042
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/addrsup.c
@@ -0,0 +1,6 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\haleb64p\alpha\addrsup.c"
diff --git a/private/ntos/nthals/halalp/alpha/adjust.c b/private/ntos/nthals/halalp/alpha/adjust.c
new file mode 100644
index 000000000..47c267fb8
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/adjust.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\adjust.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/allstart.c b/private/ntos/nthals/halalp/alpha/allstart.c
new file mode 100644
index 000000000..42f70b7ca
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/allstart.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\allstart.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/alphaio.s b/private/ntos/nthals/halalp/alpha/alphaio.s
new file mode 100644
index 000000000..d2fe61a53
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/alphaio.s
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\alphaio.s"
+
diff --git a/private/ntos/nthals/halalp/alpha/apecs.c b/private/ntos/nthals/halalp/alpha/apecs.c
new file mode 100644
index 000000000..06eb91348
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/apecs.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\apecs.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/apecserr.c b/private/ntos/nthals/halalp/alpha/apecserr.c
new file mode 100644
index 000000000..441154cc9
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/apecserr.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\apecserr.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/apecsio.s b/private/ntos/nthals/halalp/alpha/apecsio.s
new file mode 100644
index 000000000..27bb7caa7
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/apecsio.s
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\apecsio.s"
+
diff --git a/private/ntos/nthals/halalp/alpha/bios.c b/private/ntos/nthals/halalp/alpha/bios.c
new file mode 100644
index 000000000..3a9d3aa50
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/bios.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\bios.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/busdata.c b/private/ntos/nthals/halalp/alpha/busdata.c
new file mode 100644
index 000000000..2782bbbd2
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/busdata.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\haleb64p\alpha\busdata.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/cache.c b/private/ntos/nthals/halalp/alpha/cache.c
new file mode 100644
index 000000000..561528477
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/cache.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\cache.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/chipset.h b/private/ntos/nthals/halalp/alpha/chipset.h
new file mode 100644
index 000000000..0a72ef8cb
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/chipset.h
@@ -0,0 +1 @@
+#include "apecs.h"
diff --git a/private/ntos/nthals/halalp/alpha/cmos8k.c b/private/ntos/nthals/halalp/alpha/cmos8k.c
new file mode 100644
index 000000000..3656af8db
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/cmos8k.c
@@ -0,0 +1,2 @@
+#include "..\haleb64p\alpha\cmos8k.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/eb64pdef.h b/private/ntos/nthals/halalp/alpha/eb64pdef.h
new file mode 100644
index 000000000..8e7a0971b
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/eb64pdef.h
@@ -0,0 +1,6 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\haleb64p\alpha\eb64pdef.h"
diff --git a/private/ntos/nthals/halalp/alpha/ebenv.c b/private/ntos/nthals/halalp/alpha/ebenv.c
new file mode 100644
index 000000000..a993ecec8
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ebenv.c
@@ -0,0 +1,6 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\haleb64p\alpha\ebenv.c"
diff --git a/private/ntos/nthals/halalp/alpha/ebinitnt.c b/private/ntos/nthals/halalp/alpha/ebinitnt.c
new file mode 100644
index 000000000..60e8d2cb8
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ebinitnt.c
@@ -0,0 +1,6 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\haleb64p\alpha\ebinitnt.c"
diff --git a/private/ntos/nthals/halalp/alpha/ebintsup.c b/private/ntos/nthals/halalp/alpha/ebintsup.c
new file mode 100644
index 000000000..c4d181860
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ebintsup.c
@@ -0,0 +1,585 @@
+/*++
+
+Copyright (c) 1990  Microsoft Corporation
+Copyright (c) 1992, 1993  Digital Equipment Corporation
+
+Module Name:
+
+    ebintsup.c
+
+Abstract:
+
+    The module provides the interrupt support for EB64+ systems.
+
+Author:
+
+    Eric Rehm (DEC) 29-December-1993
+
+Revision History:
+
+
+--*/
+
+
+#include "halp.h"
+#include "eisa.h"
+#include "ebsgdma.h"
+#include "eb64pdef.h"
+#include "pcrtc.h"
+#include "pintolin.h"
+
+//
+// Global to control interrupt handling for EB64+
+//
+
+UCHAR IntMask0, IntMask1, IntMask2;
+
+VOID
+HalpInitializePciInterrupts (
+    VOID
+    );
+
+//
+// Define the context structure for use by interrupt service routines.
+//
+
+typedef BOOLEAN  (*PSECOND_LEVEL_DISPATCH)(
+    PKINTERRUPT InterruptObject
+    );
+
+//
+// Declare the interupt handler for the PCI and ISA bus.
+//
+
+BOOLEAN
+HalpPCIDispatch(
+    IN PKINTERRUPT Interrupt,
+    IN PVOID ServiceContext,
+    IN PKTRAP_FRAME TrapFrame
+    );
+
+//
+// The following is the interrupt object used for DMA controller interrupts.
+// DMA controller interrupts occur when a memory parity error occurs or a
+// programming error occurs to the DMA controller.
+//
+
+KINTERRUPT HalpEisaNmiInterrupt;
+
+//
+// The following function initializes NMI handling.
+//
+
+VOID
+HalpInitializeNMI(
+    VOID
+    );
+
+//
+// The following function is called when an ISA NMI occurs.
+//
+
+BOOLEAN
+HalHandleNMI(
+    IN PKINTERRUPT Interrupt,
+    IN PVOID ServiceContext
+    );
+
+VOID
+HalpDisableSioInterrupt(
+    IN ULONG Vector
+    );
+
+VOID
+HalpEnableSioInterrupt(
+    IN ULONG Vector,
+    IN KINTERRUPT_MODE InterruptMode
+    );
+
+
+BOOLEAN
+HalpInitializePCIInterrupts (
+    VOID
+    )
+
+/*++
+
+Routine Description:
+
+    This routine initializes the structures necessary for EISA & PCI operations
+    and connects the intermediate interrupt dispatcher. It also initializes the
+    ISA interrupt controller.
+
+Arguments:
+
+    None.
+
+Return Value:
+
+    If the second level interrupt dispatcher is connected, then a value of
+    TRUE is returned. Otherwise, a value of FALSE is returned.
+
+--*/
+
+{
+    KIRQL oldIrql;
+
+    //
+    // Initialize the EISA NMI interrupt.
+    //
+
+    HalpInitializeNMI();
+
+    //
+    // Directly connect the ISA interrupt dispatcher to the level for
+    // ISA bus interrupt.
+    //
+    // N.B. This vector is reserved for exclusive use by the HAL (see
+    //      interrupt initialization.
+    //
+
+    PCR->InterruptRoutine[PIC_VECTOR] = (PKINTERRUPT_ROUTINE)HalpPCIDispatch;
+    HalEnableSystemInterrupt(PIC_VECTOR, DEVICE_LEVEL, LevelSensitive);
+
+    if (SystemIsAlphaPC64)
+        (PVOID) HalpPCIPinToLineTable = (PVOID) AlphaPC64PCIPinToLineTable;
+    else
+        (PVOID) HalpPCIPinToLineTable = (PVOID) EB64PPCIPinToLineTable;
+
+    //
+    // Intitialize interrupt controller
+    //
+
+    KeRaiseIrql(ISA_DEVICE_LEVEL, &oldIrql);
+
+    //
+    // Initialize the PCI interrupts.
+    //
+    HalpInitializePciInterrupts();
+
+    //
+    // Initialize the SIO Interrupt Controller
+    //
+    HalpInitializeSioInterrupts();
+
+    //
+    // Restore IRQL level.
+    //
+
+    KeLowerIrql(oldIrql);
+
+    //
+    // Initialize the DMA mode registers to a default value.
+    // Disable all of the DMA channels except channel 4 which is the
+    // cascade of channels 0-3.
+    //
+
+    WRITE_PORT_UCHAR(
+        &((PEISA_CONTROL) HalpEisaControlBase)->Dma1BasePort.AllMask,
+        0x0F
+        );
+
+    WRITE_PORT_UCHAR(
+        &((PEISA_CONTROL) HalpEisaControlBase)->Dma2BasePort.AllMask,
+        0x0E
+        );
+
+    return(TRUE);
+}
+
+BOOLEAN
+HalpPCIDispatch(
+    IN PKINTERRUPT Interrupt,
+    IN PVOID ServiceContext,
+    IN PKTRAP_FRAME TrapFrame
+    )
+
+/*++
+
+Routine Description:
+
+    This routine is entered as the result of an interrupt being generated
+    via the vector that is connected to an interrupt object that describes
+    the PCI and ISA device interrupts. Its function is to call the second
+    level interrupt dispatch routine and acknowledge the interrupt at the ISA
+    controller.
+
+    This service routine should be connected as follows:
+
+       KeInitializeInterrupt(&Interrupt, HalpPCIDispatch,
+                             EISA_VIRTUAL_BASE,
+                             (PKSPIN_LOCK)NULL, PCI_LEVEL, PCI_LEVEL, PCI_LEVEL,
+                             LevelSensitive, TRUE, 0, FALSE);
+       KeConnectInterrupt(&Interrupt);
+
+Arguments:
+
+    Interrupt - Supplies a pointer to the interrupt object.
+
+    ServiceContext - Supplies a pointer to the ISA interrupt acknowledge
+        register.
+
+    TrapFrame - Supplies a pointer to the trap frame for this interrupt.
+
+Return Value:
+
+    Returns the value returned from the second level routine.
+
+--*/
+
+{
+    UCHAR PciVector, IntNumber;
+    ULONG PCRInOffset = 0xffff;
+    KPCR *pcr;
+
+    //
+    // Read in the 1st interrupt register.
+    //
+    PciVector = READ_PORT_UCHAR(INTERRUPT_MASK0_QVA) & IntMask0;
+
+    //
+    // Was it an ISA (SIO) interrupt?
+    //
+    if (PciVector & SIO_INTERRUPT_MASK) {
+        //
+        // ISA interrupt - call HalpSioDispatch().
+        //
+        return HalpSioDispatch();
+    }
+
+    //
+    // Which PCI interrupt was it?
+    //
+    if (PciVector) {
+        for(IntNumber = 0; IntNumber < 8; IntNumber++) {
+            if (PciVector & 1) {
+                PCRInOffset = IntNumber;
+                break;
+            }
+            PciVector >>= 1;
+        }
+    } else {
+        PciVector = READ_PORT_UCHAR(INTERRUPT_MASK1_QVA) & IntMask1;
+
+        if (PciVector) {
+            for(IntNumber = 0; IntNumber < 8; IntNumber++) {
+                if (PciVector & 1) {
+                    PCRInOffset = IntNumber + 8;
+                    break;
+                }
+                PciVector >>= 1;
+            }
+        } else if (INTERRUPT_MASK2_QVA != NULL) {
+            PciVector = READ_PORT_UCHAR(INTERRUPT_MASK2_QVA) & IntMask2;
+/*!!!!!!!!!!!!!!!!!!!!CHANGE!!!!!!!!!!!!!!!!!!!!!!*/
+            if (PciVector)
+            {
+               for(IntNumber = 0; IntNumber < 8; IntNumber++) {
+                   if (PciVector & 1) {
+                       PCRInOffset = IntNumber + 16;
+                       break;
+                   }
+                   PciVector >>= 1;
+               }
+            }
+/*!!!!!!!!!!!!!!!!!!!!CHANGE!!!!!!!!!!!!!!!!!!!!!!*/
+        }
+    }
+
+    if (PCRInOffset == 0xffff) {
+        return FALSE;
+    }
+
+    PCRInOffset += PCI_VECTORS;
+    PCRInOffset++;
+    return ((PSECONDARY_DISPATCH)PCR->InterruptRoutine[PCRInOffset])(
+        PCR->InterruptRoutine[PCRInOffset], TrapFrame);
+}
+
+
+VOID
+HalpDisablePCIInterrupt(
+    IN ULONG Vector
+    )
+
+/*++
+
+Routine Description:
+
+    This function Disables the PCI bus specified PCI bus interrupt.
+
+Arguments:
+
+    Vector - Supplies the vector of the PCI interrupt that is Disabled.
+
+Return Value:
+
+     None.
+
+--*/
+
+{
+        //
+        // Calculate the PCI interrupt vector.
+        //
+
+        Vector -= PCI_VECTORS;
+    Vector--;
+
+    //
+    // Clear the corresponding bit in the appropriate interrupt mask
+    // shadow and write it out to the interrupt mask.
+    //
+    if (Vector >= 0 && Vector <= 7) {
+        IntMask0 &= (UCHAR) ~(1 << Vector);
+        WRITE_PORT_UCHAR(INTERRUPT_MASK0_QVA, ~IntMask0);
+    } else if (Vector >= 8 && Vector <= 0xf) {
+        IntMask1 &= (UCHAR) ~(1 << (Vector - 8));
+        WRITE_PORT_UCHAR(INTERRUPT_MASK1_QVA, ~IntMask1);
+/*!!!!!!!!!!!!!!!!!!!!CHANGE!!!!!!!!!!!!!!!!!!!!!!*/
+    } else if ((Vector >= 0x10 && Vector <=0x17) &&
+               (INTERRUPT_MASK2_QVA != NULL)) {
+        IntMask2 &= (UCHAR) ~(1 << (Vector - 16));;
+/*!!!!!!!!!!!!!!!!!!!!CHANGE!!!!!!!!!!!!!!!!!!!!!!*/
+        WRITE_PORT_UCHAR(INTERRUPT_MASK2_QVA, ~IntMask2);
+    } else {
+#ifdef HALDBG
+        DbgPrint("HalpDisablePCIInterrupt: bad vector\n");
+#endif // HALDBG
+    }
+}
+
+
+VOID
+HalpEnablePCIInterrupt(
+    IN ULONG Vector
+    )
+
+/*++
+
+Routine Description:
+
+    This function enables the PCI bus specified PCI bus interrupt.
+    PCI interrupts must be LevelSensitve. (PCI Spec. 2.2.6)
+
+Arguments:
+
+    Vector - Supplies the vector of the ESIA interrupt that is enabled.
+
+    InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
+        Latched.
+
+Return Value:
+
+     None.
+
+--*/
+
+{
+        //
+        // Calculate the PCI interrupt vector.
+        //
+
+        Vector -= PCI_VECTORS;
+    Vector--;
+
+    //
+    // Set the corresponding bit in the appropriate interrupt mask
+    // shadow and write it out to the interrupt mask.
+    //
+    if (Vector >= 0 && Vector <= 7) {
+        IntMask0 |= (UCHAR) (1 << Vector);
+        WRITE_PORT_UCHAR(INTERRUPT_MASK0_QVA, ~IntMask0);
+    } else if (Vector >= 8 && Vector <= 0xf) {
+        IntMask1 |= (UCHAR) (1 << (Vector - 8));
+        WRITE_PORT_UCHAR(INTERRUPT_MASK1_QVA, ~IntMask1);
+/*!!!!!!!!!!!!!!!!!!!!CHANGE!!!!!!!!!!!!!!!!!!!!!!*/
+    } else if ((Vector >= 0x10 && Vector <= 0x17) &&
+               (INTERRUPT_MASK2_QVA != NULL)) {
+        IntMask2 |= (UCHAR) (1 << (Vector - 16));
+/*!!!!!!!!!!!!!!!!!!!!CHANGE!!!!!!!!!!!!!!!!!!!!!!*/
+        WRITE_PORT_UCHAR(INTERRUPT_MASK2_QVA, ~IntMask2);
+    } else {
+#ifdef HALDBG
+        DbgPrint("HalpEnablePCIInterrupt: bad vector\n");
+#endif // HALDBG
+    }
+}
+
+
+VOID
+HalpInitializeNMI(
+    VOID
+    )
+/*++
+
+Routine Description:
+
+   This function is called to intialize SIO NMI interrupts.
+
+Arguments:
+
+    None.
+
+Return Value:
+
+    None.
+--*/
+{
+    UCHAR DataByte;
+
+    //
+    // Initialize the SIO NMI interrupt.
+    //
+
+    KeInitializeInterrupt( &HalpEisaNmiInterrupt,
+                           HalHandleNMI,
+                           NULL,
+                           NULL,
+                           EISA_NMI_VECTOR,
+                           EISA_NMI_LEVEL,
+                           EISA_NMI_LEVEL,
+                           LevelSensitive,
+                           FALSE,
+                           0,
+                           FALSE
+                         );
+
+    //
+    // Don't fail if the interrupt cannot be connected.
+    //
+
+    KeConnectInterrupt( &HalpEisaNmiInterrupt );
+
+    //
+    // Clear the Eisa NMI disable bit.  This bit is the high order of the
+    // NMI enable register.
+    //
+
+    DataByte = 0;
+
+    WRITE_PORT_UCHAR(
+      &((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable,
+      DataByte
+      );
+
+}
+
+BOOLEAN
+HalHandleNMI(
+    IN PKINTERRUPT Interrupt,
+    IN PVOID ServiceContext
+    )
+/*++
+
+Routine Description:
+
+   This function is called when an EISA NMI occurs.  It print the appropriate
+   status information and bugchecks.
+
+Arguments:
+
+   Interrupt - Supplies a pointer to the interrupt object
+
+   ServiceContext - Bug number to call bugcheck with.
+
+Return Value:
+
+   Returns TRUE.
+
+--*/
+{
+    UCHAR   StatusByte;
+
+    StatusByte =
+        READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiStatus);
+
+    if (StatusByte & 0x80) {
+        HalDisplayString ("NMI: Parity Check / Parity Error\n");
+    }
+
+    if (StatusByte & 0x40) {
+        HalDisplayString ("NMI: Channel Check / IOCHK\n");
+    }
+
+     //
+     // This is an Sio machine, no extnded nmi information, so just do it.
+     //
+
+
+    KeBugCheck(NMI_HARDWARE_FAILURE);
+    return(TRUE);
+}
+
+
+VOID
+HalpAcknowledgeClockInterrupt(
+    VOID
+    )
+/*++
+
+Routine Description:
+
+    Acknowledge the clock interrupt from the interval timer.  The interval
+    timer for EB66 comes from the Dallas real-time clock.
+
+Arguments:
+
+    None.
+
+Return Value:
+
+    None.
+
+--*/
+{
+
+    //
+    // Acknowledge the clock interrupt by reading the control register C of
+    // the Real Time Clock.
+    //
+
+    HalpReadClockRegister( RTC_CONTROL_REGISTERC );
+
+    return;
+}
+
+VOID
+HalpInitializePciInterrupts (
+    VOID
+    )
+/*++
+
+Routine Description:
+
+    This routine initializes the PCI device interrupt mask.
+
+Arguments:
+
+    None.
+
+Return Value:
+
+    None.
+
+--*/
+{
+    //
+    // Initialize the shadow copies of the interrupt masks to enable only
+    // the SIO interrupt.
+    //
+
+    IntMask0 = (UCHAR)SIO_INTERRUPT_MASK;
+    IntMask1 = 0;
+    IntMask2 = 0;
+
+    //
+    // Write the masks.
+    //
+    WRITE_PORT_UCHAR(INTERRUPT_MASK0_QVA, ~IntMask0);
+    WRITE_PORT_UCHAR(INTERRUPT_MASK1_QVA, ~IntMask1);
+    if (INTERRUPT_MASK2_QVA != NULL) {
+        WRITE_PORT_UCHAR(INTERRUPT_MASK2_QVA, ~IntMask2);
+    }
+}
+
diff --git a/private/ntos/nthals/halalp/alpha/ebmapio.c b/private/ntos/nthals/halalp/alpha/ebmapio.c
new file mode 100644
index 000000000..60869cd20
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ebmapio.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\haleb64p\alpha\ebmapio.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/ebsgdma.c b/private/ntos/nthals/halalp/alpha/ebsgdma.c
new file mode 100644
index 000000000..f2f033fad
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ebsgdma.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\ebsgdma.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/ebsysint.c b/private/ntos/nthals/halalp/alpha/ebsysint.c
new file mode 100644
index 000000000..3147f4b1e
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ebsysint.c
@@ -0,0 +1,6 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\haleb64p\alpha\ebsysint.c"
diff --git a/private/ntos/nthals/halalp/alpha/eisasup.c b/private/ntos/nthals/halalp/alpha/eisasup.c
new file mode 100644
index 000000000..0d46ef3e4
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/eisasup.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\eisasup.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/environ.c b/private/ntos/nthals/halalp/alpha/environ.c
new file mode 100644
index 000000000..75015a0a0
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/environ.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\environ.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/ev4cache.c b/private/ntos/nthals/halalp/alpha/ev4cache.c
new file mode 100644
index 000000000..b0cf9e3be
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ev4cache.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\ev4cache.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/ev4int.c b/private/ntos/nthals/halalp/alpha/ev4int.c
new file mode 100644
index 000000000..8a10705d7
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ev4int.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\ev4int.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/ev4ints.s b/private/ntos/nthals/halalp/alpha/ev4ints.s
new file mode 100644
index 000000000..6df823ab6
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ev4ints.s
@@ -0,0 +1,6 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+#include "..\halalpha\ev4ints.s"
+
diff --git a/private/ntos/nthals/halalp/alpha/ev4mchk.c b/private/ntos/nthals/halalp/alpha/ev4mchk.c
new file mode 100644
index 000000000..697087c15
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ev4mchk.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\ev4mchk.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/ev4mem.s b/private/ntos/nthals/halalp/alpha/ev4mem.s
new file mode 100644
index 000000000..f410d09a3
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ev4mem.s
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\ev4mem.s"
+
diff --git a/private/ntos/nthals/halalp/alpha/ev4prof.c b/private/ntos/nthals/halalp/alpha/ev4prof.c
new file mode 100644
index 000000000..7ecdfa8b7
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ev4prof.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\ev4prof.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/flash8k.c b/private/ntos/nthals/halalp/alpha/flash8k.c
new file mode 100644
index 000000000..6e2b80345
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/flash8k.c
@@ -0,0 +1,2 @@
+#include "..\haleb64p\alpha\flash8k.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/flashdrv.c b/private/ntos/nthals/halalp/alpha/flashdrv.c
new file mode 100644
index 000000000..ad0994d4d
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/flashdrv.c
@@ -0,0 +1,3 @@
+#include "../halalpha/flashdrv.c"
+
+
diff --git a/private/ntos/nthals/halalp/alpha/fwreturn.c b/private/ntos/nthals/halalp/alpha/fwreturn.c
new file mode 100644
index 000000000..65ae88cb8
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/fwreturn.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\fwreturn.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/haldebug.c b/private/ntos/nthals/halalp/alpha/haldebug.c
new file mode 100644
index 000000000..ce91863ec
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/haldebug.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\haldebug.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/halpal.s b/private/ntos/nthals/halalp/alpha/halpal.s
new file mode 100644
index 000000000..fc89f8370
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/halpal.s
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\halpal.s"
+
diff --git a/private/ntos/nthals/halalp/alpha/idle.s b/private/ntos/nthals/halalp/alpha/idle.s
new file mode 100644
index 000000000..f517bab2f
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/idle.s
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\idle.s"
+
diff --git a/private/ntos/nthals/halalp/alpha/info.c b/private/ntos/nthals/halalp/alpha/info.c
new file mode 100644
index 000000000..22aef63a3
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/info.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\info.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/inithal.c b/private/ntos/nthals/halalp/alpha/inithal.c
new file mode 100644
index 000000000..a99cb9a1a
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/inithal.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\inithal.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/intsup.s b/private/ntos/nthals/halalp/alpha/intsup.s
new file mode 100644
index 000000000..a7d9f8f4f
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/intsup.s
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+#include "pcrtc.h"
+#include "..\halalpha\intsup.s"
+
diff --git a/private/ntos/nthals/halalp/alpha/ioproc.c b/private/ntos/nthals/halalp/alpha/ioproc.c
new file mode 100644
index 000000000..cc65eacde
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/ioproc.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\ioproc.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/iousage.c b/private/ntos/nthals/halalp/alpha/iousage.c
new file mode 100644
index 000000000..83cbfb656
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/iousage.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\iousage.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/machdep.h b/private/ntos/nthals/halalp/alpha/machdep.h
new file mode 100644
index 000000000..63664c856
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/machdep.h
@@ -0,0 +1,6 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\haleb64p\alpha\machdep.h"
diff --git a/private/ntos/nthals/halalp/alpha/memory.c b/private/ntos/nthals/halalp/alpha/memory.c
new file mode 100644
index 000000000..76b1eb7df
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/memory.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\memory.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/pcibus.c b/private/ntos/nthals/halalp/alpha/pcibus.c
new file mode 100644
index 000000000..56eb21557
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/pcibus.c
@@ -0,0 +1,6 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\haleb64p\alpha\pcibus.c"
diff --git a/private/ntos/nthals/halalp/alpha/pcisio.c b/private/ntos/nthals/halalp/alpha/pcisio.c
new file mode 100644
index 000000000..cf5f0f462
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/pcisio.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\pcisio.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/pcisup.c b/private/ntos/nthals/halalp/alpha/pcisup.c
new file mode 100644
index 000000000..360919f42
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/pcisup.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\pcisup.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/pcrtc.c b/private/ntos/nthals/halalp/alpha/pcrtc.c
new file mode 100644
index 000000000..2e57b87d6
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/pcrtc.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\pcrtc.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/pcserial.c b/private/ntos/nthals/halalp/alpha/pcserial.c
new file mode 100644
index 000000000..a2f159c48
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/pcserial.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\pcserial.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/pcspeakr.c b/private/ntos/nthals/halalp/alpha/pcspeakr.c
new file mode 100644
index 000000000..807b6f324
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/pcspeakr.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\pcspeakr.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/perfcntr.c b/private/ntos/nthals/halalp/alpha/perfcntr.c
new file mode 100644
index 000000000..6c0a8f892
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/perfcntr.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\perfcntr.c"
+
diff --git a/private/ntos/nthals/halalp/alpha/pintolin.h b/private/ntos/nthals/halalp/alpha/pintolin.h
new file mode 100644
index 000000000..988686a2f
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/pintolin.h
@@ -0,0 +1,212 @@
+/*++
+
+Copyright (c) 1993  Microsoft Corporation
+Copyright (c) 1994  Digital Equipment Corporation
+
+Module Name:
+
+    pintolin.h
+
+Abstract:
+
+    This file includes the platform-dependent Pin To Line Table.
+
+Author:
+
+Environment:
+
+    Kernel mode
+
+Revision History:
+
+    Dick Bissen [DEC]	13-Sep-1994
+
+
+--*/
+
+//
+// These tables represent the mapping from slot number and interrupt pin
+// into a PCI Interrupt Vector. 
+//
+// On Cabriolet, the interrupt vector is the Interrupt Request Register bit
+// representing the interrupt + 1.  The value also represents the interrupt
+// mask register bit since the mask register and the request register have
+// the same format.
+//
+// Formally, these mappings can be expressed as:
+// 
+//   PCIPinToLine: 
+//     SlotNumber.DeviceNumber x InterruptPin -> InterruptLine 
+//
+//   LineToVector:
+//     InterruptLine -> InterruptVector
+// 
+//   VectorToIRRBit:
+//     InterruptVector -> InterruptRequestRegisterBit
+//
+//   VectorToIMRBit:
+//     InterruptVector -> InterruptMaskRegisterBit
+//
+//   SlotNumberToIDSEL:
+//     SlotNumber.DeviceNumber -> IDSEL
+//
+// subject to following invariants (predicates must always be true):
+//
+//   Slot.DeviceNumber in {0,...,15}
+//
+//   InterruptPin in {1, 2, 3, 4}
+//
+//   InterruptRequestRegisterBit in {0,...,15}
+//
+//   InterruptMaskRegisterBit in {0,...,15}
+//
+//   PCIPinToLine(SlotNumber.DeviceNumber, InterruptPin) = 
+//         PCIPinToLineTable[SlotNumber.DeviceNumber, InterruptPin]
+//         (Table-lookup function initialized below)
+//
+//   LineToVector(InterruptLine) = PCI_VECTORS + InterruptLine
+//
+//   VectorToIRRBit(InterruptVector) = InterruptVector - 1
+//
+//   VectorToIMRBit(InterruptVector) [see below]
+//
+//   SlotNumberToIDSEL(SlotNumber.DeviceNumber) = (1 << (Slot.DeviceNumber+11))
+//
+// where:
+// 
+// SlotNumber.DeviceNumber:
+//   Alpha AXP Platforms receive interrupts on local PCI buses only, which
+//   are limited to 16 devices (PCI AD[11]-AD[26]). (We loose AD[17]-AD[31]
+//   since PCI Config space is a sparse space, requiring a five-bit shift.)
+//
+// InterruptPin:
+//   Each virtual slot has up to four interrupt pins INTA#, INTB#, INTC#, INTD#,
+//   as per the PCI Spec. V2.0, Section 2.2.6.  (FYI, only multifunction devices
+//   use INTB#, INTC#, INTD#.)   
+//
+//   PCI configuration space indicates which interrupt pin a device will use
+//   in the InterruptPin register, which has the values:
+//
+//              INTA# = 1, INTB#=2, INTC#=3, INTD# = 4
+//   
+//   Note that there may be up to 8 functions/device on a PCI multifunction
+//   device plugged into the option slots, e.g., Slot #0.  
+//   Each function has its own PCI configuration space, addressed
+//   by the SlotNumber.FunctionNumber field, and will identify which
+//   interrput pin of the four it will use in its own InterruptPin register.
+//
+//   If the option is a PCI-PCI bridge, interrupts across the bridge will
+//   somehow be combined to appear on some combination of the four
+//   interrupt pins that the bridge plugs into.
+//
+// InterruptLine:
+//   This PCI Configuration register, unlike x86 PC's, is maintained by
+//   software and represents offset into PCI interrupt vectors.
+//   Whenever HalGetBusData or HalGetBusDataByOffset is called,
+//   HalpPCIPinToLine() computes the correct InterruptLine register value
+//   by using the HalpPCIPinToLineTable mapping.
+//
+// InterruptRequestRegisterBit:
+//   0xff is used to mark an invalid IRR bit, hence an invalid request
+//   for a vector.  Also, note that the 16 bits of the EB66 IRR must
+//   be access as two 8-bit reads.
+//
+// InterruptMaskRegisterBit:
+//   On EB66, the PinToLine table may also be find the to write the 
+//   InterruptMaskRegister.  Formally, we can express this invariant as
+//
+//     VectorToIMRBit(InterrruptVector) = InterruptVector - 1
+//
+//   On Mustang, the table is useless.  The InterruptMaskRegister has
+//   only two bits the completely mask all interrupts from either 
+//   Slot #0 or Slot#1 (PCI AD[17] and AD[18]):
+//
+//     InterruptVector in {3,4,5,6}  then VectorToIMRBit(InterruptVector) = 0
+//     InterruptVector in {7,8,9,10} then VectorToIMRBit(InterruptVector) = 1
+//
+// IDSEL:
+//   For accessing PCI configuration space on a local PCI bus (as opposed
+//   to over a PCI-PCI bridge), type 0 configuration cycles must be generated.
+//   In this case, the IDSEL pin of the device to be accessed is tied to one
+//   of the PCI Address lines AD[11] - AD[26].  (The function field in the 
+//   PCI address is used should we be accessing a multifunction device.)
+//   Anyway, virtual slot 0 represents the device with IDSEL = AD[11], and
+//   so on.
+//  
+
+ULONG               *HalpPCIPinToLineTable;
+
+//
+// Interrupt Vector Table Mapping for eb64p
+//
+// eb64p PCI interrupts are mapped to ISA IRQs in the table below.
+//
+// Limit init table to 14 entries, which is MAX_PCI_LOCAL_DEVICES_AVANTI. 
+// We won't ever try to set an InterruptLine register of a slot greater 
+// than Virtual slot 13 = PCI_AD[24].
+//
+
+/*!!!!!!!!!!!!!!!!!!CHANGE!!!!!!!!!!!!!!!!!!!!!*/
+ULONG               AlphaPC64PCIPinToLineTable[][4]=
+{
+//    Pin 1 Pin 2 Pin 3 Pin 4
+//    ----- ----- ----- -----
+    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 0  = PCI_AD[11]
+    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 1  = PCI_AD[12]
+    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 2  = PCI_AD[13]
+    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 3  = PCI_AD[14]
+    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 4  = PCI_AD[15]
+    {  0x3,  0x8,  0xc, 0x10 },  // Virtual Slot 5  = PCI_AD[16]  bridge
+    {  0x1,  0x6,  0xa,  0xe },  // Virtual Slot 6  = PCI_AD[17]  Slot #0
+    {  0x2,  0x7,  0xb,  0xf },  // Virtual Slot 7  = PCI_AD[18]  Slot #1
+    {  0x5, 0xff, 0xff, 0xff },  // Virtual Slot 8  = PCI_AD[19]  SIO
+    {  0x4,  0x9,  0xd, 0x11 },  // Virtual Slot 9  = PCI_AD[20]  Slot #2
+    { 0x12, 0x13, 0x14, 0x15 }   // Virtual Slot 10 = PCI_AD[21]  Slot #3
+};
+//ULONG               AlphaPC64PCIPinToLineTable[][4]=
+//{
+//    Pin 1 Pin 2 Pin 3 Pin 4
+//    ----- ----- ----- -----
+//    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 0  = PCI_AD[11]
+//    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 1  = PCI_AD[12]
+//    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 2  = PCI_AD[13]
+//    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 3  = PCI_AD[14]
+//    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 4  = PCI_AD[15]
+//    {  0x3,  0x8,  0xc, 0x10 },  // Virtual Slot 5  = PCI_AD[16]  Slot #2
+//    {  0x1,  0x6,  0xa,  0xe },  // Virtual Slot 6  = PCI_AD[17]  Slot #0
+//    {  0x2,  0x7,  0xb,  0xf },  // Virtual Slot 7  = PCI_AD[18]  Slot #1
+//    {  0x5, 0xff, 0xff, 0xff },  // Virtual Slot 8  = PCI_AD[19]  SIO
+//    {  0x4,  0x9,  0xd, 0x11 }   // Virtual Slot 9  = PCI_AD[20]  Slot #3
+//};
+
+ULONG               EB64PPCIPinToLineTable[][4]=
+{
+//    Pin 1 Pin 2 Pin 3 Pin 4
+//    ----- ----- ----- -----
+    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 0  = PCI_AD[11]
+    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 1  = PCI_AD[12]
+    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 2  = PCI_AD[13]
+    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 3  = PCI_AD[14]
+    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 4  = PCI_AD[15]
+    {  0x8, 0xff, 0xff, 0xff },  // Virtual Slot 5  = PCI_AD[16]  SCSI
+    {  0x1,  0x3,  0x5,  0x5 },  // Virtual Slot 6  = PCI_AD[17]  Slot B
+    {  0x2,  0x4,  0x9,  0x9 },  // Virtual Slot 7  = PCI_AD[18]  Slot C
+    {  0x6, 0xff, 0xff, 0xff },  // Virtual Slot 8  = PCI_AD[19]  SIO
+    {  0x7, 0xa, 0xb, 0xb }   // Virtual Slot 9  = PCI_AD[20]  Slot A
+};
+//ULONG               EB64PPCIPinToLineTable[][4]=
+//{
+//    Pin 1 Pin 2 Pin 3 Pin 4
+//    ----- ----- ----- -----
+//    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 0  = PCI_AD[11]
+//    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 1  = PCI_AD[12]
+//    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 2  = PCI_AD[13]
+//    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 3  = PCI_AD[14]
+//    { 0xff, 0xff, 0xff, 0xff },  // Virtual Slot 4  = PCI_AD[15]
+//    {  0x8, 0xff, 0xff, 0xff },  // Virtual Slot 5  = PCI_AD[16]  SCSI
+//    {  0x1,  0x3,  0x5,  0xa },  // Virtual Slot 6  = PCI_AD[17]  Slot #0
+//    {  0x2,  0x4,  0x9,  0xb },  // Virtual Slot 7  = PCI_AD[18]  Slot #1
+//    {  0x6, 0xff, 0xff, 0xff },  // Virtual Slot 8  = PCI_AD[19]  SIO
+//    {  0x7, 0xff, 0xff, 0xff }   // Virtual Slot 9  = PCI_AD[20]  Tulip
+//};
+
diff --git a/private/ntos/nthals/halalp/alpha/vga.c b/private/ntos/nthals/halalp/alpha/vga.c
new file mode 100644
index 000000000..764c585af
--- /dev/null
+++ b/private/ntos/nthals/halalp/alpha/vga.c
@@ -0,0 +1,7 @@
+//
+// This file simply includes the source file from the common Alpha
+// HAL directory.
+//
+
+#include "..\halalpha\vga.c"
+