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| author | Adam <you@example.com> | 2020-05-17 05:51:50 +0200 |
|---|---|---|
| committer | Adam <you@example.com> | 2020-05-17 05:51:50 +0200 |
| commit | e611b132f9b8abe35b362e5870b74bce94a1e58e (patch) | |
| tree | a5781d2ec0e085eeca33cf350cf878f2efea6fe5 /private/ntos/nthals/halast | |
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Diffstat (limited to 'private/ntos/nthals/halast')
59 files changed, 7644 insertions, 0 deletions
diff --git a/private/ntos/nthals/halast/drivesup.c b/private/ntos/nthals/halast/drivesup.c new file mode 100644 index 000000000..38259e5f4 --- /dev/null +++ b/private/ntos/nthals/halast/drivesup.c @@ -0,0 +1,7 @@ +// +// This file simply includes the common sources from the current HAL +// directory. When the structure is finally changed, the real file should +// be in this directory. +// + +#include "..\drivesup.c" diff --git a/private/ntos/nthals/halast/hal.rc b/private/ntos/nthals/halast/hal.rc new file mode 100644 index 000000000..3cba4ad89 --- /dev/null +++ b/private/ntos/nthals/halast/hal.rc @@ -0,0 +1,11 @@ +#include <windows.h> + +#include <ntverp.h> + +#define VER_FILETYPE VFT_DLL +#define VER_FILESUBTYPE VFT2_UNKNOWN +#define VER_FILEDESCRIPTION_STR "Hardware Abstraction Layer DLL" +#define VER_INTERNALNAME_STR "hal.dll" + +#include "common.ver" + diff --git a/private/ntos/nthals/halast/hal.src b/private/ntos/nthals/halast/hal.src new file mode 100644 index 000000000..da778bb9d --- /dev/null +++ b/private/ntos/nthals/halast/hal.src @@ -0,0 +1,7 @@ +// +// This file simply includes the common sources from the current HAL +// directory. When the structure is finally changed, the real file should +// be in this directory. +// + +#include "..\hal.src" diff --git a/private/ntos/nthals/halast/i386/astclock.asm b/private/ntos/nthals/halast/i386/astclock.asm new file mode 100644 index 000000000..9f02059f9 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astclock.asm @@ -0,0 +1,578 @@ + title "Interval Clock Interrupt" +;++ +; +; Copyright (c) 1989 Microsoft Corporation +; Copyright (c) 1992 AST Research Inc. +; +; Module Name: +; +; astclock.asm +; +; Abstract: +; +; This module implements the code necessary to field and process the +; interval clock interrupt. +; +; Author: +; +; Shie-Lin Tzong (shielint) 12-Jan-1990 +; +; Environment: +; +; Kernel mode only. +; +; Revision History: +; +; bryanwi 20-Sep-90 +; +; Add KiSetProfileInterval, KiStartProfileInterrupt, +; KiStopProfileInterrupt procedures. +; KiProfileInterrupt ISR. +; KiProfileList, KiProfileLock are delcared here. +; +; shielint 10-Dec-90 +; Add performance counter support. +; Move system clock to irq8, ie we now use RTC to generate system +; clock. Performance count and Profile use timer 1 counter 0. +; The interval of the irq0 interrupt can be changed by +; KiSetProfileInterval. Performance counter does not care about the +; interval of the interrupt as long as it knows the rollover count. +; Note: Currently I implemented 1 performance counter for the whole +; i386 NT. It works on UP and SystemPro. +; +; John Vert (jvert) 11-Jul-1991 +; Moved from ke\i386 to hal\i386. Removed non-HAL stuff +; +; shie-lin tzong (shielint) 13-March-92 +; Move System clock back to irq0 and use RTC (irq8) to generate +; profile interrupt. Performance counter and system clock use time1 +; counter 0 of 8254. +; +; Quang Phan (v-quangp) 11-Aug-1992 +; Convert to ASTMP system. All processors receive interrupts from the +; system clock and profile interrupts. Added support for the CPU leds. +; +;-- + +.386p + .xlist +include hal386.inc +include callconv.inc +include i386\ix8259.inc +include i386\ixcmos.inc +include i386\kimacro.inc +include mac386.inc +include i386\astmp.inc + .list + + EXTRNP _DbgBreakPoint,0,IMPORT + EXTRNP _KeUpdateSystemTime,0 + EXTRNP _KeUpdateRunTime,1,IMPORT + EXTRNP Kei386EoiHelper,0,IMPORT + EXTRNP _HalEndSystemInterrupt,2 + EXTRNP _HalBeginSystemInterrupt,3 + EXTRNP _HalRequestIpi,1 + EXTRNP _HalpAcquireCmosSpinLock ,0 + EXTRNP _HalpReleaseCmosSpinLock ,0 + EXTRNP _KeSetTimeIncrement,2,IMPORT + extrn _HalpSystemHardwareLock:DWORD + EXTRNP _DisplPanel,1 + extrn _HalpIRQLtoVector:BYTE + extrn _EBI2_CallTab:DWORD + extrn _EBI2_MMIOTable:DWORD +; +; Constants used to initialize timer 0 +; + +TIMER1_DATA_PORT0 EQU 40H ; Timer1, channel 0 data port +TIMER1_CONTROL_PORT0 EQU 43H ; Timer1, channel 0 control port +TIMER1_IRQ EQU 0 ; Irq 0 for timer1 interrupt + +COMMAND_8254_COUNTER0 EQU 00H ; Select count 0 +COMMAND_8254_RW_16BIT EQU 30H ; Read/Write LSB firt then MSB +COMMAND_8254_MODE2 EQU 4 ; Use mode 2 +COMMAND_8254_BCD EQU 0 ; Binary count down +COMMAND_8254_LATCH_READ EQU 0 ; Latch read command + +PERFORMANCE_FREQUENCY EQU 1193182 + +; +; Constants used to initialize CMOS/Real Time Clock +; + +CMOS_STATUS_BUSY EQU 80H ; Time update in progress +RTC_OFFSET_SECOND EQU 0 ; second field of RTC memory +RTC_OFFSET_MINUTE EQU 2 ; minute field of RTC memory +RTC_OFFSET_HOUR EQU 4 ; hour field of RTC memory +RTC_OFFSET_DAY_OF_WEEK EQU 6 ; day-of-week field of RTC memory +RTC_OFFSET_DATE_OF_MONTH EQU 7 ; date-of-month field of RTC memory +RTC_OFFSET_MONTH EQU 8 ; month field of RTC memory +RTC_OFFSET_YEAR EQU 9 ; year field of RTC memory +RTC_OFFSET_CENTURY EQU 32h ; Century field of RTC memory + +; +; ==== Values used for System Clock ==== +; + +; +; Convert the interval to rollover count for 8254 Timer1 device. +; Timer1 counts down a 16 bit value at a rate of 1.193181667M counts-per-sec. +; +; The best fit value closest to 10ms (but not below) is 10.0144012689ms: +; ROLLOVER_COUNT 11949 +; TIME_INCREMENT 100144 +; Calculated error is -.0109472 s/day +; +; The best fit value closest to 15ms (but not above) is 14.9952019ms: +; ROLLOVER_COUNT 17892 +; TIME_INCREMENT 149952 +; Calculated error is -.0109472 s/day +; +; On 486 class machines or better we use a 10ms tick, on 386 +; class machines we use a 15ms tick +; + +ROLLOVER_COUNT EQU 11949 + +_DATA SEGMENT DWORD PUBLIC 'DATA' + +; +; 8254 spinlock. This must be acquired before touching the 8254 chip. +; + public _Halp8254Lock + +_Halp8254Lock dd 0 + +; +; PerfCounter value lock. locks access to the HalpPerfCounterLow/High vars. +; + +_HalpPerfCounterLock dd 0 + + public HalpPerfCounterLow + public HalpPerfCounterHigh +HalpPerfCounterLow dd 0 +HalpPerfCounterHigh dd 0 +HalpPerfCounterInit dd 0 + +_DATA ends + + +_TEXT SEGMENT DWORD PUBLIC 'CODE' + ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING + + page ,132 + subttl "Initialize Clock" +;++ +; +; VOID +; HalpInitializeClock ( +; ) +; +; Routine Description: +; +; This routine initialize system time clock using 8254 timer1 counter 0 +; to generate an interrupt at every 15ms interval at 8259 irq0 +; +; See the definition of TIME_INCREMENT and ROLLOVER_COUNT if clock rate +; needs to be changed. +; +; Arguments: +; +; None +; +; Return Value: +; +; None. +; +;-- +cPublicProc _HalpInitializeClock,0 + + pushfd ; save caller's eflag + cli ; make sure interrupts are disabled + +; +; Set clock rate +; + + mov al,COMMAND_8254_COUNTER0+COMMAND_8254_RW_16BIT+COMMAND_8254_MODE2 + out TIMER1_CONTROL_PORT0, al ;program count mode of timer 0 + IoDelay + mov ecx, ROLLOVER_COUNT + mov al, cl + out TIMER1_DATA_PORT0, al ; program timer 0 LSB count + IoDelay + mov al,ch + out TIMER1_DATA_PORT0, al ; program timer 0 MSB count + + popfd ; restore caller's eflag + +; +; Fill in PCR value with TIME_INCREMENT +; + mov edx, TIME_INCREMENT + stdCall _KeSetTimeIncrement, <edx, edx> + + mov HalpPerfCounterInit, 1 ; Indicate performance counter + ; has been initialized. + stdRET _HalpInitializeClock + +stdENDP _HalpInitializeClock + + page ,132 + subttl "Query Performance Counter" +;++ +; +; LARGE_INTEGER +; KeQueryPerformanceCounter ( +; OUT PLARGE_INTEGER PerformanceFrequency OPTIONAL +; ) +; +; Routine Description: +; +; This routine returns current 64-bit performance counter and, +; optionally, the Performance Frequency. +; +; Note this routine can NOT be called at Profiling interrupt +; service routine. Because this routine depends on IRR0 to determine +; the actual count. +; +; Also note that the performace counter returned by this routine +; is not necessary the value when this routine is just entered. +; The value returned is actually the counter value at any point +; between the routine is entered and is exited. +; +; Arguments: +; +; PerformanceFrequency [TOS+4] - optionally, supplies the address +; of a variable to receive the performance counter frequency. +; +; Return Value: +; +; Current value of the performance counter will be returned. +; +;-- + +; +; Parameter definitions +; + +KqpcFrequency EQU [esp+12] ; User supplied Performance Frequence + +cPublicProc _KeQueryPerformanceCounter,1 + + push ebx + push esi + +; +; First check to see if the performance counter has been initialized yet. +; Since the kernel debugger calls KeQueryPerformanceCounter to support the +; !timer command, we need to return something reasonable before 8254 +; initialization has occured. Reading garbage off the 8254 is not reasonable. +; + cmp HalpPerfCounterInit, 0 + jne Kqpc01 ; ok, perf counter has been initialized + +; +; Initialization hasn't occured yet, so just return zeroes. +; + mov eax, 0 + mov edx, 0 + jmp Kqpc20 + +Kqpc01: +Kqpc11: pushfd + cli +ifndef NT_UP + lea eax, _Halp8254Lock + ACQUIRE_SPINLOCK eax, Kqpc198 +endif + +; +; Fetch the base value. Note that interrupts are off. +; +; NOTE: +; Need to watch for Px reading the 'CounterLow', P0 updates both +; then Px finishes reading 'CounterHigh' [getting the wrong value]. +; After reading both, make sure that 'CounterLow' didn't change. +; If it did, read it again. This way, we won't have to use a spinlock. +; + +@@: + mov ebx, HalpPerfCounterLow + mov esi, HalpPerfCounterHigh ; [esi:ebx] = Performance counter + + cmp ebx, HalpPerfCounterLow ; + jne @b +; +; Fetch the current counter value from the hardware +; + + mov al, COMMAND_8254_LATCH_READ+COMMAND_8254_COUNTER0 + ;Latch PIT Ctr 0 command. + out TIMER1_CONTROL_PORT0, al + IODelay + in al, TIMER1_DATA_PORT0 ;Read PIT Ctr 0, LSByte. + IODelay + movzx ecx,al ;Zero upper bytes of (ECX). + in al, TIMER1_DATA_PORT0 ;Read PIT Ctr 0, MSByte. + mov ch, al ;(CX) = PIT Ctr 0 count. + +ifndef NT_UP + lea eax, _Halp8254Lock + RELEASE_SPINLOCK eax +endif + +; +; Now enable interrupts such that if timer interrupt is pending, it can +; be serviced and update the PerformanceCounter. Note that there could +; be a long time between the sti and cli because ANY interrupt could come +; in in between. +; + + popfd ; don't re-enable interrupts if + nop ; the caller had them off! + jmp $+2 + + +; +; Fetch the base value again. +; + +@@: + mov eax, HalpPerfCounterLow + mov edx, HalpPerfCounterHigh ; [edx:eax] = new counter value + + cmp eax, HalpPerfCounterLow + jne @b + +; +; Compare the two reads of Performance counter. If they are different, +; simply returns the new Performance counter. Otherwise, we add the hardware +; count to the performance counter to form the final result. +; + + cmp eax, ebx + jne short Kqpc20 + cmp edx, esi + jne short Kqpc20 + neg ecx ; PIT counts down from 0h + add ecx, ROLLOVER_COUNT + add eax, ecx + adc edx, 0 ; [edx:eax] = Final result + +; +; Return the counter +; + +Kqpc20: + ; return value is in edx:eax + +; +; Return the freq. if caller wants it. +; + + or dword ptr KqpcFrequency, 0 ; is it a NULL variable? + jz short Kqpc99 ; if z, yes, go exit + + mov ecx, KqpcFrequency ; (ecx)-> Frequency variable + mov DWORD PTR [ecx], PERFORMANCE_FREQUENCY ; Set frequency + mov DWORD PTR [ecx+4], 0 + +Kqpc99: + pop esi ; restore esi and ebx + pop ebx + stdRET _KeQueryPerformanceCounter + +ifndef NT_UP +Kqpc198: popfd + SPIN_ON_SPINLOCK eax,<Kqpc11> +endif + +stdENDP _KeQueryPerformanceCounter + + +;++ +; +; VOID +; HalCalibratePerformanceCounter ( +; IN volatile PLONG Number +; ) +; +; /*++ +; +; Routine Description: +; +; This routine calibrates the performance counter value for a +; multiprocessor system. The calibration can be done by zeroing +; the current performance counter, or by calculating a per-processor +; skewing between each processors counter. +; +; Arguments: +; +; Number - Supplies a pointer to count of the number of processors in +; the configuration. +; +; Return Value: +; +; None. +;-- +cPublicProc _HalCalibratePerformanceCounter,1 + mov eax, [esp+4] ; ponter to Number + pushfd ; save previous interrupt state + cli ; disable interrupts (go to high_level) + + lock dec dword ptr [eax] ; count down + +@@: cmp dword ptr [eax], 0 ; wait for all processors to signal + jnz short @b + + ; + ; Nothing to calibrate on a AST MP machine. There is only a single + ; 8254 device + ; + + popfd ; restore interrupt flag + stdRET _HalCalibratePerformanceCounter + +stdENDP _HalCalibratePerformanceCounter + + + page ,132 + subttl "System Clock Interrupt" +;++ +; +; Routine Description: +; +; +; This routine is entered as the result of an interrupt generated by CLOCK2. +; Its function is to dismiss the interrupt, raise system Irql to +; CLOCK2_LEVEL, update performance counter and transfer control to the +; standard system routine to update the system time and the execution +; time of the current thread +; and process. +; +; +; Arguments: +; +; None +; Interrupt is disabled +; +; Return Value: +; +; Does not return, jumps directly to KeUpdateSystemTime, which returns +; +; Sets Irql = CLOCK2_LEVEL and dismisses the interrupt +; +;-- + ENTER_DR_ASSIST Hci_a, Hci_t + +cPublicProc _HalpClockInterrupt,0 + +; +; Save machine state in trap frame +; + + ENTER_INTERRUPT Hci_a, Hci_t + +; +; (esp) - base of trap frame +; + +; +; dismiss interrupt and raise Irql +; + + movzx eax,_HalpIRQLtoVector[CLOCK2_LEVEL] + push eax + sub esp, 4 ; allocate space to save OldIrql + +; esp - OldIrql + stdCall _HalBeginSystemInterrupt,<CLOCK2_LEVEL,eax,esp> + or al,al ; check for spurious interrupt + jz Hci100 + +; +; Update performance counter +; + cmp fs:PcHal.PcrEBI2ProcessorID, 0 + jnz short @f + + add HalpPerfCounterLow, ROLLOVER_COUNT ; update performace counter + adc HalpPerfCounterHigh, 0 + +@@: +; +; Check for Idle state and log processor state to the front panel CPU leds. +; + inc fs:PcHal.PcrCpuLedRateCount + cmp fs:PcHal.PcrCpuLedRateCount, CpuLedSamplingRate + jne Hci010 ; Don't update LED yet + mov fs:PcHal.PcrCpuLedRateCount,0 ;reset rate count + mov edx, fs:PcPrcb + mov eax, [edx].PbIdleThread + cmp eax, [edx].PbCurrentThread + je ProcIdle + CALL_EBI2 LogProcBusy,1 + jmp Hci010 +ProcIdle: + CALL_EBI2 LogProcIdle,1 + +Hci010: +; +; (esp) = OldIrql +; (esp+4) = Vector +; (esp+8) = base of trap frame +; (ebp) = address of trap frame +; (eax) = time increment +; + mov eax, TIME_INCREMENT + + cmp fs:PcHal.PcrEBI2ProcessorID, 0 ; is this the master cpu? + je _KeUpdateSystemTime@0 ; if it is, update system time + + sti + stdCall _KeUpdateRunTime,<dword ptr [esp]> ; othewise update runtime + + INTERRUPT_EXIT ; lower irql to old value, iret + +Hci100: + add esp, 8 ; spurious, no EndOfInterrupt + SPURIOUS_INTERRUPT_EXIT ; exit interrupt without eoi + +stdENDP _HalpClockInterrupt + +;++ +; +; ULONG +; HalSetTimeIncrement ( +; IN ULONG DesiredIncrement +; ) +; +; /*++ +; +; Routine Description: +; +; This routine initialize system time clock to generate an +; interrupt at every DesiredIncrement interval. +; +; Arguments: +; +; DesiredIncrement - desired interval between every timer tick (in +; 100ns unit.) +; +; Return Value: +; +; The *REAL* time increment set. +;-- +cPublicProc _HalSetTimeIncrement,1 + + mov eax, TIME_INCREMENT + stdRET _HalSetTimeIncrement + +stdENDP _HalSetTimeIncrement + + +_TEXT ends + end + diff --git a/private/ntos/nthals/halast/i386/astdetct.c b/private/ntos/nthals/halast/i386/astdetct.c new file mode 100644 index 000000000..cf2c00e90 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astdetct.c @@ -0,0 +1,169 @@ +/*++ + +Copyright (c) 1992 AST Research Inc. + +Module Name: + + astdetct.c + +Abstract: + + +Author: + + Bob Beard (v-bobb) 24-Jul-1992 + +Environment: + + Kernel mode only. + +Revision History: + + Bob Beard (v-bobb) 19-Aug-1992 detect if MP + Quang Phan (v-quangp) 27-Aug-1992 modified to work with the NT Setup + program. + +--*/ + +#ifndef _NTOS_ +#include "nthal.h" +#endif + +#include "halp.h" +#include "astebiii.h" + +#define AST_MANUFACTURER_ID 0x0674 +#define AST_EBI2_STRING 0x32494245 + +ULONG ProcCount; +//#define MAX_EBI_SLOTS 32L +//VOID* EBI2_MMIOTable[MAX_EBI_SLOTS]; + +// +// EBI_II function offset table +// + +EBI_II EBI2_CallTab; + +// +// Global pointer to BIOS +// + +PVOID BiosPtr; + +BOOLEAN +GetProcCount() +/*++ + +Routine Description: + Call EBI2 to get the number of processors in the system. + To make this call work with the NT current Setup environment, + (memory address limited to 16MB), a fake MMIOTable is passed to EBI. + ProcCount contains the number of processors in the system. + +Arguments: + none. + +Return Value: + True if successfully initialized. False otherwise. + +--*/ +{ + +ULONG i; +ULONG *Alias = (ULONG *)&EBI2_CallTab; +ebi_iiSig *Sig = (ebi_iiSig*)((ULONG)BiosPtr + EBI_II_SIGNATURE); +ULONG *OffTab; + +// +// Build the EBI II offset table +// + + OffTab =(ULONG *) ((ULONG)BiosPtr + (REAL_TO_LIN(Sig->seg,Sig->off) - + REAL_TO_LIN(BIOS_SEG, 0))); + for( i = 0; i < ( sizeof( offsetTable ) / sizeof( ULONG )); i++ ) + Alias[i] = OffTab[i] + (ULONG)BiosPtr; + +// +// Find out the number of good processors +// + +if ( (EBI2_CallTab.GetNumProcs)( (VOID *) 0, &ProcCount ) ) + return(FALSE); + + return(TRUE); +} + + + +ULONG +DetectAST( + OUT PBOOLEAN IsConfiguredMp +) +/*++ + +Routine Description: + Determine on which AST platform we are running. Special HAL is needed + for EBI II based AST machines. + +Arguments: + PBOOLEAN IsConfiguredMp returns with value of TRUE if MP. FALSE if + UP. + +Return Value: + Boolean that indicates if AST EBI II platform is detected. TRUE means + an AST EBI II platform was detected. FALSE indicates it was not. + + +--*/ +{ + +USHORT ManufacturerId; +PULONG EBI2StringPtr; +ULONG ProcCount; +UCHAR ProductId; + +// +// Read the EISA ManufactuerID and check for AST +// + +ManufacturerId = (((USHORT)(READ_PORT_UCHAR((PUCHAR)0xc80))) << 8) + | (READ_PORT_UCHAR((PUCHAR)0xc81)); +if (ManufacturerId != AST_MANUFACTURER_ID) + return(FALSE); + +// +//This HAL works with Manhattans that have EISA's ProductId 0x40-0x4F. +// + +ProductId = ((READ_PORT_UCHAR((PUCHAR)0xc82))); +if ((ProductId & 0xF0) != 0x40) + return(FALSE); + +// +// Map in all of AST BIOS for EBI II calls +// + +BiosPtr = (PVOID)((ULONG)REAL_TO_LIN( BIOS_SEG, 0 )); +BiosPtr = HalpMapPhysicalMemory(BiosPtr, 0x10000/PAGE_SIZE); // assumes PAGE_SIZE <= 64k +if (BiosPtr == NULL) + return(FALSE); + +EBI2StringPtr = (PULONG)((ULONG)BiosPtr + EBI_II_SIGNATURE); +if (*EBI2StringPtr != AST_EBI2_STRING) + return(FALSE); + +// +// Call EBI II to get num. of processors +// +if (!GetProcCount()) + return(FALSE); + +// +// This is an MP hal +// + + *IsConfiguredMp = TRUE; + +return(TRUE); +} diff --git a/private/ntos/nthals/halast/i386/astdisp.h b/private/ntos/nthals/halast/i386/astdisp.h new file mode 100644 index 000000000..36a78f35c --- /dev/null +++ b/private/ntos/nthals/halast/i386/astdisp.h @@ -0,0 +1,59 @@ +/*++ + +Copyright (c) 1992 AST Research Inc. + +Module Name: + + astdisp.h + +Abstract: + + Display codes for debugging of AST HAL and AST EBI errors. + +Author: + + Bob Beard (v-bobb) 25-Jul-1992 + +Environment: + + +Revision History: + +--*/ + +VOID DisplPanel(ULONG x); + +#ifdef BBTEST +// Debugging codes 0x00 - 0x9f +#define HALEnterDetect 0x01 +#define HALASTMachineDetected 0x02 +#define HALBIOSMappedOK 0x03 +#define HALBIOSSignatureOK 0x04 + +#define HALEnterEBIInit 0x05 +#define HALInitMMIOTable 0x06 +#define HALExitEBIInit 0x07 + +#define HALInitIpi 0x08 +#define HALInitIpiExit 0x09 +#define HALDoRequestIPI 0x0a +#define HALInitInterrupts 0x0b +#define HALEnterASTHAL 0x0c +#define HALExitASTHAL 0x0d +#define HALEnterInitMp 0x0e +#endif + +// Error codes 0xa0 - 0xff +#define HALSlotProblem 0xa0 +#define HALMMIOProblem 0xa1 +#define HALPhysicalAllocProblem 0xa2 +#define HALEBIInitProblem 0xa3 +#define HALEBIGetProcProblem 0xa4 +#define HALEBINoProcsProblem 0xa5 +#define HALMemoryProblem 0xa6 +#define HALIpiInitVecProblem 0xa7 +#define HALIpiInitIDProblem 0xa8 +#define HALIntSubsystemProblem 0xa9 +#define HALCacheEnableProblem 0xaa +#define HALSpiInitVecProblem 0xab +#define HALGetRevisionProblem 0xac diff --git a/private/ntos/nthals/halast/i386/astebi.c b/private/ntos/nthals/halast/i386/astebi.c new file mode 100644 index 000000000..95903b5a5 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astebi.c @@ -0,0 +1,181 @@ +/*++ + +Copyright (c) 1992 AST Research Inc. + +Module Name: + + astebi.c + +Abstract: + + NT HAL to AST EBI2 translation file. This file contains routines that + convert NT HAL calls to AST EBI2 calls. + +Author: + + Bob Beard (v-bobb) 24-Jul-1992 + +Environment: + + Kernel mode only. + +Revision History: + Quang Phan (v-quangp) 27-Aug-1992: Moved DisplPanel from astdetct.c + into to this module because astdetct is also used for the NT setup + program. + +--*/ + +#include "halp.h" +#include "astebiii.h" +#include "astdisp.h" + +extern VOID* EBI2_MMIOTable[]; +extern EBI_II EBI2_CallTab; + +#define IRQ0_VECTOR_BASE PRIMARY_VECTOR_BASE +#define ALL_IRQS (0x0000fffb) +#define ALL_PROCS (0xffffffff) + +static UCHAR hex_to_asc(SHORT x) +{ + return(x < 0xa ? x+'0' : x-10+'A'); +} + + +VOID +HalpInitializePICs() +/*++ + +Routine Description: + Initialize the AST Interrupt environment. Called once by P0 during + Phase 0. + +Arguments: + none. + +Return Value: + NONE + +--*/ +{ + + dWord subsystemType; + + // + // Turn off all interrupts while setting the interrupt environment + // + + _asm pushfd + _asm cli + + // + // Check to see the type of interrupt subsystem + // + + EBI2_CallTab.GetIntSubsysType( EBI2_MMIOTable, &subsystemType ); + if ( subsystemType != EBI_INT_SUBSYS_ADI) + DisplPanel(HALIntSubsystemProblem); + + // + // Set the IRQ vectors 0 & 8 + // + + if ( EBI2_CallTab.SetIRQVectorAssign( EBI2_MMIOTable, 0, IRQ0_VECTOR_BASE) ) + DisplPanel(HALIntSubsystemProblem); + if ( EBI2_CallTab.SetIRQVectorAssign( EBI2_MMIOTable, 8, IRQ0_VECTOR_BASE+8) ) + DisplPanel(HALIntSubsystemProblem); + + // + // Mask off all Interrupts for All Processors Globally + // ( Except chain interrupt, IPI and SPI ) + // + + if ( EBI2_CallTab.SetGlobalIntMask( EBI2_MMIOTable, ALL_IRQS) ) + DisplPanel(HALIntSubsystemProblem); + + // + // Switch to Distributed Interrupt Handling + // + + EBI2_CallTab.SetAdvIntMode( EBI2_MMIOTable ); + + // + // Cancel all pending interrupts (except IPI and SPI) + // + + if ( EBI2_CallTab.CancelInterrupt( EBI2_MMIOTable, ALL_IRQS, ALL_PROCS) ) + DisplPanel(HALIntSubsystemProblem); + + // + // Return interrupts to entry state + // + + _asm popfd + +} + + +VOID +ASTEnableCaches() +/*++ + +Routine Description: + Enable the internal and external caches of the processor that calls + this routine. + +Arguments: + none. + +Return Value: + NONE + +--*/ +{ + + if ( EBI2_CallTab.DisableRAMCache( EBI2_MMIOTable ) ) + DisplPanel(HALCacheEnableProblem); + + if ( EBI2_CallTab.EnableRAMCache( EBI2_MMIOTable ) ) + DisplPanel(HALCacheEnableProblem); + +} + + +VOID +DisplPanel(ULONG x) +/*++ + +Routine Description: + Display 2 hex digits on front panel of AST Manhattan. All digits + are preceded by a "H " (H blank) to indicate HAL output. + +Arguments: + A SHORT value to output as hex digits. + +Return Value: + none. + +--*/ +{ +UCHAR digit1,digit2; + +#define DISP_ADR (PUCHAR) 0xec +#define DISP_DAT (PUCHAR) 0xed + + digit1 = hex_to_asc((SHORT)((x & 0xf0) >> 4)); + digit2 = hex_to_asc((SHORT)(x & 0x0f)); + +// digit 4 + WRITE_PORT_UCHAR(DISP_ADR, 7); + WRITE_PORT_UCHAR(DISP_DAT, 'H'); +// digit 3 + WRITE_PORT_UCHAR(DISP_ADR, 6); + WRITE_PORT_UCHAR(DISP_DAT, ' '); +// digit 2 + WRITE_PORT_UCHAR(DISP_ADR, 5); + WRITE_PORT_UCHAR(DISP_DAT, digit1); +// digit 1 + WRITE_PORT_UCHAR(DISP_ADR, 4); + WRITE_PORT_UCHAR(DISP_DAT, digit2); +} diff --git a/private/ntos/nthals/halast/i386/astebi2.inc b/private/ntos/nthals/halast/i386/astebi2.inc new file mode 100644 index 000000000..3f8343327 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astebi2.inc @@ -0,0 +1,1227 @@ +; +;~~~ +; 06/16/92 Added an error message and few equates to help +; with the UPS LED translation. +; +;~~~ +; 06/08/92 Updating EBI II to meet the 2.8 EBI II specification. +; Adding Multi-threading support for EBI II +; +;~~~ +; 5/21/92 Reved version of EBI implementation to 2.8 +; Support for specific EOI. +; A number of new equates. +; +;~~~ +; 4/28/92 MPX updates. +; +; Added IRQ0_Vector and IRQ8_Vector to EBI 2 memory +; structure. +; +; created a macro EDI_EBI_MEM_ADD +; +; Added an IPI_ID_Valid_Mask +; +;~~~ +; +; 4/17/92 +; +; Added Bios Time out Bit mask in NMICR +; Added SMEARRegister entry to the EBI 2 memory structure. +; +;~~~ +; 4/15/92 Coding OEM0 function to help NMI generation and +; debugging. +; +;~~~ +; 4/13/92 Updating this module to reflect the new EBI II Spec rel +; 2.7. +; All functions will be re-arranged. This file will +; contain all EBI II functions need for the SCO EFS +; Implementation. Refer to EBI2STAT.DOC for a +; condensed list of these functions. +; +;~~~ +; 4/2/92 Added more equates, new error messages. +; +;~~~ +; 3/20/92 Added new equates and MemTable_To_Edi macro +; +;~~~ +; 3/16/92 Adding more EBI 2 functionality to support the SCO +; EFS implementation. +;~~~ + + +;***************************************************************************** +; Compilation debugging switches +;***************************************************************************** +;SIMULATE_MANHATTAN EQU 1 +;SIMULATE_MPSYSTEM EQU 1 +;FAKE_MMIOTABLE EQU 1 +DELETED_FUNCTIONS EQU 1 ;a flag to not compile the functions + ;that were in an older rev of the + ;EBI II spec but no longer are + ;needed. +;UGLY EQU 1 + +;***************************************************************************** +; Declare Equates +;***************************************************************************** + +; +;Equates for the AST OEM call Set_Irq13_Latch +; + +SET_IRQ13_LATCH equ 6 ;subfunc# +IRQ13_LATCH_ON equ 1 +IRQ13_LATCH_OFF equ 0 + +; +; The structure and the definitions for the new local int mask call +; + +PORT_TYPE_MASK equ 3 +PORT_TYPE_MEMORY equ 0 +PORT_TYPE_IO equ 1 + +PORT_WIDTH_MASK equ 01CH +EIGHT_BIT_PORTS equ 000H +SIXTEEN_BIT_PORTS equ 004H +THIRTY_TWO_BIT_PORT equ 008H + +;Function return successfull codes. +OK equ 0 +PROC_RUNNING equ 1 +PROC_STOPPED equ 2 +PROC_NO_CACHE equ 3 +NO_MEMORY_ERRORS EQU 4 ;No RAM errors were found +MEMORY_ERRORS_FOUND EQU 5 ;Hardware detected a RAM error. +WRONG_GRAPH_MODE EQU 6 ;can not write to Graph Mode in this mode. + +;Function return ERROR codes +ERR_BAD EQU 0FFFFFFFFH ;-1 +ERR_NOT_SUPPORTED EQU 0FFFFFFFEH ;-2 +ERR_NONESUCH EQU 0FFFFFFFDH ;-3 +ERR_BAD_PROC_ID EQU 0FFFFFFFCH ;-4 +ERR_PROC_ABSENT EQU 0FFFFFFFBH ;-5 +ERR_PROC_BAD EQU 0FFFFFFFAH ;-6 +ERR_UNKNOWN_INT EQU 0FFFFFFF9H ;-7 +ERR_DISPLAY_OVERFLOW EQU 0FFFFFFF8H ;-8 +ERR_BAD_CHARS EQU 0FFFFFFF7H ;-9 +ERR_BAD_SELECTOR EQU 0FFFFFFF6H ;-10 +ERR_BAD_CACHE_MODE EQU 0FFFFFFF5H ;-11 +ERR_BAD_VECTOR EQU 0FFFFFFF4H ;-12 +ERR_BAD_COLOR EQU 0FFFFFFF3H ;-13 +ERR_BAD_GRAPH_MODE EQU 0FFFFFFF2H ;-14 +ERR_BAD_BOARD_NUM EQU 0FFFFFFF1H ;-15 +ERR_BAD_MODULE_NUM EQU 0FFFFFFF0H ;-16 +ERR_BAD_IRQ_NUM EQU 0FFFFFFEFH ;-17 +ERR_BAD_OFFSWITCH EQU 0FFFFFFEEH ;-18 +ERR_BAD_PHYS_ADDR EQU 0FFFFFFEDH ;-19 +ERR_BAD_LENGTH EQU 0FFFFFFECH ;-20 +ERR_BAD_BLOCK_NUM EQU 0FFFFFFEBH ;-21 +ERR_BAD_GLOB_MASK_IRQ EQU 0FFFFFFEAH ;-22 +ERR_BAD_LOC_MASK_IRQ EQU 0FFFFFFE9H ;-23 +ERR_CANT_CANCEL_INT EQU 0FFFFFFE8H ;-24 +ERR_PROC_STILL_RUNNING EQU 0FFFFFFE7H ;-25 +ERR_BAD_POWER_SUPPLY_NUM EQU 0FFFFFFE6H ;-26 +ERR_BAD_FRONT_PANEL_MODE EQU 0FFFFFFE5H ;-27 +ERR_MULTI_TIME_OUT EQU 0FFFFFFE4H ;-28 +ERR_FRONT_PANEL_DISABLED EQU 0FFFFFFE3H ;-29 + +;OEM function error return codes +OEM0_ERR_BAD_EISA_REF EQU 0FFFF0000H ; 0 +OEM0_ERR_BAD_COM2_OVERRIDE EQU 0FFFEFFFFH ; 1 +OEM0_ERR_BAD_GEN_MULTIBIT EQU 0FFFEFFFEH ; 2 +OEM0_ERR_BAD_GEN_SINGLEBIT EQU 0FFFEFFFDH ; 3 +OEM0_ERR_BAD_IRQ13_LATCH EQU 0FFFEFFFCH ; 4 +OEM0_ERR_BAD_CACHE_MODE EQU 0FFFEFFFBH ; 5 + +;OEM completion codes. +OEM0_INFO_BANK_ABSENT EQU 10000 ;0 + +;ERR_BAD EQU 0FFFFFFFFH ;-1 +;ERR_NOT_SUPPORTED EQU 0FFFFFFFEH ;-2 +;ERR_NONESUCH EQU 0FFFFFFFDH ;-3 +;ERR_INVALID_PROC_ID EQU 0FFFFFFFCH ;-4 +;ERR_PROC_ABSENT EQU 0FFFFFFFBH ;-5 +;ERR_PROC_BAD EQU 0FFFFFFFAH ;-6 +;ERR_UNKNOWN_NMI EQU 0FFFFFFF9H ;-7 +;ERR_DISPLAY_OVERFLOW EQU 0FFFFFFF8H ;-8 +;ERR_BAD_CHARS EQU 0FFFFFFF7H ;-9 +;ERR_BAD_SELECTOR EQU 0FFFFFFF6H ;-10 +;ERR_BAD_CACHE_MODE EQU 0FFFFFFF5H ;-11 +;ERR_BAD_VECTOR EQU 0FFFFFFF4H ;-12 +;ERR_BAD_COLOR EQU 0FFFFFFF3H ;-13 +;ERR_BAD_GRAPH_MODE EQU 0FFFFFFF2H ;-14 +;ERR_INVALID_BOARD_NUM EQU 0FFFFFFF1H ;-15 +;ERR_INVALID_MODULE_NUM EQU 0FFFFFFF0H ;-16 +;ERR_INVALID_IRQ_NUM EQU 0FFFFFFEFH ;-17 +;ERR_INVALID_OFFSWITCH_MODE EQU 0FFFFFFEEH ;-18 +;ERR_INVALID_PHYS_ADR EQU 0FFFFFFEDH ;-19 +;ERR_INVALID_LENGTH EQU 0FFFFFFECH ;-20 +;ERR_INVALID_BLOCK_NUM EQU 0FFFFFFEBH ;-21 +;ERR_INVALID_GLOB_MASK_IRQ EQU 0FFFFFFEAH ;-22 +;ERR_INVALID_LOC_MASK_IRQ EQU 0FFFFFFE9H ;-23 +;ERR_CANT_CANCEL_INT EQU 0FFFFFFE8H ;-24 +;ERR_INVALID_EISA_REF EQU 0FFFFFFE7H ;-25 +;ERR_INVALID_COM2_OVER EQU 0FFFFFFE6H ;-26 +;ERR_INVALID_GEN_MULTI EQU 0FFFFFFE5H ;-27 +;ERR_INVALID_GEN_SINGLE EQU 0FFFFFFE4H ;-28 +;ERR_INVALID_IRQ13_LATCH EQU 0FFFFFFE3H ;-29 + +;NMI and SPI SOURCE equates +NMI_SRC_NONE EQU 0 ;No source was found +;1 is reserved. +NMI_SRC_LOCALSOFTNMI EQU 2 ;Software generated NMI +NMI_SRC_MEM EQU 3 ;Memory Double bit ECC error +NMI_SRC_PROCESSOR EQU 4 ;PROCESSOR error. +;5 is reserved. +NMI_SRC_SYS_PARITY EQU 6 ;System bus Parity, address or data +NMI_SRC_SYS_TIMEOUT EQU 7 ;System bus timeout. +NMI_SRC_SHUTDOWN EQU 8 ;Shutdown Button. +NMI_SRC_ATTENTION EQU 9 ;Attention Button. +NMI_SRC_POWERFAIL EQU 0AH ;Power Fail. +NMI_SRC_EISA_FAIL_SAFE EQU 0BH ;Eisa Fail safe timer error +NMI_SRC_EISA_BUSTIMEOUT EQU 0CH ;EISA Bus timeout +NMI_SRC_EISA_IOCHECK EQU 0DH ;EISA IO Check +NMI_SRC_EISA_SWGEN EQU 0EH ;EISA software generated NMI +NMI_SRC_SYS_IO EQU 0FH ;System I/O error + +NMI_SRC_MASK EQU 7 ;Mask for bits 0 - 2. + +;Interrupt Subsystem Type +INT_SUBSYS_EISA EQU 0 ;EISA interrupt subsystem type. +INT_SUBSYS_ISA EQU 1 ;ISA interrupt subsystem type. +INT_SUBSYS_ADI EQU 2 ;ADI interrupt subsystem type. +INT_SUBSYS_MPIC EQU 3 ;MPIC interrupt subsystem type. + +INT_MODE_BYPASS EQU 1 ;Bypass mode flag. +INT_MODE_ADI EQU 2 ;Advanced Distributed int. mode + +IVR_0_ADR EQU 20H ;I/O port for 8259 Init. Master. +IVR_8_ADR EQU 0A0H ;I/O port for 8259 Init. Slave. +IVR_0_EISA_ADR EQU 4D0H ;EISA 8259 I/O port for Master. +IVR_8_EISA_ADR EQU 4D1H ;EISA 8259 I/O port for Slave. +IMR_0_ADR EQU 21H ;I/O port address for IRQ 0 - 7 +IMR_8_ADR EQU 0A1H ;I/O prot address for IRQ 8 - 15 +IRQ_MAX EQU 15 ;Highest IRQ number supported. +ICW1_MASK EQU 11H ;8259 ICW1 settings. Cascade Mode +ICW3_MASK_MASTER EQU 4 ;8259 ICW3 settings. Slave is on IRQ2 +ICW3_MASK_SLAVE EQU 2 ;8259 ICW3 settings. Slave ID +ICW4_MASK EQU 1 ;8259 ICW4 settings. 8086 mode, Normal + ;EOI, fully nested mode, non buffered. + +OCW2_MASK EQU 60H ;Specific EOI Mask, bit 0-2 should + ;be the irq number. +IRQ2_EOI_MASK EQU 62H ;Mask command to EOI IRQ 2. +READ_ISR_COM EQU 0BH ;command to 8259 to read ISR +READ_IRR_COM EQU 0AH ;command to 8259 to read IRR + +MAX_SPI_VECTOR EQU 255 ;Maximum SPI Vector number currently + ;supported by our hardware. +MAX_IPI_VECTOR EQU 255 ;Maximum IPI Vector number currently + ;supported by our hardware. + +;EISA EOI registers +NMISTATUSREG EQU 61H +MIENABLEREG EQU 70H +EXTENDEDNMIREG EQU 461H + +; + +;Bit positions. +BIT_0 EQU 01H +BIT_1 EQU 02H +BIT_2 EQU 04H +BIT_3 EQU 08H +BIT_4 EQU 10H +BIT_5 EQU 20H +BIT_6 EQU 40H +BIT_7 EQU 80H +BIT_8 EQU 0100H +BIT_9 EQU 0200H +BIT_10 EQU 0400H +BIT_11 EQU 0800H +BIT_12 EQU 1000H +BIT_13 EQU 2000H +BIT_14 EQU 4000H +BIT_15 EQU 8000H + + ;The Bits that are set(1) indicated that such an interrupt + ;is supported in the Interrupt Mask Bitmap Definition. +LOCAL_INT_VALID_MASK EQU 0700FFFFH +GLOBAL_INT_VALID_MASK EQU 0000FFFFH +CANCEL_INT_VALID_MASK EQU 0100FFFFH + +IRQ0_IRQ15_MASK EQU 0000FFFFH +IPI_ID_VALID_MASK EQU 0FFFFFF00H +SPI_INT_MASK EQU 01000000H +LSI_INT_MASK EQU 02000000H +IPI_INT_MASK EQU 04000000H +CLRSPI EQU BIT_2 ;clear SPI bit in ICR regs. + ;bit definition in the ADI for ISR and IRR for following Interrupts. +LSI_ADI_IR_BIT EQU BIT_5 +LSI_ADI_IS_BIT EQU BIT_5 +IPI_ADI_IR_BIT EQU BIT_6 +IPI_ADI_IS_BIT EQU BIT_6 +SPI_ADI_IR_BIT EQU BIT_7 +SPI_ADI_IS_BIT EQU BIT_7 + +TRUE EQU 01H ;Boolean True. +FALSE EQU 00H ;Boolean False. + +ADIEOI_MASK EQU 40h ;bit 6 of ICR +IGN_IPI EQU 08h ;IPI ignore bit in the ICR + +SWNMI EQU BIT_0 ;Software NMI bit in NMICR +SIOEM EQU BIT_1 ;SIOEM in NMICR +BTEM_BIT EQU BIT_2 ;BTEM in NMICR + +IOI_IR EQU BIT_3 ;in IRR register. + +BYP_BIT EQU BIT_7 ;in CMCR + +MASTER_BIT EQU BIT_7 ;in ICR + +ENABLE_INT EQU BIT_2 ;in CMCR + +;Type of ECC error from a memory board. This will be the values +;returned to the caller in the memErrFlags. +MEM_ERR_PARITY EQU 1 ;memory parity error. +MEM_ERR_SINGLE_BIT EQU 2 ;memory single bit ECC error. +MEM_ERR_MULTI_BIT EQU 3 ;memory Multi bit ECC error. +MEM_ERR_INDETERMINTE EQU 0FFFFFFFFH ;-1 Info requested in indeterminate. +INDETERMINITE EQU 0FFFFFFFFH ;-1 + +ZERO EQU 0 +ONE EQU 1 ;Decimal One. +TWO EQU 2 +THREE EQU 3 +FOUR EQU 4 +SIXTY4_KB EQU 10000H ;64 K Bytes. +Sixteen_KB EQU 4000H ;16 KB bytes +ONE_MB EQU 100000H ;1 MB. +Eight_MB EQU 800000H ;8 MB. +Sixteen_MB EQU 1000000H ;16 MB. +Thirty2_MB EQU 2000000H ;32 MB. +NEGONE EQU 0FFFFFFFFH ;-1 + +CPUBOARD_SETABLEREGS EQU 10000H ;Offset to the CPU board + ;settable registers from + ;the base address for the + ;slot it currently occupies. +MEMBOARD_SETABLEREGS EQU 10100H ;Offset to the memory board + ;settable registers from the base + ;of DISTC address. + +VALID_UPS_LEDCOLORS EQU 3 ;highest color setting +VALID_OFFSWITCH_MODES EQU 1 ;highest off switch mode setting +VALID_CACHE_CONTROL_MODES EQU 1 ;highest cache control mode setting +VALID_FRONT_PANEL_MODES EQU 1 ;highest valid front panel modes. + +ENABLE_FRONT_PANEL_INT EQU 1 ;enable front panel mode command. + +FIRST_PAIR_SIMMS EQU 10H ;Mem Config mask indicating +SECOND_PAIR_SIMMS EQU 20H ;which pair of SIMMS are +THIRD_PAIR_SIMMS EQU 40H ;present on the current +FOURTH_PAIR_SIMMS EQU 80H ;memory board. + +MEM_BOARD_RESERVED EQU 0 ;reseved equate for mem board + +CACHE_READ_ONLY equ 1 ; Selectable cache modes. +CACHE_WRITE_THRU equ 2 ; Mode 0 is default, which +CACHE_WRITE_BACK equ 3 ; is NOT readonly and write +CACHE_READ_WRITE equ 4 ; back. + +ASCII_ALPHA_NUM_DISP equ 1 ; Code for full ASCII display. +ASCII_ALPHA_NUM_WID equ 4 ; Number of chars on FP disp. +ATTENTION_MASK equ 20h ; Mask for attention button. + +CACHE_MASK equ 0ch ; Mask for bits 2,3. +CACHE_RDONLY_MASK equ 4 ; Mask for bit 2 of CMMS reg. +CACHE_WR_THRU_MASK equ 8 ; Mask for bit 3 of CMMS reg. +DISABLE_CACHE equ 60000000h ; Set bits 29, 30 of CR0. +CACHE_MODE_VALID EQU 07H ; valid mode masks. +CACHE_MODE_MASK EQU 1CH ; CMMS cache mode mask. + +EBI_2_MAJOR equ 02h ; Revision 02.08.01 +EBI_2_MINOR equ 08h ; of the EBI II Specification. +EBI_2_ZZ equ 01h + +FLUSH_MODE_MASK equ 3 ; Mask for bits 0,1. +FP_MODE_MASK equ 1 ; Mask for bit 0. +FP_SHUTDWN equ 80h ; Bit position for shutdown. +FP_ENABLE_SHUTDOWN EQU 40h ;bit possition for enabling shutdown +FP_THERMAL_MASK equ 10h ; Mask for bit 4. +MAX_FP_DIGITS equ 4 ; 4-digit ASCII display. +MEM_MAP_IO_BASE_ADDR equ 0d0000000h ; Start of hw i/o addresses. +MEM_MAP_IO_SIZE equ 10000000h ; Size used for hw i/o. +MEM_MAX_BANKS equ 4 ;max # of banks per mem board. +MP_SPECIFIC_EOI equ 60h ; Sends specific EOI to PIC. +FP_INTMODE_DISABLED EQU 0 ;indicates front panel interr + ;mode is disabled. + +KEYLOCK_LOCKED_HW EQU 6 +KEYLOCK_SERVICE_HW EQU 5 +KEYLOCK_UNLOCK_HW EQU 3 +KEYLOCK_OFF_HW EQU 7 + +KEYLOCK_LOCKED_SW EQU 0 +KEYLOCK_SERVICE_SW EQU 1 +KEYLOCK_UNLOCK_SW EQU 2 +KEYLOCK_OFF_SW EQU 3 + + +NUM_KEY_POSITIONS equ 4 ; FP has 4 key positions. +KEYLOCK_MASK equ 7 ; KEYLOCK POSITION MASK +SHUTDOWN_MASK equ 8 ; Mask for bit 3. +SHUTDOWN_NMI_SRC equ 8 ; Numerical equiv for OFF btn. +TIMER_FREQ equ 1000 ; Hard code to 1000 KHz. +UPS_LED_MASK equ 30h ; Mask for bits 4,5. +NULL equ 0 + + +;hardware led setting. +UPS_HARD_DARK EQU 0 +UPS_HARD_RED EQU 2 +UPS_HARD_GREEN EQU 1 +UPS_HARD_AMBER EQU 3 + +;EBI II specified led setting. +UPS_EBI_DARK EQU 0 +UPS_EBI_RED EQU 1 +UPS_EBI_GREEN EQU 2 +UPS_EBI_AMBER EQU 3 + +REGIONAL_CACHE_CONTROL_ENABLED EQU 1 ;Cache control flag. +CACHE_CONTROL_GRANULARITY EQU 100000H;Current granularity is 1MB + +EBI2_MEM_ENTRY EQU 16 ;This is the entry number for + ;EBI II memory in the MMIO + ;Table. 0 based table. +EBI2_MEM_LENGTH EQU 400H ;1KB of RAM + + +VALID_GRAPH_MODES EQU 2 ;highest graph mode setting +FP_HISTOGRAM EQU 0H ;currently definied Front +FP_STATUS EQU 1H ;panel Graph Modes. +FP_OVERRIDE EQU 2H ; + + + +IRQ_0 EQU 0 ;PIC #1 (Master) +IRQ_1 EQU 1 ;PIC #1 (Master) +IRQ_2 EQU 2 ;Inaccessable in cascaded PIC system +IRQ_3 EQU 3 ;PIC #1 (Master) +IRQ_4 EQU 4 ;PIC #1 (Master) +IRQ_5 EQU 5 ;PIC #1 (Master) +IRQ_6 EQU 6 ;PIC #1 (Master) +IRQ_7 EQU 7 ;PIC #1 (Master) +IRQ_8 EQU 8 ;PIC #2 (1st slave) +IRQ_9 EQU 9 ;PIC #2 (1st slave) +IRQ_10 EQU 10 ;PIC #2 (1st slave) +IRQ_11 EQU 11 ;PIC #2 (1st slave) +IRQ_12 EQU 12 ;PIC #2 (1st slave) +IRQ_13 EQU 13 ;PIC #2 (1st slave) +IRQ_14 EQU 14 ;PIC #2 (1st slave) +IRQ_15 EQU 15 ;PIC #2 (1st slave) +IRQ_16 EQU 16 ;Unused. +IRQ_17 EQU 17 ;Unused. +IRQ_18 EQU 18 ;Unused. +IRQ_19 EQU 19 ;Unused. +IRQ_20 EQU 20 ;Unused. +IRQ_21 EQU 21 ;Unused. +IRQ_22 EQU 22 ;Unused. +IRQ_23 EQU 23 ;Unused. +IRQ_24 EQU 24 ;SPI (See below) +IRQ_25 EQU 25 ;LSI (See below) +IRQ_26 EQU 26 ;IPI (See below) +IRQ_27 EQU 27 ;Unused. +IRQ_28 EQU 28 ;Unused. +IRQ_29 EQU 29 ;Unused. +IRQ_30 EQU 30 ;Unused. +IRQ_31 EQU 31 ;Unused. + +IRQ_SPI EQU IRQ_24 +IRQ_LSI EQU IRQ_25 +IRQ_IPI EQU IRQ_26 + +NUM_POWER_SUPPLIES_SUPPORTED EQU 2 ;Current # of power supplies + ;supported on a Manhattan. +PS_0_OK EQU BIT_6 ;Power supply 0 OK +PS_1_OK EQU BIT_7 ;Power Supply 1 OK +PS_0_INSTALLED EQU BIT_8 ;Power Supply 0 Installed +PS_1_INSTALLED EQU BIT_9 ;Power Supply 1 Installed. + +;BIT definitions for the EBI_SEM, a semaphore dword to control +;access to EBI II multi-threadable functions. + +SEM_EnableRAMCache EQU 1 ;bit 1 of EBI_SEM +SEM_DisableRAMCache EQU 2 +SEM_FlushRAMCache EQU 3 +SEM_LogProcIdle EQU 4 +SEM_LogProcBusy EQU 5 +SEM_GetPanellAttnSwitch EQU 6 +SEM_GetPanelOffSwitch EQU 7 +SEM_GetNMISource EQU 8 +SEM_NonMaskableIntEOI EQU 9 +SEM_GetSPISource EQU 10 +SEM_MaskableIntEOI EQU 11 +SEM_GetLocalIRQStatus EQU 12 +SEM_GetGLobalIRQStatus EQU 13 + + +;***************************************************************************** +; Declare Structure Templates +;***************************************************************************** +; +;Interrupt Mask Info. +; +EBI2maskInfo struc + numPorts dd 0 + flags dd 0 + portAddress0 dd 0 + portAddress1 dd 0 + portAddress2 dd 0 + portAddress3 dd 0 + reserved0 dd 0 + reserved1 dd 0 +EBI2maskInfo ends + + +EBI2_Mstruc struc + FP_GraphMode DD ? ;Front Panel Graph Mode + FP_IntMode DD ? ;Front Panel Interrupt Mode + IntSubSysMode DD ? ;Interrupt subsystem mode + SMEARRegister DD ? ;storage for SMEAR + IRQ0_Vector DD ? ;Vector number for IRQ0-7 + IRQ8_Vector DD ? ;and IRQ8-15 + EBI_SEM DD ? ;Semaphor for Multi-threadable + ;functions. + EBI_2TEMP DD ? ;temporary location for debug + CPU_Activity DB ? ;CPU Activity value. + SimPowerFail DB ? ;Set if we are simulate a PFI + +EBI2_Mstruc ends + + +parm_list struc + ebp_reg dd ? ;EBP register + ret_addr_off dd ? ;32 bit function return add. + MMIOPtr dd ? ;MMIOPtr + parm1dd dd ? ;1st 32 bit parameter + parm2dd dd ? ;2nd 32 bit parameter + parm3dd dd ? ;3RD 32 bit parameter + parm4dd dd ? ;4th 32 bit parameter + +parm_list ends + + +;real mode parameter list. + +RMparm_list struc + RMebp_reg dw ? ;EBP register + RMret_addr dd ? ;32 bit function return add. + RMparm1 dd ? ;1st 32 bit parameter + RMparm2 dd ? ;2nd 32 bit parameter + +RMparm_list ends + + + +procConfigData struc + processorStatus db ? + processorType db ? + coprocessorType db ? + serialNum DD ? + boardRev db ? + board_Type db ? + manufacturing_1 DB ? + manufacturing_2 DB ? + manufacturing_3 DB ? + manufacturing_4 DB ? + manufacturing_5 DB ? + manufacturing_6 DB ? + manufacturing_7 DB ? + manufacturing_8 DB ? + board_Info_1 DB ? + board_Info_2 DB ? + board_Info_3 DB ? + board_Info_4 DB ? + board_Info_5 DB ? + board_Info_6 DB ? + board_Info_7 DB ? + board_Info_8 DB ? + board_Info_9 DB ? + board_Info_10 DB ? + board_Info_11 DB ? + board_Info_12 DB ? + board_Info_13 DB ? + board_Info_14 DB ? + board_Info_15 DB ? + board_Info_16 DB ? + board_Info_17 DB ? + board_Info_18 DB ? + board_Info_19 DB ? + board_Info_20 DB ? + slotNumber DD ? + +procConfigData ends + +SIZE_OF_MEMDESCE EQU 4 ;number of DD entries in MemDescEntry +SIZE_OF_MMIO_TE EQU 4 ;number of DD in MMIO_Table_Entry + +MMIO_Table_Entry struc + + slot_add_low DD ? ;physical slot address, lower 32 bits + slot_add_high DD ? ;physical slot address, upper 32 bits + slot_length DD ? ;length of address space required + slot_reserved DD ? ;reserved + +MMIO_Table_Entry ends + +memBankInfo struc + + bankStartAddr_low DD ? + bankStartAddr_high DD ? + bankSize DD ? + bankECCSoftErrors DD ? + bankECCHardErrors DD ? + memBankInfoReserved DD ? + +memBankInfo ends + + +memBoardInfo struc + attributes DD ? + numBanks DD ? + slotNum DD ? + mBI_Reserved DD ? +memBoardInfo ends + +memoryErrorInfo struc + mEI_StartAddr_low DD ? + mEI_StartAddr_high DD ? + mEI_Length DD ? ;Length of block containing error. + mEI_Count DD ? ;Number of errors in this block + mEI_memErrFlags DD ? ;Additional info. + mEI_slotNumber DD ? ;Physical slot number of board + mEI_moduleNumber DD ? ;Module on board experiencing error. +memoryErrorInfo ends + + +cacheContInfo struc + cCI_Flags DD ? ;type of regional cache control + ;available by this hardware + cCI_Granularity DD ? ;Granularity of control region + cCI_Reserved DD ? ; ???NULL??? +cacheContInfo ends + +PhysicalAddress struc + PhsyAddrLow DD ? ;Lower 32 bits of a 64 Bit + ;physical address + PhsyAddrHi DD ? ;Upper 32 bits of a 64 bit + ;physical address. +PhysicalAddress ends + +OEM0ParmPacket Struc + OEM0_subfunc DD ? + OEM0_parm1dd DD ? + OEM0_parm2dd DD ? + OEM0_parm3dd DD ? + OEM0_parm4dd DD ? +OEM0ParmPacket ends + +revisionCode struc + major db ? ;revision number of + minor db ? ;EBI II in accordance with + ZZ db ? ;AST Revision number specification. +revisionCode ends + +powerSupplyInfo struc + present DD ? ;1 - Supply installed, + ;0 - not present + onLine DD ? ;1- Supply providing nominal + ;power, 0 - no power + PSI_Reserved DD ? ;AST reserved. +powerSupplyInfo ends + +;***************************************************************************** +; Declare Macros +;***************************************************************************** + + +;***************************************************************************** +; Macro: ProcTable_To_ESI +;***************************************************************************** +; We need to determine the offset to the begining of proc table. +; It is a requirement for DS and SS to be the same becuase we are +; running in a flat model addressing system. +; +; we need to determine the current address. +; we need to determine the difference between the current +; address and the begining of ProcTable. Keep in mind ProcTable +; is in a different segment. +; Then we subtract the difference from the current address and +; we have an offset that is pointing to the begining of ProcTable. +; +; Inputs : name of a near label +; +; Outputs : ESI will point to the begining of ProcTableLen +; +; +; Register Usage : ESI +; +;----------------------------------------------------------------------------- + +ProcTable_To_ESI MACRO + LOCAL current_add + call current_add + +current_add: + pop esi ;esi contains the address of the + ;current instruciton. + push eax + mov eax,offset current_add + sub eax,offset ProcTableLen ;eax contains the difference between + ;our address and begining of PorcTableLen + + sub esi,eax ;esi is pointing to start of ProcTableLen + pop eax + + ;sub esi,(offset addres- offset ProcTableLen) ;this does not work. + +ENDM + +;***************************************************************************** +; Macro: MemDesc_To_ESI +;***************************************************************************** +; We need to determine the offset to the begining of Memory Description table. +; It is a requirement for DS and SS to be the same becuase we are +; running in a flat model addressing system. +; +; we need to determine the current address. +; we need to determine the difference between the current +; address and the begining of MemDescTable. Keep in mind MemDescTable +; is in a different segment. +; Then we subtract the difference from the current address and +; we have an offset that is pointing to the begining of MemDescLen +; +; Inputs : name of a near label +; +; Outputs : ESI will point to the begining of MemDescLen +; +; +; Register Usage : ESI +; +;----------------------------------------------------------------------------- + +MemDesc_To_ESI MACRO + LOCAL MemDesc_add + + + call MemDesc_add + +MemDesc_add: + pop esi ;esi contains the address of the + ;current instruciton. + push eax + mov eax,offset MemDesc_add + sub eax,offset MemDescLen ;eax contains the difference between + ;our address and begining of MemDescLen + + sub esi,eax ;esi is pointing to start of MemDescLen + pop eax + + +ENDM + +;***************************************************************************** +; Macro: MemDesc_To_SI_16 +;***************************************************************************** +; +; Only in Real Mode or 16 bit protected mode. +; +; We need to determine the offset to the begining of Memory Description table. +; It is a requirement for DS and SS to be the same becuase we are +; running in a flat model addressing system. +; +; we need to determine the current address. +; we need to determine the difference between the current +; address and the begining of MemDescTable. Keep in mind MemDescTable +; is in a different segment. +; Then we subtract the difference from the current address and +; we have an offset that is pointing to the begining of MemDescLen +; +; Inputs : name of a near label +; +; Outputs : SI will point to the begining of MemDescLen +; +; +; Register Usage : SI +; +;----------------------------------------------------------------------------- + +MemDesc_To_SI_16 MACRO + LOCAL MemDesc_add_16 + + + call MemDesc_add_16 + +MemDesc_add_16: + pop si ;si contains the address of the + ;current instruciton. + push eax + mov eax,offset MemDesc_add_16 + sub eax,offset MemDescLen ;ax contains the difference between + ;our address and begining of MemDescLen + + sub si,ax ;si is pointing to start of MemDescLen + pop eax + + +ENDM + + +;***************************************************************************** +; Macro: MemTable_To_ESI +;***************************************************************************** +; We need to determine the offset to the begining of Memoryc table. +; It is a requirement for DS and SS to be the same becuase we are +; running in a flat model addressing system. +; +; we need to determine the current address. +; we need to determine the difference between the current +; address and the begining of MemTable. Keep in mind MemTable +; is in a different segment. +; Then we subtract the difference from the current address and +; we have an offset that is pointing to the begining of MemTable. +; +; Inputs : name of a near label +; +; Outputs : ESI will point to the begining of MemTableLen +; +; +; Register Usage : ESI +; +;----------------------------------------------------------------------------- + +MemTable_To_ESI MACRO + LOCAL MemTable_add + + call MemTable_add + +MemTable_add: + pop esi ;esi contains the address of the + ;current instruciton. + push eax + mov eax,offset MemTable_add + sub eax,offset MemTableLen ;eax contains the difference between + ;our address and begining of MemTableLen + + sub esi,eax ;esi is pointing to start of MemTableLen + pop eax + +ENDM + +MemTable_To_EDI MACRO + LOCAL MemTable_add_edi + + call MemTable_add_edi + +MemTable_add_edi: + pop edi ;edi contains the address of the + ;current instruciton. + push eax + mov eax,offset MemTable_add_edi + sub eax,offset MemTableLen ;eax contains the difference between + ;our address and begining of MemTableLen + + sub edi,eax ;edi is pointing to start of MemTableLen + pop eax + +ENDM + + +;***************************************************************************** +; Macro: MMIO_Table_To_ESI +;***************************************************************************** +; We need to determine the offset to the begining of MMIO_Table +; It is a requirement for DS and SS to be the same becuase we are +; running in a flat model addressing system. +; +; we need to determine the current address. +; we need to determine the difference between the current +; address and the begining of MMIO_Table. Keep in mind MMIO_Table +; is in a different segment. +; Then we subtract the difference from the current address and +; we have an offset that is pointing to the begining of MMIO_TableLen. +; +; Inputs : name of a near label +; +; Outputs : ESI will point to the begining of MMIO_TableLen +; +; +; Register Usage : ESI +; +;----------------------------------------------------------------------------- +MMIOTable_To_ESI MACRO + LOCAL MMIOTable_add + + + call MMIOTable_add + +MMIOTable_add: + pop esi ;esi contains the address of the + ;current instruciton. + push eax + mov eax,offset MMIOTable_add + sub eax,offset MMIO_TableLen ;eax contains the difference between + ;our address and begining of MMIO_TableLen + + sub esi,eax ;esi is pointing to start of MMIO_TableLen + pop eax + + +ENDM + +;***************************************************************************** +; Macro: OEM0_SubFuncStart_To_ESI +;***************************************************************************** +; +;----------------------------------------------------------------------------- +OEM0_SubFuncStart_To_ESI MACRO + LOCAL OEM0_SubFuncStart_add + + + call OEM0_SubFuncStart_add + +OEM0_SubFuncStart_add: + pop esi ;esi contains the address of the + ;current instruciton. + push eax + mov eax,offset OEM0_SubFuncStart_add + sub eax,offset OEM0_SubFuncLen + + ;eax contains the difference between + ;our address and begining of OEM0_SubFuncLen + + sub esi,eax ;esi is pointing to start of OEM0_SubFuncLen + pop eax + + +ENDM + +;***************************************************************************** +; Macro: BaseofROM_To_ESI +;***************************************************************************** +; +;----------------------------------------------------------------------------- +BaseofROM_To_ESI MACRO + LOCAL BaseofROM_add + + + call BaseofROM_add + +BaseofROM_add: + pop esi ;esi contains the address of the + ;current instruciton. + + sub esi,offset BaseofROM_add;esi contains the virtual address + ;to base of ROM. + + + +ENDM + +;***************************************************************************** +; Macro: ESI_MMIO_NUM_SLOT +;***************************************************************************** +; +; The following Macro will determine the virtual memory mapped I/O address +; for a certain slot number. +; The slot number is passed in EAX, and the virtual address is returned +; in ESI. +; +; Inputs : EBP.parm_list.MMIOPTR +; EAX slot number. +; +; Outputs : ESI will contain the virtual memory mapped I/O address for +; the specificed slot. +; +; Register Usage : ESI and EAX +; +; NOTE : For future enhancements or requirements, this macro should +; only use ESI and EAX and NO OTHER REGISTERS. +; +; +;----------------------------------------------------------------------------- + +ESI_MMIO_NUM_SLOT MACRO + + + ;Since MMIOPtr passed by the EBI II caller is a pointer to a + ;table containing the virtual address created by the OS for + ;the Manhattan memory mapped I/O address space. + ; + ;The first entry in the table is the virtual address for the + ;global (IOSM) MM I/O virtual address. + + ;setup ESI to point to the MM IO Table provide to us by the + ;EBI II caller. + mov esi, dword ptr [ebp.parm_list.MMIOPtr] + + ;eax is now the offset in to the MM IO Table to the virtual + ;address of memory mapped I/O for this slot. + + ;update ESI to containing the virtual address of the memory + ;mapped I/O for the callers slot. + mov esi,[esi][eax*4] + + +ENDM +;***************************************************************************** +; Macro: ESI_MMIO_CURR_SLOT +;***************************************************************************** +; +; The following Macro will determine the current CPU slot memory +; mapped I/O address. This value will be returned in ESI. +; +; +; Inputs : EBP.parm_list.MMIOPTR +; +; Outputs : ESI will point to the begining of the current slots +; MM I/O address +; +; +; Register Usage : ESI and EAX +; +; NOTE : For future enhancements or requirements, this macro should +; only use ESI and EAX and NO OTHER REGISTERS. +; +; +;----------------------------------------------------------------------------- + +ESI_MMIO_CURR_SLOT MACRO + + + ;Since MMIOPtr passed by the EBI II caller is a pointer to a + ;table containing the virtual address created by the OS for + ;the Manhattan memory mapped I/O address space. + ; + ;The first entry in the table is the virtual address for the + ;global (IOSM) MM I/O virtual address. + + ;setup ESI to point to the MM IO Table provide to us by the + ;EBI II caller. + + push eax ;save eax + + mov esi, dword ptr [ebp.parm_list.MMIOPtr] + + ;get the first entry from the table, which is the virtual address + ;for the global MM IO address space, also known as Slot 0 + mov eax, [esi] + + ;determine the caller SLOT number. + mov al, byte ptr [eax].G_SlotID + NOT al ;invert it back to 1 based. + and al,0FH ;clear upper nibble. + + ;clear the upper 24 bits of eax. + and eax,0ffH + + ;eax is now the offset in to the MM IO Table to the virtual + ;address of memory mapped I/O for this slot. + + ;update ESI to containing the virtual address of the memory + ;mapped I/O for the callers slot. + mov esi,[esi][eax*4] + pop eax + + +ENDM + + +;***************************************************************************** +; Macro: ESI_MMIO_GLOBAL +;***************************************************************************** +; +; The following Macro will determine the Global memory +; mapped I/O address. This value will be returned in ESI. +; +; +; Inputs : EBP.parm_list.MMIOPTR +; +; Outputs : ESI will point to the begining of the Global memory +; mapped I/O address +; +; +; Register Usage : ESI +; +; NOTE : For future enhancements or requirements, this macro should +; only use ESI and NO OTHER REGISTERS. +; +;----------------------------------------------------------------------------- + +ESI_MMIO_GLOBAL MACRO + + ;Since MMIOPtr passed by the EBI II caller is a pointer to a + ;table containing the virtual address created by the OS for + ;the Manhattan memory mapped I/O address space. + ; + ;The first entry in the table is the virtual address for the + ;global (IOSM) MM I/O virtual address. + + ;setup ESI to point to the MM IO Table provide to us by the + ;EBI II caller. + mov esi, dword ptr [ebp.parm_list.MMIOPtr] + + ;get the first entry from the table, which is the virtual address + ;for the global MM IO address space, also known as Slot 0 + + mov esi, [esi] + +ENDM + + +;***************************************************************************** +; Macro: ESI_EBI_MEM_ADD +;***************************************************************************** +; +; The following Macro will determine the virtual memory mapped I/O address +; for the memory reserved for EBI II. +; +; Inputs : EBP.parm_list.MMIOPTR +; +; Outputs : ESI will contain the virtual memory mapped I/O address for +; the memory reserved for EBI II. +; +; Register Usage : ESI +; +; NOTE : For future enhancements or requirements, this macro should +; only use ESI NO OTHER REGISTERS. +; +; +;----------------------------------------------------------------------------- + +ESI_EBI_MEM_ADD MACRO + + + ;Since MMIOPtr passed by the EBI II caller is a pointer to a + ;table containing the virtual address created by the OS for + ;the Manhattan memory mapped I/O address space. + ; + ;The first entry in the table is the virtual address for the + ;global (IOSM) MM I/O virtual address. + + ;setup ESI to point to the MM IO Table provide to us by the + ;EBI II caller. + + mov esi, dword ptr [ebp.parm_list.MMIOPtr] + + ;eax is now the offset in to the MM IO Table to the virtual + ;address of memory mapped I/O for this slot. + + ;update ESI to containing the virtual address of the memory + ;mapped I/O for the memory reserved for EBI II. + + mov esi,dword ptr [esi][EBI2_MEM_ENTRY*4] + + +ENDM +EDI_EBI_MEM_ADD MACRO + + + mov edi, dword ptr [ebp.parm_list.MMIOPtr] + + ;eax is now the offset in to the MM IO Table to the virtual + ;address of memory mapped I/O for this slot. + + ;update ESI to containing the virtual address of the memory + ;mapped I/O for the memory reserved for EBI II. + + mov edi,dword ptr [edi][EBI2_MEM_ENTRY*4] + + +ENDM + +;***************************************************************************** +; Macro: LOCK_SEMAPHORE +;***************************************************************************** +; +;----------------------------------------------------------------------------- +LOCK_SEMAPHORE MACRO SEM_NUM + LOCAL LS_CheckSem,LS_QuickCheck,LS_ProbableSucess + LOCAL LS_Sucess + + + push esi ;save esi + ESI_EBI_MEM_ADD ;point esi to EBI II memory space. + +LS_CheckSem: + lock bts dword ptr [esi].EBI2_Mstruc.EBI_SEM,SEM_NUM + + jnc LS_Sucess ;the semaphore was previously not set + + ;Some one has already locked this semaphore, do a quick check + ;hoping for it to free, if we time out then we return with the + ;carry set and an error code in eax. + push ecx + mov ecx, NEGONE + +LS_QuickCheck: + bt dword ptr [esi].EBI2_Mstruc.EBI_SEM,SEM_NUM + jnc LS_ProbableSucess ;it must have clear, make sure it is so + + loop LS_QuickCheck ;do another quick check, until ecx is 0 + + ;we must have timeout, in order to prevent a dead lock + ;return an error code. + pop ecx + mov eax, ERR_MULTI_TIME_OUT + stc ;set the carry indicating a problem with the macro + jmp LS_Sucess ;exit macro. + +LS_ProbableSucess: + ;the Semaphore seems to have cleared, but we need to make + ;sure by doing a lock bts + pop ecx + jmp LS_CheckSem + +LS_Sucess: + pop esi +ENDM + +;***************************************************************************** +; Macro: UNLOCK_SEMAPHORE +;***************************************************************************** +; +;----------------------------------------------------------------------------- +UNLOCK_SEMAPHORE MACRO UN_SEM_NUM + + + push esi ;save esi + ESI_EBI_MEM_ADD ;point esi to EBI II memory space. + + ;clear the semaphore in question. + LOCK btr dword ptr [esi].EBI2_Mstruc.EBI_SEM,UN_SEM_NUM + + pop esi +ENDM + + + +;***************************************************************************** +; Macro: IODELAY +;***************************************************************************** + +IODELAY MACRO + jmp Short $+2 + jmp Short $+2 + jmp Short $+2 + jmp Short $+2 +ENDM + diff --git a/private/ntos/nthals/halast/i386/astebiii.h b/private/ntos/nthals/halast/i386/astebiii.h new file mode 100644 index 000000000..251c200c8 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astebiii.h @@ -0,0 +1,745 @@ +/***************************************************************************\ +* File: ebi_ii.h - Standard definitions for EBI II interfacing. * +* * +* Data structures, defined values and function prototypes for accessing * +* AST EBI II compliant function libraries. * +* * +* By D. Shively II (dash) * +* * +* * +* ------------------------------------------------------------------------- * +* Edit history: * +* * +* Who Date Comment * +* ----- -------- ----------------------------------------------- * +* Dash 10/11/91 Inception * +* Dash 10/16/91 Version 2.1 * +* Dash 10/28/91 Version 2.2 * +* Dash 11/13/91 Version 2.3 * +* Dash 12/03/91 Version 2.4 * +* Dash 12/13/91 Version 2.4a * +* Dash 12/17/91 Version 2.4b * +* Dash 12/20/91 Version 2.4c * +* Dash 1/02/92 Version 2.5 * +* Dash 2/10/92 Version 2.5a (Note: was previously erroneously 2.6) * +* Dash & * +* rossw 3/03/92 Version 2.6 * +* Dash 4/14/92 Version 2.7 * +* Dash 4/26/92 Version 2.7.01 * +* Dash 4/30/92 Version 2.7.02 * +* Dash 6/02/92 Version 2.8 * +* Dash 9/21/92 Version 2.9 * +* * +\***************************************************************************/ + +#ifndef EBI_II_H +#define EBI_II_H + + +/* + * Portable data type definitions + */ +typedef unsigned char byte; // 8-bit quantity +typedef unsigned short word; // 16-bit quantity +typedef unsigned long dWord; // 32-bit quantity +typedef long status; // Completion status return data type + +/* + * The structure and the definitions for the new local int mask call + */ + +#define PORT_TYPE_MASK (3) +#define PORT_TYPE_MEMORY (0) +#define PORT_TYPE_IO (1) + +#define PORT_WIDTH_MASK (0x1C) +#define EIGHT_BIT_PORTS (0) +#define SIXTEEN_BIT_PORTS (4) +#define THIRTY_TWO_BIT_PORT (8) + +typedef struct { + dWord numPorts; + dWord flags; + dWord portAddress[4]; + dWord reserved[2]; +} maskInfo; + + +/* + * Macro to convert a segmented real mode address into a linear + * physical address. + */ +#define REAL_TO_LIN(seg,off) ((seg << 4) + off) + + +/* + * The EBI II signature is located in the BIOS segment at offset + * EBI_II_SIGNATURE. Thus, to derive it's linear address we + * use REAL_TO_LIN( BIOS_SEG, EBI_II_SIGNATURE ) + */ +#define BIOS_SEG (0xf000) +#define EBI_II_SIGNATURE (0xffe2) + + +/* + * Data structure defining EBI II signature/pointer area. + */ +typedef struct { + char sig[4]; // Signature string: literally "EBI2" + word seg; // Real mode segment + word off; // Real mode offset +} ebi_iiSig; + + +/* + * System board control register defines + */ +#define CFRAM_BIT 0x2 +#define CFRAM_OFFSET 0x20000 +#define CMMS_BIT 0x3 +#define CMMS_OFFSET 0x10008L +#define CMAS_BIT 0x1F +#define CMAS_OFFSET 0x10010L +#define MEMSLOT_BASEADDR 0xD0000000 +#define CPU_BOARD 0x10000L +#define CMCR_OFFSET 0x178L +#define BRSEL_BIT 0x40 +#define IBSR01_OFFSET 0x118L +#define ICR_OFFSET 0x128L + + +/* + * EBI II function completion codes. Non-error values are zero + * or greater. Erroneous results are less than zero. + */ +#define OK (0) +#define PROC_RUNNING (1) +#define PROC_STOPPED (2) +#define NO_CACHE (3) +#define NO_MEMORY_ERRORS (4) +#define MEMORY_ERROR_FOUND (5) +#define WRONG_PROC_GRAPH_MODE (6) +#define EMPTY_MEMORY_BANK (10000) + +#define BAD (-1) +#define ERR_NOT_SUPPORTED (-2) +#define ERR_NONESUCH (-3) +#define ERR_BAD_PROC_ID (-4) +#define ERR_PROC_ABSENT (-5) +#define ERR_PROC_BAD (-6) +#define ERR_UNKNOWN_INT (-7) +#define ERR_DISPLAY_OVERFLOW (-8) +#define ERR_BAD_CHARS (-9) +#define ERR_BAD_SELECTOR (-10) +#define ERR_BAD_CACHE_MODE (-11) +#define ERR_BAD_VECTOR (-12) +#define ERR_BAD_COLOR (-13) +#define ERR_BAD_GRAPH_MODE (-14) +#define ERR_BAD_BOARD_NUM (-15) +#define ERR_BAD_MODULE_NUM (-16) +#define ERR_BAD_IRQ_NUM (-17) +#define ERR_BAD_OFFSWITCH (-18) +#define ERR_BAD_PHYS_ADDR (-19) +#define ERR_BAD_LENGTH (-20) +#define ERR_BAD_BLOCK_NUM (-21) +#define ERR_BAD_GLOB_MASK_IRQ (-22) +#define ERR_BAD_LOC_MASK_IRQ (-23) +#define ERR_CANT_CANCEL_INT (-24) +#define ERR_PROC_STILL_RUNNING (-25) +#define ERR_POWER_SUPPLY_NUM (-26) +#define ERR_BAD_VIS_MODE (-27) + +#define IsOK(n) ( n >= OK ) +#define IsBad(n) ( n < OK ) + + +/* + * Independent hardware manufacturers and OEMs are allowed to define + * function extensions to the calling system in the OEM function array + * at the end of the ebi_ii structure. To avoid collisions in OEM + * specified completion/error codes, use the following system: + * To define a non-error completion code, define it as: + * #define name OEMCompCode(OEMNum,sequenceNum) + * + * Define an error code as: + * #define name OEMErrorCode( OEMNum,sequenceNum) + * + * Where: + * + * OEMNum The OEM number assigned you by AST (if you don't + * have one, contact them. Really, go ahead.) For + * example, AST themselves are OEM #0. + * + * sequenceNum The conditions sequential number. I.e.- the + * 1st condition defined is 0, then next 1, etc. + * + * Example: + * AST uses the following definition in it's OEM include file, astoem.h: + * + * #define ERR_BAD_COM2_OVERRIDE OEMErrorCode(0,-1) + * + * (See astoem.h for additional examples.) + */ + +/* + * Macros for OEM completion code definition. + */ +#define EBI2_OEM_COMP_CODE_BASE (65536L) +#define EBI2_OEM_ERR_CODE_BASE (-65536L) +#define EBI2_OEM_COMP_CODE_GAP (65536L) + +#define OEMCompCode(OEMNum,sequenceNum) \ + ( EBI2_OEM_COMP_CODE_BASE + (OEMNum * EBI2_OEM_COMP_CODE_GAP) \ + + sequenceNum ) + +#define OEMErrorCode(OEMNum,sequenceNum) \ + ( EBI2_OEM_ERR_CODE_BASE - (OEMNum * EBI2_OEM_COMP_CODE_GAP) \ + - sequenceNum ) + + +/* + * Processor configuration data table + */ +typedef struct procConfigData { + byte processorStatus; // See Table 3 + byte processorType; // See Table 4 + byte coprocessorType; // See Table 6 + byte serialNum[4]; // Packed BCD board serial number + byte boardRev; // 2 byte Hex board revision + byte boardType; // See table 5 + byte manufacturing[8]; // Unused bytes, NULL filled + byte boardInfo[20]; // Board specific info, format + // to be defined + dWord slotNumber; // Physical slot this board occupies +} procConfigData; + + +/* + * ProcessorType codes + */ +#define PTYPE_80386 (0x10) // Intel family of processors +#define PTYPE_80486 (0x11) +#define PTYPE_80586 (0x12) +#define PTYPE_80686 (0x13) +#define PTYPE_80786 (0x14) + +#define PTYPE_SPARC (0x20) // Sun SPARC type processor + +#define PTYPE_MIPS4000 (0x30) // Mips +#define PTYPE_MIPS5000 (0x31) + +#define PTYPE_68030 (0x40) // Motorola 68000 family +#define PTYPE_68040 (0x41) +#define PTYPE_68050 (0x42) + +#define PTYPE_88000 (0x50) // Motorola 88000 RISC family +#define PTYPE_88110 (0x51) + +#define PTYPE_34010 (0x60) // TI 34000 graphics processor family +#define PTYPE_34020 (0x61) +#define PTYPE_34030 (0x62) + +#define PTYPE_R6000 (0x70) // IBM + +#define PTYPE_80860 (0x80) // Intel i860 RISC processor family +#define PTYPE_80960 (0x81) + + +/* + * ProcessorStatus codes + */ +#define PSTAT_ABSENT (0) +#define PSTAT_RUNNING (1) +#define PSTAT_RESET (2) +#define PSTAT_FAULT (0x0f) + + +/* + * coprocessorType codes + */ +#define CPTYPE_387 (0x10) // Intel type coprocessor family +#define CPTYPE_487 (0x11) +#define CPTYPE_587 (0x12) + +#define CPTYPE_3167 (0x20) // Weitek coprocessors for 80x86 processors +#define CPTYPE_4167 (0x21) +#define CPTYPE_5167 (0x22) + +#define CPTYPE_68881 (0x30) // Motorola mathco's +#define CPTYPE_68882 (0x31) + +#define CPTYPE_34081 (0x40) // Floating point coprocessors for TI 34000 +#define CPTYPE_34082 (0x41) // family + + +/* + * ProcessorGraph mode values + */ +#define HISTO_MODE 0 // Histogram mode +#define STATUS_MODE 1 +#define OVERRIDE_MODE 2 + + +/* + * Define data type for a 64-bit linear physical address. + */ +typedef struct { + dWord low; + dWord high; +} physAddr; + +/* + * Define cache mode values + */ +#define ENABLE_CACHE (0) +#define DISABLE_CACHE (4) +#define AUTO_WRITE_THRU (0) +#define FORCE_WRITE_THRU (2) +#define AUTO_READ_ONLY (0) +#define FORCE_READ_ONLY (1) +#define DEFAULT_CACHE_MODE (0) + + +/* + * cache region control word values + */ +#define ENABLE_REGION_CACHING (1) +#define DISABLE_REGION_CACHING (0) + + +/* + * The Cache control information structure; returned GetCacheControlInfo(). + */ +typedef struct cacheControlInfo { + dWord flags; // See table 9. + dWord controlGranularity; // In bytes. + dWord RESERVED; +} cacheControlInfo; + + +typedef struct { + dWord r_eax; + dWord r_ebx; + dWord r_ecx; + dWord r_edx; + dWord r_edi; + dWord r_esi; + dWord r_ebp; +} poss_regs; + + +/* + * memoryBlockInfo definition + */ +typedef struct memoryBlockInfo { + physAddr blockStartAddr; // Start address of this memory block + dWord blockSize; // Size of this block + dWord blockAttributes; // Attributes of this block +} memoryBlockInfo; + + +/* + * Module attribute bit definitions and macros. Also used on + * GetMemBankInfoPacket (See astoem.h). + */ +#define RAM_WIDTH_MASK (0x0f) +#define extractRAMWidth(n) ((n) & RAM_WIDTH_MASK ) +#define RAM_PRESENT (0x10) +#define ECC_PRESENT (0x100) +#define INTERLEAVED (0x200) +#define BIT_MODE_MASK (0xfc00) +#define BIT_MODE_64 (0) +#define BIT_MODE_128 (0x400) +#define extractBitMode(n) ((n) & BIT_MODE_MASK) + + +/* + * memoryErrorInfo definition + */ +typedef struct memoryErrorInfo { + physAddr location; // Location of block containing error + dWord length; // Length of block containing errors in bytes + dWord count; // Number of errors in this block + dWord memErrFlags; // Additional info; see definitions below and Table 20 + dWord slotNumber; // Physical slot number of board experiencing error + dWord moduleNumber; // Module on board experiencing error +} memoryErrorInfo; + + +/* + * memErrFlags bits definitions + */ +#define MEM_ERR_TYPE_MASK 0x0f +#define GETMEMERRTYPE(n) ((n) & MEM_ERR_TYPE_MASK) + +#define MEM_NO_ERROR (0) +#define MEM_ERR_PARITY (1) +#define MEM_ERR_SINGLEBIT_ECC (2) +#define MEM_ERR_MULTIBIT_ECC (3) + +#define SLOT_NUM_INDETERMINATE (-1) +#define MOD_NUM_INDETERMINATE (-1) + + +/* + * Front panel UPS light color codes + */ +#define UPS_COLOR_DARK (0) +#define UPS_COLOR_GREEN (2) +#define UPS_COLOR_AMBER (3) +#define UPS_COLOR_RED (1) + + +/* + * Font panel key position codes + */ +#define KEY_POS_LOCKED 0 +#define KEY_POS_SERVICE 1 +#define KEY_POS_UNLOCKED 2 +#define KEY_POS_OFF 3 + + +/* + * The EBI II revision code structure + */ +typedef struct revisionCode { + byte major; // EBI II revision major number (the XX in XX.YY) + byte minor; // EBI II revision minor number (the YY in XX.YY) + byte RESERVED; +} revisionCode; + + +/* + * Define data type describing the in ROM offset table. + */ +typedef dWord offsetTable[128]; // Unresolved BIOS offset table + + +/* + * IOInfoTable structure. The address of such a table must be + * provided during virtually any EBI II call. + */ +typedef struct { + physAddr address; // Physical address of this slot's I/O area + dWord length; // Length of area, or 0 if no I/O area + dWord flags; // Allocation type flags} IOInfoTable; +} IOInfoTable; + +#define ALLOCATE_RAM (1) // Only one bit used so far + + +/* + * NMI and SPI Source constants + */ +#define NMI_NONE_FOUND (0) +// RESERVED (1) +#define NMI_SW_GEN_NMI (2) +#define NMI_MEMORY_ERROR (3) +#define NMI_PROC_ERROR (4) +// RESERVED (5) +#define NMI_BUS_PARITY (6) +#define NMI_BUS_TIMEOUT (7) +#define NMI_FP_SHUTDOWN (8) +#define NMI_FP_ATTENTION (9) +#define NMI_POWERFAIL (10) +#define NMI_EISA_FAILSAFE_TIMER (11) +#define NMI_EISA_BUS_TIMEOUT (12) +#define NMI_EISA_IO_CHECK (13) +#define NMI_EISA_SW_GEN_NMI (14) +#define NMI_SYS_IO_ERROR (15) + +#define OEM_NMI_BASE (0x10000000L) +#define OEM_NMI_GAP (0x01000000L) +#define OEM_NMI_NUM(OEM,NMI_NUM) ( \ + OEM_NMI_BASE + \ + (OEM_NMI_GAP * OEM) + \ + NMI_NUM \ + ) + + +#define SPI_NONE_FOUND (0) +// RESERVED (1) +// RESERVED (2) +#define SPI_MEMORY_ERROR (3) +#define SPI_PROC_ERROR (4) +// RESERVED (5) +#define SPI_BUS_PARITY (6) +#define SPI_BUS_TIMEOUT (7) +#define SPI_FP_SHUTDOWN (8) +#define SPI_FP_ATTENTION (9) +#define SPI_POWERFAIL (10) +#define SPI_EISA_FAILSAFE_TIMER (11) +#define SPI_EISA_BUS_TIMEOUT (12) +#define SPI_EISA_IO_CHECK (13) +#define SPI_EISA_SW_GEN_NMI (14) +#define SPI_SYS_IO_ERROR (15) + +#define OEM_SPI_BASE (0x10000000L) +#define OEM_SPI_GAP (0x01000000L) +#define OEM_SPI_NUM(OEM,SPI_NUM) ( \ + OEM_SPI_BASE + \ + (OEM_SPI_GAP * OEM) + \ + SPI_NUM \ + ) + + +/* + * Front panel OFF switch mode constants + */ +#define OFF_SWITCH_NMI (0) +#define OFF_SWITCH_HW_SHUTDOWN (1) + + +/* + * Interrupt subsystem typecodes + */ +#define EBI_INT_SUBSYS_EISA (0) +#define EBI_INT_SUBSYS_ISA (1) +#define EBI_INT_SUBSYS_ADI (2) +#define EBI_INT_SUBSYS_MPIC (3) + + +/* + * IRQ numbers. + */ +#define EBI_IRQ0 (0L) // PIC #1 (Master) +#define EBI_IRQ1 (1L) // PIC #1 (Master) +#define EBI_IRQ2 (2L) // Inaccessable in cascaded PIC system +#define EBI_IRQ3 (3L) // PIC #1 (Master) +#define EBI_IRQ4 (4L) // PIC #1 (Master) +#define EBI_IRQ5 (5L) // PIC #1 (Master) +#define EBI_IRQ6 (6L) // PIC #1 (Master) +#define EBI_IRQ7 (7L) // PIC #1 (Master) +#define EBI_IRQ8 (8L) // PIC #2 (1st slave) +#define EBI_IRQ9 (9L) // PIC #2 (1st slave) +#define EBI_IRQ10 (10L) // PIC #2 (1st slave) +#define EBI_IRQ11 (11L) // PIC #2 (1st slave) +#define EBI_IRQ12 (12L) // PIC #2 (1st slave) +#define EBI_IRQ13 (13L) // PIC #2 (1st slave) +#define EBI_IRQ14 (14L) // PIC #2 (1st slave) +#define EBI_IRQ15 (15L) // PIC #2 (1st slave) +#define EBI_IRQ16 (16L) // PIC #3 (2nd slave) +#define EBI_IRQ17 (17L) // PIC #3 (2nd slave) +#define EBI_IRQ18 (18L) // PIC #3 (2nd slave) +#define EBI_IRQ19 (19L) // PIC #3 (2nd slave) +#define EBI_IRQ20 (20L) // PIC #3 (2nd slave) +#define EBI_IRQ21 (21L) // PIC #3 (2nd slave) +#define EBI_IRQ22 (22L) // PIC #3 (2nd slave) +#define EBI_IRQ23 (23L) // PIC #3 (2nd slave) +#define EBI_IRQ24 (24L) // SPI (See below) +#define EBI_IRQ25 (25L) // LSI (See below) +#define EBI_IRQ26 (26L) // IPI (See below) +#define EBI_IRQ27 (27L) // Reserved +#define EBI_IRQ28 (28L) // Reserved +#define EBI_IRQ29 (29L) // Reserved +#define EBI_IRQ30 (30L) // Reserved +#define EBI_IRQ31 (31L) // Reserved + +#define EBI_SPI_IRQ (EBI_IRQ24) +#define EBI_LSI_IRQ (EBI_IRQ25) +#define EBI_IPI_IRQ (EBI_IRQ26) + +#define EBI_IRQBIT0 (0x1L) // PIC #1 (Master) +#define EBI_IRQBIT1 (0x2L) // PIC #1 (Master) +#define EBI_IRQBIT2 (0x4L) // Inaccessable in cascaded PIC system +#define EBI_IRQBIT3 (0x8L) // PIC #1 (Master) +#define EBI_IRQBIT4 (0x10L) // PIC #1 (Master) +#define EBI_IRQBIT5 (0x20L) // PIC #1 (Master) +#define EBI_IRQBIT6 (0x40L) // PIC #1 (Master) +#define EBI_IRQBIT7 (0x80L) // PIC #1 (Master) +#define EBI_IRQBIT8 (0x100L) // PIC #2 (1st slave) +#define EBI_IRQBIT9 (0x200L) // PIC #2 (1st slave) +#define EBI_IRQBIT10 (0x400L) // PIC #2 (1st slave) +#define EBI_IRQBIT11 (0x800L) // PIC #2 (1st slave) +#define EBI_IRQBIT12 (0x1000L) // PIC #2 (1st slave) +#define EBI_IRQBIT13 (0x2000L) // PIC #2 (1st slave) +#define EBI_IRQBIT14 (0x4000L) // PIC #2 (1st slave) +#define EBI_IRQBIT15 (0x8000L) // PIC #2 (1st slave) +#define EBI_IRQBIT16 (0x10000L) // PIC #3 (2nd slave) +#define EBI_IRQBIT17 (0x20000L) // PIC #3 (2nd slave) +#define EBI_IRQBIT18 (0x40000L) // PIC #3 (2nd slave) +#define EBI_IRQBIT19 (0x80000L) // PIC #3 (2nd slave) +#define EBI_IRQBIT20 (0x100000L) // PIC #3 (2nd slave) +#define EBI_IRQBIT21 (0x200000L) // PIC #3 (2nd slave) +#define EBI_IRQBIT22 (0x400000L) // PIC #3 (2nd slave) +#define EBI_IRQBIT23 (0x800000L) // PIC #3 (2nd slave) +#define EBI_IRQBIT24 (0x1000000L) // SPI (See below) +#define EBI_IRQBIT25 (0x2000000L) // LSI (See below) +#define EBI_IRQBIT26 (0x4000000L) // IPI (See below) +#define EBI_IRQBIT27 (0x8000000L) // Reserved +#define EBI_IRQBIT28 (0x10000000L) // Reserved +#define EBI_IRQBIT29 (0x20000000L) // Reserved +#define EBI_IRQBIT30 (0x40000000L) // Reserved +#define EBI_IRQBIT31 (0x80000000L) // Reserved + +#define EBI_SPI_IRQBIT (EBI_IRQBIT24) +#define EBI_LSI_IRQBIT (EBI_IRQBIT25) +#define EBI_IPI_IRQBIT (EBI_IRQBIT26) + + +/* + * Constants used in powerSupplyInfo.present and onLine (See Below) + */ +#define POWER_SUPPLY_PRESENT (1) +#define POWER_SUPPLY_ABSENT (0) +#define POWER_SUPPLY_ONLINE (1) +#define POWER_SUPPLY_OFFLINE (0) + + +/* + * Power supply information structure. + */ +typedef struct { + dWord present; // 1 - Supply installed, 0 - absent + dWord onLine; // 1 - Supply providing nominal power, 0 - no power provided + dWord RESERVED[8]; // Unused at this time, reserved by AST +} powerSupplyInfo; + + +/* + * Front panel switch visibility values + */ +#define PANEL_SWITCHES_INVISIBLE (0) +#define PANEL_SWITCHES_VISIBLE (1) + + +/* + * 32-bit protected mode EBI II call structure. This structure is built + * based on the ROM offset table. + * Calls are made thusly: + * + * EBI_II callTab; + * void *MMIOTable; + * dWord numProcs; + * + * retStat = (callTab.GetNumProcs)( MMIOTable, &numProcsPtr ); + */ +typedef struct EBI_II { + status (__cdecl *GetNumProcs)( void *MMIOTable, dWord *numProcs ); // 1 + status (__cdecl *GetProcConf)( void *MMIOTable, + dWord processorID, + procConfigData *configData ); // 2 + status (__cdecl *StartProc)( void *MMIOTable, dWord processorID ); // 3 + status (__cdecl *StopProc)( void *MMIOTable, dWord processorID ); // 4 + status (__cdecl *GetProcID)( void *MMIOTable, dWord *processorID ); // 5 + status (__cdecl *EnableRAMCache)( void *MMIOTable ); // 6 + status (__cdecl *DisableRAMCache)( void *MMIOTable ); // 7 + status (__cdecl *FlushRAMCache)( void *MMIOTable, dWord flushType ); // 8 + status (__cdecl *ControlCacheRegion)( void *MMIOTable, + dWord control, + physAddr start, + dWord length ); // 9 + status (__cdecl *GetCacheControlInfo)( void *MMIOTable, + cacheControlInfo *info ); // 10 + status (__cdecl *SetPanelUPS)( void *MMIOTable, dWord LEDColor ); // 11 + status (__cdecl *GetPanelUPS)( void *MMIOTable, dWord *LEDColor ); // 12 + status (__cdecl *SetPanelProcGraphMode)( void *MMIOTable, + dWord displayMode ); // 13 + status (__cdecl *GetPanelProcGraphMode)( void *MMIOTable, + dWord *displayMode ); // 14 + status (__cdecl *SetPanelProcGraphValue)( void *MMIOTable, dWord value ); // 15 + status (__cdecl *GetPanelProcGraphValue)( void *MMIOTable, dWord *value ); // 16 + status (__cdecl *LogProcIdle)( void *MMIOTable ); // 17 + status (__cdecl *LogProcBusy)( void *MMIOTable ); // 18 + status (__cdecl *GetPanelAttnSwitchLatch)( void *MMIOTable, dWord *latch ); // 19 + status (__cdecl *GetPanelOffSwitchLatch)( void *MMIOTable, dWord *latch ); // 20 + status (__cdecl *GetPanelKeyPos)( void *MMIOTable, dWord *keyPos ); // 21 + status (__cdecl *GetPanelAlphaNumInfo)( void *MMIOTable, + dWord *displayType, + dWord *width ); // 22 + status (__cdecl *GetPanelAlphaNum)( void *MMIOTable, byte *contents ); // 23 + status (__cdecl *SetPanelAlphaNum)( void *MMIOTable, byte *string ); // 24 + status (__cdecl *SetPanelOffSwitchMode)( void *MMIOTable, dWord mode ); // 25 + status (__cdecl *GetPanelOffSwitchMode)( void *MMIOTable, dWord *mode ); // 26 + status (__cdecl *GetIntSubsysType)( void *MMIOTable, dWord *subsystemType ); // 27 + status (__cdecl *SetGlobalIntMask)( void *MMIOTable, dWord mask ); // 28 + status (__cdecl *GetGlobalIntMask)( void *MMIOTable, dWord *mask ); // 29 + status (__cdecl *SetLocalIntMask)( void *MMIOTable, + dWord mask, + dWord processorID ); // 30 + status (__cdecl *GetLocalIntMask)( void *MMIOTable, + dWord *mask, + dWord processorID ); // 31 + status (__cdecl *SetAdvIntMode)( void *MMIOTable ); // 32 + status (__cdecl *SetIRQVectorAssign)( void *MMIOTable, + dWord IRQNum, + dWord vectorNum ); // 33 + status (__cdecl *GetIRQVectorAssign)( void *MMIOTable, + dWord IRQNum, + dWord *vectorNum ); // 34 + status (__cdecl *GetNumPowerSupplies)( void *MMIOTable, + dWord *numSupplies ); // 35 + status (__cdecl *GetPowerSupplyInfo)( void *MMIOTable, + dWord supplyNum, + powerSupplyInfo *info ); // 36 + status (__cdecl *DeInitEBI)( void *MMIOTable ); // 37 + status (__cdecl *SetLSIVector)( void *MMIOTable, + dWord processorID, + dWord vector ); // 38 + status (__cdecl *GetLSIVector)( void *MMIOTable, + dWord processorID, + dWord *vector ); // 39 + status (__cdecl *SetSPIVector)( void *MMIOTable, + dWord processorID, + dWord vector ); // 40 + status (__cdecl *GetSPIVector)( void *MMIOTable, + dWord processorID, + dWord *vector ); // 41 + status (__cdecl *SetIPIVector)( void *MMIOTable, + dWord processorID, + dWord vector ); // 42 + status (__cdecl *GetIPIVector)( void *MMIOTable, + dWord processorID, + dWord *vector ); // 43 + status (__cdecl *SetIPIID)( void *MMIOTable, dWord processorID, dWord ID ); // 44 + status (__cdecl *GetIPIID)( void *MMIOTable, dWord processorID, dWord *ID ); // 45 + status (__cdecl *GenIPI)( void *MMIOTable, dWord ID ); // 46 + status (__cdecl *GenLSI)( void *MMIOTable ); // 47 + status (__cdecl *GetNMISource)( void *MMIOTable, dWord *NMISource ); // 48 + status (__cdecl *GetSPISource)( void *MMIOTable, dWord *SPISource ); // 49 + status (__cdecl *GetLocalIRQStatus)( void *MMIOTable, + dWord processorID, + dWord *inService, + dWord *requested ); // 50 + status (__cdecl *MaskableIntEOI)( void *MMIOTable, dWord intNum ); // 51 + status (__cdecl *NonMaskableIntEOI)( void *MMIOTable ); // 52 + status (__cdecl *CancelInterrupt)( void *MMIOTable, + dWord mask, + dWord processorID ); // 53 + status (__cdecl *GetSysTimer)( void *MMIOTable, dWord *timerValue ); // 54 + status (__cdecl *GetSysTimerFreq)( void *MMIOTable, dWord *frequency ); // 55 + status (__cdecl *GetNumMemBlocks)( void *MMIOTable, dWord *numBlocks ); // 56 + dWord GetNumMemBlocks16; // Not accessable in protected mode // 57 + status (__cdecl *GetMemBlockInfo)( void *MMIOTable, + memoryBlockInfo *blockInfo, + dWord blockNum ); // 58 + dWord GetMemBlockInfo16; // Not accessable in protected mode // 59 + status (__cdecl *GetMemErrorInfo)( void *MMIOTable, memoryErrorInfo *info ); // 60 + status (__cdecl *GetRevision)( void *MMIOTable, revisionCode *rev ); // 61 + status (__cdecl *GetNumSlots)( dWord *numSlots ); // 62 + status (__cdecl *GetMMIOTable)( IOInfoTable *infoTable ); // 63 + status (__cdecl *InitEBI)( void *MMIOTable ); // 64 + status (__cdecl *GetThermalState)( void *MMIOTable, dWord *temperature ); // 65 + status (__cdecl *ShutdownPowerSupply)( void *MMIOTable ); // 66 + status (__cdecl *SimulatePowerFail)( void *MMIOTable, + dWord processorID ); // 67 + status (__cdecl *SetPanelSwitchVisibility)( void *MMIOTable, dWord mode ); // 68 + status (__cdecl *GetPanelSwitchVisibility)( void *MMIOTable, dWord *mode ); // 69 + status (__cdecl *GetGlobalIRQStatus)( void *MMIOTable, + dWord *inService, + dWord *requested ); // 70 + status (__cdecl *FastSetLocalIntMask)( dWord handle, dWord mask ); // 71 + status (__cdecl *GetProcIntHandle)( void *MMIOTable, + dWord processorID, + dWord *handle ); // 72 + status (__cdecl *RegSetLocalIntMask)(); //73 + status (__cdecl *GetLocalIntMaskInfo)( void *MMIOTable, //74 + maskInfo *info, + dWord proccessorID ); + status (__cdecl *ASTx[22])( void *MMIOTable, ... ); // 75..96 + status (__cdecl *OEM[32])( void *MMIOTable, ... ); // 97..128 +} EBI_II; + +#endif + +/* ----------------------- End of ebi_ii.h ----------------------- */ diff --git a/private/ntos/nthals/halast/i386/astebini.c b/private/ntos/nthals/halast/i386/astebini.c new file mode 100644 index 000000000..5984377d3 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astebini.c @@ -0,0 +1,189 @@ +/*++ + +Copyright (c) 1992 AST Research Inc. + +Module Name: + + astebini.c + +Abstract: + + Initialization code for AST Manhattan system. + +Author: + + Bob Beard (v-bobb) 24-Jul-1992 + +Environment: + + Kernel mode only. + +Revision History: + +--*/ + +#ifndef _NTOS_ +#include "nthal.h" +#endif + +#include "halp.h" +#include "astebiii.h" +#include "astdisp.h" + +VOID DisplPanel(ULONG x); + +extern PVOID BiosPtr; + +// *** temporary way to do MMIOTable & EbiMemory +#define MAX_EBI_SLOTS 32L +VOID* EBI2_MMIOTable[MAX_EBI_SLOTS]; +#define MAX_EBI_MEMORY 1024L +static UCHAR EbiMemory[MAX_EBI_MEMORY]; + +// +// EBI Revision +// + +revisionCode EBI2_revision; + +// +// Number of good processors in the system +// + +ULONG EBI2_ProcCnt; +ULONG MpCount; // zero based version for HalStartNextProcessor + +// +// EBI_II function offset table +// + +extern EBI_II EBI2_CallTab; + + +BOOLEAN +ASTInitEBI2() +/*++ + +Routine Description: + Initialize the AST EBI II environment. Only called if an AST machine + with EBI II capability. Gets table of EBI II call addresses in ebi_call_table. + Sets up EBI2_MMIOTable (EBI II Memory Mapped I/O Table). + +Arguments: + none. + +Return Value: + True if EBI II successfully initialized. False otherwise. + +--*/ +{ + +ULONG i; +//ULONG *Alias = (ULONG *)&EBI2_CallTab; +//ebi_iiSig *Sig = (ebi_iiSig*)((ULONG)BiosPtr + EBI_II_SIGNATURE); +//ULONG *OffTab; +IOInfoTable IOInfo[MAX_EBI_SLOTS]; +dWord NumSlots; +ULONG Pages; +procConfigData ConfigData; +ULONG ProcCount; + +//*** v-quangp: This table is already build at astdetct.c ** +// +// Build the EBI II offset table +// +// +// OffTab =(ULONG *) ((ULONG)BiosPtr + (REAL_TO_LIN(Sig->seg,Sig->off) - +// REAL_TO_LIN(BIOS_SEG, 0))); +// for( i = 0; i < ( sizeof( offsetTable ) / sizeof( ULONG )); i++ ) +// Alias[i] = OffTab[i] + (ULONG)BiosPtr; +// +// +// Get the number of "slots" (logical address spaces) +// + +EBI2_CallTab.GetNumSlots( &NumSlots ); +if (NumSlots > MAX_EBI_SLOTS) + { DisplPanel(HALSlotProblem); return(FALSE); } + +// +// Get the Memory Mapped I/O Information +// + +if ( (EBI2_CallTab.GetMMIOTable( IOInfo ))) + { DisplPanel(HALMMIOProblem); return(FALSE); } + +for( i = 0; i < NumSlots; i++ ) + if( IOInfo[i].length ) { + +// +// Allocate some memory for EBI II +// + + if ( IOInfo[i].flags & ALLOCATE_RAM ) + { if (IOInfo[i].length > MAX_EBI_MEMORY) + { DisplPanel(HALMemoryProblem); return(FALSE); } + EBI2_MMIOTable[i] = EbiMemory; + } + +// +// Allocate a virtual address spanning the memory mapped I/O range +// for a given slot. +// + + else { + Pages = IOInfo[i].length / PAGE_SIZE; + if ( IOInfo[i].length % PAGE_SIZE ) + Pages++; + EBI2_MMIOTable[i] = HalpMapPhysicalMemory( (PVOID)IOInfo[i].address.low, Pages ); + if ( EBI2_MMIOTable[i] == NULL ) + { DisplPanel(HALPhysicalAllocProblem); return(FALSE); } + } + } + +// +// Initialize EBI II +// + + if ( (EBI2_CallTab.InitEBI)( EBI2_MMIOTable ) ) + { DisplPanel(HALEBIInitProblem); return(FALSE); } + +// +// Put NT on the front panel display +// + + EBI2_CallTab.SetPanelAlphaNum( EBI2_MMIOTable, " NT "); + +// +// Find out the number of good processors +// + + if ( (EBI2_CallTab.GetNumProcs)( EBI2_MMIOTable, &ProcCount ) ) + { DisplPanel(HALEBIGetProcProblem); return(FALSE); } + + EBI2_ProcCnt = ProcCount; + for (i=0; i<ProcCount; i++) + if ( (EBI2_CallTab.GetProcConf)( EBI2_MMIOTable, i, &ConfigData ) ) + EBI2_ProcCnt--; + + if (EBI2_ProcCnt == 0) + { DisplPanel(HALEBINoProcsProblem); return(FALSE); } + + MpCount = EBI2_ProcCnt - 1; + +// +// Turn on the front panel cpu activity bar graph in histogram mode +// + + EBI2_CallTab.SetPanelProcGraphMode( EBI2_MMIOTable, 0 ); + +// +// Get EBI2 Revision +// + +if ( (EBI2_CallTab.GetRevision( EBI2_MMIOTable, &EBI2_revision ))) + { DisplPanel(HALGetRevisionProblem); return(FALSE); } + + + return(TRUE); +} diff --git a/private/ntos/nthals/halast/i386/asthal.c b/private/ntos/nthals/halast/i386/asthal.c new file mode 100644 index 000000000..d3be648dc --- /dev/null +++ b/private/ntos/nthals/halast/i386/asthal.c @@ -0,0 +1,364 @@ +/*++ + +Copyright (c) 1991 Microsoft Corporation +Copyright (c) 1992 AST Research Inc. + +Module Name: + + asthal.c + +Abstract: + + + This module implements the initialization of the system dependent + functions that define the Hardware Architecture Layer (HAL) for an + AST EBI2 (Manhattan) system. + +Author: + + David N. Cutler (davec) 25-Apr-1991 + +Environment: + + Kernel mode only. + +Revision History: + + Bob Beard (v-bobb) 31-Jul-1992 convert for AST EBI2 system +--*/ + +#include "halp.h" +#include "astdisp.h" + +ULONG HalpBusType; + +ADDRESS_USAGE HalpDefaultASTIoSpace = { + NULL, CmResourceTypePort, InternalUsage, + { + // Standard PC ISA I/O space used... + 0x000, 0x10, // ISA DMA + 0x0C0, 0x10, // ISA DMA + 0x080, 0x10, // DMA + + 0x020, 0x2, // PIC + 0x0A0, 0x2, // Cascaded PIC + + 0x040, 0x4, // Timer1, Referesh, Speaker, Control Word + 0x048, 0x4, // Timer2, Failsafe + + 0x061, 0x1, // NMI (system control port B) + 0x092, 0x1, // system control port A + + 0x070, 0x2, // Cmos/NMI enable + 0x0F0, 0x10, // coprocessor ports + + // Standard PC EISA I/O space used... + 0x0D0, 0x10, // DMA + 0x400, 0x10, // DMA + 0x480, 0x10, // DMA + 0x4C2, 0xE, // DMA + 0x4D4, 0x2C, // DMA + + 0x461, 0x2, // Extended NMI + 0x464, 0x2, // Last Eisa Bus Muster granted + + 0x4D0, 0x2, // edge/level control registers + + 0xC84, 0x1, // System board enable + + // AST I/O Space used... + + 0x0E8, 0x1, // XBus configuration register + 0x0EB, 0x1, // BIOS Flash register + 0x0EC, 0x2, // Front panel display addr/data registers + + 0x36E, 0x2, // SuperIO Index/Data register set#1 + 0x398, 0x2, // SuperIO Index/Data register set#2 + + 0, 0 + } +}; + + +ULONG +HalpInitMP( + IN ULONG Phase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock + ); + +BOOLEAN +EBI2_InitIpi( + IN ULONG ProcessorID + ); + +BOOLEAN +EBI2_InitSpi( + IN ULONG ProcessorID + ); + +VOID +ASTEnableCaches(); + +extern CCHAR HalpIRQLtoVector[]; +extern ULONG MpCount; + +KSPIN_LOCK HalpSystemHardwareLock; + +BOOLEAN +HalInitSystem ( + IN ULONG Phase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock + ) + + +/*++ + +Routine Description: + + This function initializes the Hardware Architecture Layer (HAL) for an + x86 AST Manhattan system. + +Arguments: + + None. + +Return Value: + + A value of TRUE is returned is the initialization was successfully + complete. Otherwise a value of FALSE is returend. + +--*/ + +{ + PMEMORY_ALLOCATION_DESCRIPTOR Descriptor; + PLIST_ENTRY NextMd; + KIRQL CurrentIrql; + PKPRCB pPRCB; + ULONG BuildType; + + + pPRCB = KeGetCurrentPrcb(); + + if (Phase == 0) { + + HalpBusType = LoaderBlock->u.I386.MachineType & 0x00ff; + + // + // Verify Prcb version and build flags conform to + // this image + // + + BuildType = 0; +#if DBG + BuildType |= PRCB_BUILD_DEBUG; +#endif +#ifdef NT_UP + BuildType |= PRCB_BUILD_UNIPROCESSOR; +#endif + + if (pPRCB->MajorVersion != PRCB_MAJOR_VERSION) { + KeBugCheckEx (MISMATCHED_HAL, + 1, pPRCB->MajorVersion, PRCB_MAJOR_VERSION, 0); + } + + if (pPRCB->BuildType != BuildType) { + KeBugCheckEx (MISMATCHED_HAL, + 2, pPRCB->BuildType, BuildType, 0); + } + + + // + // Phase 0 initialization + // only called by P0 + // + + + HalpInitializePICs(); + + // + // Now that the PICs are initialized, we need to mask them to + // reflect the current Irql + // + + CurrentIrql = KeGetCurrentIrql(); + CurrentIrql = KfRaiseIrql(CurrentIrql); + + // + // Fill in handlers for APIs which this hal supports + // + + HalQuerySystemInformation = HaliQuerySystemInformation; + HalSetSystemInformation = HaliSetSystemInformation; + + // + // Initialize CMOS + // + + HalpInitializeCmos(); + + // + // Register base IO space used by hal + // + + HalpRegisterAddressUsage (&HalpDefaultASTIoSpace); + + HalpInitializeDisplay(); + + // + // Initialize spinlock used by HalGetBusData hardware access routines + // + + KeInitializeSpinLock(&HalpSystemHardwareLock); + + // + // Determine if there is physical memory above 16 MB. + // + + LessThan16Mb = TRUE; + + NextMd = LoaderBlock->MemoryDescriptorListHead.Flink; + + while (NextMd != &LoaderBlock->MemoryDescriptorListHead) { + Descriptor = CONTAINING_RECORD( NextMd, + MEMORY_ALLOCATION_DESCRIPTOR, + ListEntry ); + + if (Descriptor->BasePage + Descriptor->PageCount > 0x1000) { + LessThan16Mb = FALSE; + } + + NextMd = Descriptor->ListEntry.Flink; + } + + // + // Determine the size need for map buffers. If this system has + // memory with a physical address of greater than + // MAXIMUM_PHYSICAL_ADDRESS, then allocate a large chunk; otherwise, + // allocate a small chunk. + // + + if (LessThan16Mb) { + + // + // Allocate a small set of map buffers. They are only need for + // slave DMA devices. + // + + HalpMapBufferSize = INITIAL_MAP_BUFFER_SMALL_SIZE; + + } else { + + // + // Allocate a larger set of map buffers. These are used for + // slave DMA controllers and Isa cards. + // + + HalpMapBufferSize = INITIAL_MAP_BUFFER_LARGE_SIZE; + + } + + // + // Allocate map buffers for the adapter objects + // + + HalpMapBufferPhysicalAddress.LowPart = + HalpAllocPhysicalMemory (LoaderBlock, MAXIMUM_PHYSICAL_ADDRESS, + HalpMapBufferSize >> PAGE_SHIFT, TRUE); + HalpMapBufferPhysicalAddress.HighPart = 0; + + + if (!HalpMapBufferPhysicalAddress.LowPart) { + + // + // There was not a satisfactory block. Clear the allocation. + // + + HalpMapBufferSize = 0; + } + + } else { + + // + // Phase 1 initialization + // + + // + // Enable caching on the processor + // + + ASTEnableCaches(); + + if (pPRCB->Number == 0) { + HalpRegisterInternalBusHandlers (); + } + + // + // Initialize the profile interrupt vector. + // + + KiSetHandlerAddressToIDT( HalpIRQLtoVector[PROFILE_LEVEL], + HalpProfileInterrupt); + + // + // enable PROFILE interrupt + // + + HalEnableSystemInterrupt( HalpIRQLtoVector[PROFILE_LEVEL], + PROFILE_LEVEL, Latched); + + // + // Initialize stall execution on each processor + // + + HalpInitializeStallExecution(KeGetPcr()->Prcb->Number); + + HalStopProfileInterrupt(0); + + // + // Initialize the clock interrupt vector + // + // + + KiSetHandlerAddressToIDT( HalpIRQLtoVector[CLOCK2_LEVEL], + HalpClockInterrupt); + + // + // enable CLOCK2 interrupt + // + + HalEnableSystemInterrupt( HalpIRQLtoVector[CLOCK2_LEVEL], + CLOCK2_LEVEL, Latched); + +// HalpEnableInterruptHandler ( +// DeviceUsage, // Report as device vector +// 8, // Bus interrupt level +// HalpIRQLtoVector[CLOCK2_LEVEL], // System IDT +// CLOCK2_LEVEL, // System Irql +// HalpClockInterrupt, // ISR +// Latched ); + + // + // Initialize the IPI vector + // + + EBI2_InitIpi(KeGetPcr()->Prcb->Number); + + // + // Initialize the SPI vector + // + + EBI2_InitSpi(KeGetPcr()->Prcb->Number); + + // + // If this is the first processor, initialize the clock + // + + if (pPRCB->Number == 0) { + HalpInitializeClock(); + } + } + + HalpInitMP(Phase, LoaderBlock); + + return TRUE; +} diff --git a/private/ntos/nthals/halast/i386/astipi.asm b/private/ntos/nthals/halast/i386/astipi.asm new file mode 100644 index 000000000..bb8467d6a --- /dev/null +++ b/private/ntos/nthals/halast/i386/astipi.asm @@ -0,0 +1,268 @@ + title "Interprocessor Interrupt" +;++ +; +;Copyright (c) 1991 Microsoft Corporation +;Copyright (c) 1992 AST Research Inc. +; +;Module Name: +; +; astipi.asm +; +;Abstract: +; +; AST Manhattan IPI code. +; Provides the HAL support for Interprocessor Interrupts for the +; MP Manhattan implementation. +; +;Author: +; +; Ken Reneris (kenr) 13-Jan-1992 +; Bob Beard (v-bobb) 24-Jul-1992 added support for AST EBI2 machines +; +;Revision History: +; +; Quang Phan (v-quangp) 15-Dec-1992: Added code to get ProcIntHandle +; for FastSetLocalIntMask calls. +; +; Quang Phan (v-quangp) 27-Aug-1992: Changed back to call ASTInitEBI2 +; at HalInitialzeProcessor (was at detectAST()). +;-- +.386p + .xlist + +; +; Normal includes +; + +include hal386.inc +include callconv.inc +include i386\astmp.inc +include i386\kimacro.inc +include i386\ix8259.inc + + EXTRNP _KiCoprocessorError,0,IMPORT + EXTRNP Kei386EoiHelper,0,IMPORT + EXTRNP _HalBeginSystemInterrupt,3 + EXTRNP _HalEndSystemInterrupt,2 + EXTRNP _KiIpiServiceRoutine,2,IMPORT + EXTRNP _HalEnableSystemInterrupt,3 + EXTRNP _HalpInitializePICs,0 + EXTRNP _HalDisplayString,1 + EXTRNP _HalEnableSystemInterrupt,3 + EXTRNP _HalDisableSystemInterrupt,2 + EXTRNP _DetectAST,1 + EXTRNP _DisplPanel,1 + EXTRNP _EBI2_InitIpi,1 + EXTRNP _ASTInitEBI2,0 + EXTRNP _KeSetTimeIncrement,2,IMPORT + extrn _HalpIRQLtoVector:BYTE + extrn _EBI2_CallTab:DWORD + extrn _EBI2_MMIOTable:DWORD + extrn EBI2_InitLocalIntFunctions:NEAR + extrn _HalpDefaultInterruptAffinity:DWORD + +_DATA SEGMENT DWORD PUBLIC 'DATA' + + public _HalpProcessorPCR, _HalpInitializedProcessors +_HalpProcessorPCR dd MAXIMUM_PROCESSORS dup (?) ; PCR pointer for each processor +_HalpInitializedProcessors dd 0 + +BadHalString db 'HAL: AST HAL.DLL cannot be run on non AST MP machine',cr,lf + db ' or AST MP machine not configured properly.',cr, lf + db ' Replace the hal.dll with the correct hal', cr, lf + db ' or configure the machine properly', cr, lf + db ' System is HALTING *********', 0 + +BadEBIString db 'HAL: AST EBI2 cannot be initialized',cr,lf + db ' System is HALTING *********', 0 + +MPFlag db 0 ; Flag for MP determination + +_DATA ends + + page ,132 + subttl "Post InterProcessor Interrupt" +_TEXT SEGMENT DWORD PUBLIC 'CODE' + ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING + + +;++ +; +; VOID +; HalInitializeProcessor( +; ULONG Number +; ); +; +;Routine Description: +; +; Initialize hal pcr values for current processor (if any) +; (called shortly after processor reaches kernel, before +; HalInitSystem if P0) +; +; IPI's and KeReadir/LowerIrq's must be available once this function +; returns. (IPI's are only used once two or more processors are +; available) +; +; . Enable IPI interrupt (makes sense for P1, P2, ...). +; . Save Processor Number in PCR. +; . if (P0) +; . determine what kind of system is it, +; . if (NotAST_EBI2) Halt; +; . Enable PINTs on CPU. +; +;Arguments: +; +; Number - Logical processor number of calling processor +; +;Return Value: +; +; None. +; +;-- +cPublicProc _HalInitializeProcessor,1 + + ; Set initial interrupt bit mask for this processor + + mov dword ptr fs:PcIDR, MaskAllIrqs ; Set to EBI2 Bit mask + + ; EBI2 processor ID = NT processor ID + + mov eax, [esp+4] ; Save processor # in PCR + mov fs:PcHal.PcrEBI2ProcessorID, eax + lock bts _HalpDefaultInterruptAffinity, eax + lock inc _HalpInitializedProcessors + + mov ecx, fs:PcSelfPcr ; Flat address of this PCR + mov _HalpProcessorPCR[eax*4], ecx ; Save it away + + mov dword ptr fs:PcStallScaleFactor, INITIAL_STALL_COUNT + + push eax + mov eax, TIME_INCREMENT + stdCall _KeSetTimeIncrement, <eax, eax> + pop eax + + mov dword ptr fs:PcHal.PcrCpuLedRateCount, 0 ;init CpuLed rate count + + or eax, eax + jnz ipi_10 + + ; Run on P0 only + +; Detect if AST machine + stdCall _DetectAST,<offset MPFlag> + or eax, eax + jz NotAST + + stdCall _ASTInitEBI2 ; Init EBI2 + or eax,eax + jz EBI2InitProblem + + ; Done with P0 initialization + +ipi_10: + +ifdef QPTEST + +; Enable IPIs for each processor + +; push the processor number + stdCall _EBI2_InitIpi,<[esp+4]> + or eax, eax + jz NotAST + +endif +; +;Initialize data structure for EBI SetLocalMask call +; + call EBI2_InitLocalIntFunctions + or eax,eax + jnz EBI2InitProblem + +; +;Store EBI2 MMIO_Table for later use. +; + lea eax,_EBI2_MMIOTable + mov fs:PcHal.PcrEBI2MMIOtable, eax + + stdRET _HalInitializeProcessor + +NotAST: + stdCall _HalDisplayString, <offset BadHalString> +@@: jmp short @b + +EBI2InitProblem: + stdCall _HalDisplayString, <offset BadEBIString> +@@: jmp short @b + +stdENDP _HalInitializeProcessor + + +;++ +; +; VOID +; HalpIPInterrupt ( +; ); +; +; Routine Description: +; +; This routine is entered as the result of an interrupt generated by the +; IPI hardware. +; +; Arguments: +; +; None. +; Interrupt is dismissed +; +; Return Value: +; +; None. +; +;-- + + ENTER_DR_ASSIST Hipi_a, Hipi_t +cPublicProc _HalpIPInterrupt,0 + +; +; Save machine state in trap frame +; + ENTER_INTERRUPT Hipi_a, Hipi_t ; (ebp) -> Trap frame +; +; Save previous IRQL +; + + movzx eax, _HalpIRQLtoVector[IPI_LEVEL] + push eax ;interrupt vector + sub esp, 4 ;space for OldIrql + +; esp &OldIrql +; eax interrupt vector +; IPI_LEVEL new Irql + ;raise to new Irql + stdCall _HalBeginSystemInterrupt,<IPI_LEVEL,eax,esp> + or al, al + jz Hipi100 ;jump if spurrious interrupt + +; Pass Null ExceptionFrame +; Pass TrapFrame to Ipi service rtn + + stdCall _KiIpiServiceRoutine,<ebp,0> + + +; +; Do interrupt exit processing +; + INTERRUPT_EXIT ; will return to caller + +Hipi100: + + DisplPanel HalSpuriousInterrupt4 + + add esp, 8 ; spurious, no EndOfInterrupt + EXIT_ALL ,,NoPreviousMode ; without lowering irql + +stdENDP _HalpIPInterrupt + +_TEXT ENDS + END + diff --git a/private/ntos/nthals/halast/i386/astipirq.c b/private/ntos/nthals/halast/i386/astipirq.c new file mode 100644 index 000000000..88d7beb83 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astipirq.c @@ -0,0 +1,155 @@ +/*++ + +Copyright (c) 1992 AST Research Inc. + +Module Name: + + astipirq.c + +Abstract: + + IPI interrupt generation and initialization + + +Author: + + Bob Beard (v-bobb) 24-Jul-1992 + +Environment: + + Kernel mode only. + +Revision History: + +--*/ + +#include "halp.h" +#include "astebiii.h" +#include "astdisp.h" + +extern VOID* EBI2_MMIOTable[]; +extern EBI_II EBI2_CallTab; +extern CCHAR HalpIRQLtoVector[]; +VOID DisplPanel(ULONG x); +VOID HalpIPInterrupt(VOID); +VOID HalpSPInterrupt(VOID); + +KSPIN_LOCK EBI2_ipi_lock; + +BOOLEAN +EBI2_InitIpi( + IN ULONG ProcessorID + ) +/*++ + +Routine Description: + Initialize the IPI for this processor + +Arguments: + ProcessorID - The EBI2 processor to be initialized for IPI + +Return Value: + TRUE if IPI set up properly. FALSE otherwise. + +--*/ +{ + +// *** Hack to get around EBI2 problem of destroying ebx on call +// to SetIpiVector +ULONG EBI2_Hack_Val; + +EBI2_Hack_Val = ProcessorID+1; + +if ( EBI2_CallTab.SetIPIVector( EBI2_MMIOTable, ProcessorID, + HalpIRQLtoVector[IPI_LEVEL] ) ) + {DisplPanel(HALIpiInitVecProblem); return(FALSE); } + +//if ( EBI2_CallTab.SetIPIID( EBI2_MMIOTable, ProcessorID, +// (1 << ProcessorID) ) ) +if ( EBI2_CallTab.SetIPIID( EBI2_MMIOTable, (EBI2_Hack_Val-1), + (1 << (EBI2_Hack_Val-1) ) ) ) + {DisplPanel(HALIpiInitIDProblem); return(FALSE); } + + +KiSetHandlerAddressToIDT( HalpIRQLtoVector[IPI_LEVEL], HalpIPInterrupt ); + +KeInitializeSpinLock( &EBI2_ipi_lock ); + +HalEnableSystemInterrupt( HalpIRQLtoVector[IPI_LEVEL], IPI_LEVEL, Latched ); + +return(TRUE); + +} + +VOID +HalRequestIpi( + IN ULONG Mask + ) +/*++ + +Routine Description: + Generate an IPI to each processor requested in the Mask + +Arguments: + Mask - a bit mask of the processors to be interrupted + +Return Value: + None. + +--*/ +{ + + _asm { + pushfd + cli + } + + KiAcquireSpinLock( &EBI2_ipi_lock); + EBI2_CallTab.GenIPI( EBI2_MMIOTable, Mask ); + KiReleaseSpinLock( &EBI2_ipi_lock); + + _asm { + popfd + } +} + +BOOLEAN +EBI2_InitSpi( + IN ULONG ProcessorID + ) +/*++ + +Routine Description: + Initialize the SPI for this processor + +Arguments: + ProcessorID - The EBI2 processor to be initialized for SPI + +Return Value: + TRUE if SPI set up properly. FALSE otherwise. + +--*/ +{ + +// +// Set the vector for SPI +// + +if ( EBI2_CallTab.SetSPIVector( EBI2_MMIOTable, ProcessorID, + HalpIRQLtoVector[POWER_LEVEL] ) ) + {DisplPanel(HALSpiInitVecProblem); return(FALSE); } + + +KiSetHandlerAddressToIDT( HalpIRQLtoVector[POWER_LEVEL], HalpSPInterrupt ); + +HalEnableSystemInterrupt( HalpIRQLtoVector[POWER_LEVEL], POWER_LEVEL, Latched ); + +// +// Make the switches visible to software +// + +EBI2_CallTab.SetPanelSwitchVisibility( EBI2_MMIOTable, PANEL_SWITCHES_VISIBLE); + +return(TRUE); + +} diff --git a/private/ntos/nthals/halast/i386/astirql.asm b/private/ntos/nthals/halast/i386/astirql.asm new file mode 100644 index 000000000..349984167 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astirql.asm @@ -0,0 +1,1110 @@ + title "Irql Processing" +;++ +; +; Copyright (c) 1989 Microsoft Corporation +; Copyright (c) 1992 AST Research Inc. +; +; Module Name: +; +; astirql.asm +; +; Abstract: +; +; ASTMP IRQL +; +; This module implements the code necessary to raise and lower i386 +; Irql and dispatch software interrupts with the AST MP hardware. +; +; Author: +; +; Shie-Lin Tzong (shielint) 8-Jan-1990 +; +; Environment: +; +; Kernel mode only. +; +; Revision History: +; +; Quang Phan (v-quangp) 15-Dec-92 +; Implemented the fast SetLocalInterruptMask in Raise/LowerIrql. +; Removed spinlock in Raise/LowerIrql routines. +; +; Quang Phan (v-quangp) 24-Jul-1992 +; Converted to AST MP hardware. +; +; John Vert (jvert) 27-Nov-1991 +; Moved from kernel into HAL +; +;-- + +.386p + .xlist +include hal386.inc +include callconv.inc +include mac386.inc +include i386\ix8259.inc +include i386\kimacro.inc +include i386\astebi2.inc +include i386\astmp.inc + .list + + + EXTRNP _KeBugCheck,1,IMPORT + + extrn _HalpApcInterrupt:NEAR + extrn _HalpDispatchInterrupt:NEAR + extrn _HalpApcInterrupt2ndEntry:NEAR + extrn _HalpDispatchInterrupt2ndEntry:NEAR + extrn _KiUnexpectedInterrupt:NEAR + extrn _HalpBusType:DWORD + extrn _EBI2_CallTab:DWORD + extrn _EBI2_MMIOTable:DWORD + extrn _EBI2_Lock:DWORD + extrn HalpIRQLtoEBIIntNumber:DWORD + extrn _EBI2_revision:DWORD + EXTRNP _DisplPanel,1 + EXTRNP Kei386EoiHelper,0,IMPORT + EXTRNP _KiDispatchInterrupt,0,IMPORT +; +; Interrupt flag bit maks for EFLAGS +; +EFLAGS_IF equ 200H +EFLAGS_SHIFT equ 9 +; +; +; IRQL level of hardware interrupts +; +HARDWARE_LEVEL equ 12 + +_DATA SEGMENT DWORD PUBLIC 'DATA' +; +;;;;;;;;;;;;;;;; +; +; Information for irq, irql and mask (EBI2) translation +; +;System System Bus +;IRQL EBI Vector IRQ Common use Name +;----- --- ------ ------ ---------- ---- +; 00 LOW_LEV +; 01 APC_LEVEL +; 02 25 ??? LSI DPC_LEVEL +; 03 WAKE_LEVEL +; 04 +; 05 +; 06 +; 07 +; 08 +; 09 +; 10 +; 11 +; 12 7 PVB+7 EISA IRQ7 LPT1 +; 13 6 PVB+6 EISA IRQ6 Flpy +; 14 5 PVB+5 EISA IRQ5 LPT2 +; 15 4 PVB+4 EISA IRQ4 COM1 +; 16 3 PVB+3 EISA IRQ3 COM2 +; 17 15 PVB+15 EISA IRQ15 +; 18 14 PVB+14 EISA IRQ14 AT disk +; 19 13 PVB+13 EISA IRQ13 +; 20 12 PVB+12 EISA IRQ12 +; 21 11 PVB+11 EISA IRQ11 +; 22 10 PVB+10 EISA IRQ10 +; 23 9 PVB+9 EISA IRQ9 +; 24 8 PVB+8 EISA IRQ8 +; 25 2 PVB+9 EISA IRQ2 (IRQ chaining) +; 26 1 PVB+1 EISA IRQ1 Kbd +; 27 0 PVB+0 EISA IRQ8 RTC PROFILE_LEVEL +; 28 8 PVB EISA IRQ0 CLOCK2_LEVEL +; 29 26 PVB+26 IPI IPI_LEVELx +; 30 24 PVB+24 SPI POWER_LEVEL +; 31 HIGH_LEVEL +; +; +; Notes: +; 1. PVB: PRIMARY_VECTOR_BASE = 30h (PIC1BASE = 30h, PIC2BASE = 38h) +; +;;;;;;;;;;;;;;;; +; +; CCHAR HalpIRQLtoEBIBitMask[32]; This array is used to get the value +; for the EBI bitmask from the KIRQL. + Public _HalpIRQLtoEBIBitMask + align 4 +_HalpIRQLtoEBIBitMask Label Byte + dd 0 ;IRQL 0 (Unused Mask) + dd 0 ;IRQL 1 + dd 1 SHL (IRQ_25) ;IRQL 2 (EBI IRQ-25) + dd 0 ;IRQL 3 + dd 0 ;IRQL 4 + dd 0 ;IRQL 5 + dd 0 ;IRQL 6 + dd 0 ;IRQL 7 + dd 0 ;IRQL 8 + dd 0 ;IRQL 9 + dd 0 ;IRQL 10 + dd 0 ;IRQL 11 + dd 1 SHL (IRQ_7) ;IRQL 12 + dd 1 SHL (IRQ_6) ;IRQL 13 + dd 1 SHL (IRQ_5) ;IRQL 14 + dd 1 SHL (IRQ_4) ;IRQL 15 + dd 1 SHL (IRQ_3) ;IRQL 16 + dd 1 SHL (IRQ_15) ;IRQL 17 + dd 1 SHL (IRQ_14) ;IRQL 18 + dd 1 SHL (IRQ_13) ;IRQL 19 + dd 1 SHL (IRQ_12) ;IRQL 20 + dd 1 SHL (IRQ_11) ;IRQL 21 + dd 1 SHL (IRQ_10) ;IRQL 22 + dd 1 SHL (IRQ_9) ;IRQL 23 + dd 1 SHL (IRQ_8) ;IRQL 24 + dd 1 SHL (IRQ_2) ;IRQL 25 + dd 1 SHL (IRQ_1) ;IRQL 26 + dd 1 SHL (IRQ_8) ;IRQL 27 (IRQ-8) (Profile clock) + dd 0 ;IRQL 28 (IRQ-0) (clock) + dd 1 SHL (IRQ_26) ;IRQL 29 (IPI-0) + dd 1 SHL (IRQ_24) ;IRQL 30 (SPI-0) + dd 0 ;IRQL 31 +; +; CCHAR HalpIRQLtoVector[36]; this array is used to get the interrupt +; vector used for a given KIRQL, zero +; means no vector is used for the KIRQL + Public _HalpIRQLtoVector +_HalpIRQLtoVector Label Byte +; ;IRQL + db 0 ;0 + db 0 ;1 APC_LEVEL + db 0 ;2 DISPATCH_LEVEL + db 0 ;3 WAKE_LEVEL + db 0 ;4 + db 0 ;5 + db 0 ;6 + db 0 ;7 + db 0 ;8 + db 0 ;9 + db 0 ;10 + db 0 ;11 + db PRIMARY_VECTOR_BASE+7 ;12 irq7 + db PRIMARY_VECTOR_BASE+6 ;13 irq6 + db PRIMARY_VECTOR_BASE+5 ;14 irq5 + db PRIMARY_VECTOR_BASE+4 ;15 irq4 + db PRIMARY_VECTOR_BASE+3 ;16 irq3 + db PRIMARY_VECTOR_BASE+15 ;17 irq15 + db PRIMARY_VECTOR_BASE+14 ;18 irq14 + db PRIMARY_VECTOR_BASE+13 ;19 irq13 + db PRIMARY_VECTOR_BASE+12 ;20 irq12 + db PRIMARY_VECTOR_BASE+11 ;21 irq11 + db PRIMARY_VECTOR_BASE+10 ;22 irq10 + db PRIMARY_VECTOR_BASE+9 ;23 irq9 + db PRIMARY_VECTOR_BASE+8 ;24 irq8 + db 0 ;25 irq2 (used for chaining) + db PRIMARY_VECTOR_BASE+1 ;26 irq1 + db PRIMARY_VECTOR_BASE+8 ;27 irq8 PROFILE_LEVEL + db PRIMARY_VECTOR_BASE ;28 irq0 CLOCK2_LEVEL + db PRIMARY_VECTOR_BASE+26 ;29 IPI_LEVEL + db PRIMARY_VECTOR_BASE+24 ;30 POWER_LEVEL (SPI) + db 0 ;prevent CPL 0 enable changes ;HIGH_LEVEL + db 0, 0, 0, 0 ;four extra levels for good luck + +; +; CCHAR HalpBusIntToIRQL[16]; this array is used to get the IRQL +; from the the Bus Interrupt number + Public _HalpBusIntToIRQL +_HalpBusIntToIRQL Label Byte +; IRQL ;Bus Interrupt number + db CLOCK2_LEVEL ;0 + db PROFILE_LEVEL-1 ;1 + db 0 ;2 + db PROFILE_LEVEL-11 ;3 + db PROFILE_LEVEL-12 ;4 + db PROFILE_LEVEL-13 ;5 + db PROFILE_LEVEL-14 ;6 + db PROFILE_LEVEL-15 ;7 + db PROFILE_LEVEL-3 ;8 + db PROFILE_LEVEL-4 ;9 + db PROFILE_LEVEL-5 ;10 + db PROFILE_LEVEL-6 ;11 + db PROFILE_LEVEL-7 ;12 + db PROFILE_LEVEL-8 ;13 + db PROFILE_LEVEL-9 ;14 + db PROFILE_LEVEL-10 ;15 + +; +;Translation table from Irql to EBI interrupt bit mask. This table is +;used for setting the processor interrupt level (irql) +; + public KiEBI2IntMaskTable +KiEBI2IntMaskTable label dword + align 4 + +; ILS <--- irqs -----> +; PSP +; III 11.. ..10 +; ... 54 .. +; vvv vv vv +; + dd 00000000000000000000000000000000B ; irql 0 + dd 00000000000000000000000000000000B ; irql 1 + dd 00000000000000000000000000000000B ; irql 2 + dd 00000000000000000000000000000000B ; irql 3 + dd 00000000000000000000000000000000B ; irql 4 + dd 00000010000000000000000000000000B ; irql 5 + dd 00000010000000000000000000000000B ; irql 6 + dd 00000010000000000000000000000000B ; irql 7 + dd 00000010000000000000000000000000B ; irql 8 + dd 00000010000000000000000000000000B ; irql 9 + dd 00000010000000000000000000000000B ; irql 10 + dd 00000010000000000000000000000000B ; irql 11 + dd 00000010000000000000000010000000B ; irql 12 irq7 + dd 00000010000000000000000011000000B ; irql 13 irq6 + dd 00000010000000000000000011100000B ; irql 14 irq5 + dd 00000010000000000000000011110000B ; irql 15 irq4 + dd 00000010000000000000000011111000B ; irql 16 irq3 + dd 00000010000000001000000011111000B ; irql 17 irq15 + dd 00000010000000001100000011111000B ; irql 18 irq14 + dd 00000010000000001110000011111000B ; irql 19 irq13 + dd 00000010000000001111000011111000B ; irql 20 irq12 + dd 00000010000000001111100011111000B ; irql 21 irq11 + dd 00000010000000001111110011111000B ; irql 22 irq10 + dd 00000010000000001111111011111000B ; irql 23 irq9 + dd 00000010000000001111111111111010B ; irql 24 irq8 + dd 00000010000000001111111011111000B ; irql 25 irq2 + dd 00000010000000001111111011111010B ; irql 26 irq1 + dd 00000010000000001111111111111010B ; irql 27 irq8 (Profile) + dd 00000010000000001111111111111011B ; irql 28 irq0 + dd 00000110000000001111111111111011B ; irql 29 ipi + dd 00000111000000001111111111111011B ; irql 30 spi + dd 00000111000000001111111111111011B ; irql 31 +; +; 10987654321098765432109876543210- ; bit position +; + align 4 +; +; The following tables define the addresses of software interrupt routers +; Use this table if there is NO machine state frame on stack already +; + public SWInterruptHandlerTable +SWInterruptHandlerTable label dword + dd offset FLAT:_KiUnexpectedInterrupt ; irql 0 + dd offset FLAT:_HalpApcInterrupt ; irql 1 + dd offset FLAT:_HalpDispatchInterrupt ; irql 2 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 3 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 4 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 5 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 6 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 7 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 8 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 9 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 10 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 11 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 12 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 13 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 14 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 15 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 16 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 17 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 18 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 19 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 20 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 21 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 22 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 23 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 24 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 25 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 26 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 27 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 28 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 29) + + public ASTSWInterruptHandlerTable +ASTSWInterruptHandlerTable label dword + dd offset FLAT:_KiUnexpectedInterrupt ; irql 0 + dd offset FLAT:_HalpApcInterrupt ; irql 1 + dd offset FLAT:_ASTDispatchInterrupt ; irql 2 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 3 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 4 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 5 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 6 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 7 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 8 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 9 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 10 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 11 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 12 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 13 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 14 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 15 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 16 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 17 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 18 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 19 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 20 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 21 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 22 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 23 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 24 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 25 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 26 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 27 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 28 + dd offset FLAT:_KiUnexpectedInterrupt ; irql 29) +; +; The following table picks up the highest pending software irq level +; from software irr +; + + public SWInterruptLookUpTable +SWInterruptLookUpTable label byte + db 0 ; SWIRR=0, so highest pending SW irql= 0 + db 0 ; SWIRR=1, so highest pending SW irql= 0 + db 1 ; SWIRR=2, so highest pending SW irql= 1 + db 1 ; SWIRR=3, so highest pending SW irql= 1 + db 2 ; SWIRR=4, so highest pending SW irql= 2 + db 2 ; SWIRR=5, so highest pending SW irql= 2 + db 2 ; SWIRR=6, so highest pending SW irql= 2 + db 2 ; SWIRR=7, so highest pending SW irql= 2 + db 3 ; SWIRR=8, so highest pending SW irql= 3 + db 3 ; SWIRR=9, so highest pending SW irql= 3 + db 3 ; SWIRR=A, so highest pending SW irql= 3 + db 3 ; SWIRR=B, so highest pending SW irql= 3 + db 3 ; SWIRR=C, so highest pending SW irql= 3 + db 3 ; SWIRR=D, so highest pending SW irql= 3 + db 3 ; SWIRR=E, so highest pending SW irql= 3 + db 3 ; SWIRR=F, so highest pending SW irql= 3 + + db 4 ; SWIRR=10, so highest pending SW irql= 4 + db 4 ; SWIRR=11, so highest pending SW irql= 4 + db 4 ; SWIRR=12, so highest pending SW irql= 4 + db 4 ; SWIRR=13, so highest pending SW irql= 4 + db 4 ; SWIRR=14, so highest pending SW irql= 4 + db 4 ; SWIRR=15, so highest pending SW irql= 4 + db 4 ; SWIRR=16, so highest pending SW irql= 4 + db 4 ; SWIRR=17, so highest pending SW irql= 4 + db 4 ; SWIRR=18, so highest pending SW irql= 4 + db 4 ; SWIRR=19, so highest pending SW irql= 4 + db 4 ; SWIRR=1A, so highest pending SW irql= 4 + db 4 ; SWIRR=1B, so highest pending SW irql= 4 + db 4 ; SWIRR=1C, so highest pending SW irql= 4 + db 4 ; SWIRR=1D, so highest pending SW irql= 4 + db 4 ; SWIRR=1E, so highest pending SW irql= 4 + db 4 ; SWIRR=1F, so highest pending SW irql= 4 + + + public EBI2_ProcIntHandle + public EBI2_maskInfo +EBI2_maskInfo dd 8 dup(0) +EBI2_ProcIntHandle dd 0 + + + + +_DATA ENDS + + page ,132 + subttl "Raise Irql" + +_TEXT SEGMENT DWORD PUBLIC 'CODE' + ASSUME DS:FLAT, ES:FLAT, SS:FLAT, FS:NOTHING, GS:NOTHING +;++ +; +; KIRQL +; FASTCALL +; KfRaiseIrql ( +; IN KIRQL NewIrql +; ) +; +; Routine Description: +; +; This routine is used to raise IRQL to the specified value. +; Also, a mask will be used to mask off all the lower lever 8259 +; interrupts. +; +; Arguments: +; +; (ecx) = NewIrql - the new irql to be raised to +; +; Return Value: +; +; OldIrql - the addr of a variable which old irql should be stored +; +;-- + +; equates for accessing arguments +; since eflags and iret addr are pushed into stack, all the arguments +; offset by 8 bytes +; + +cPublicFastCall KfRaiseIrql,1 +cPublicFpo 0,1 + + pushfd + cli + movzx eax,cl ; get new irql value + movzx ecx,byte ptr fs:PcIrql ; get current irql + +if DBG + cmp cl,al ; old > new? + jbe short Kri99 ; no, we're OK + push eax ; put new irql where we can find it + push ecx ; put old irql where we can find it + mov byte ptr fs:PcIrql,0 ; avoid recursive error + stdCall _KeBugCheck, <IRQL_NOT_GREATER_OR_EQUAL> +Kri99: +endif + mov fs:PcIrql, al ; set the new irql + cmp al,HARDWARE_LEVEL ; software level? + jb short kri10 ; go skip setting 8259 hardware + +; +;Disable interrupt locally. Depending on type of hardware this function +;will jump to the appropriate code that was setup priviously via the +;PcrEBI2SetLocalIntMaskFunction pointer +; + mov eax,KiEBI2IntMaskTable[eax*4] ;get ebi2 bitmask (eax=irql) + or eax,fs:PcIDR ;mask off irq which disabled + jmp dword ptr fs:[PcHal.PcrEBI2RaiseIrqlFunction] + + +;---------------------------- +; +;Code for using direct hardware access (32-bit interface hw) +; +KriDirectAccessIntMask32: + + mov edx,fs:PcHal.PcrEBI2portAddress0 + mov dword ptr [edx], eax + mov eax, dword ptr [edx] ;flush write buffer +; +; +; Note: It is very important that we set the old irql AFTER we raised to +; the new irql. Otherwise, if there is an interrupt that comes in between +; and the OldIrql is not a local variable, the caller will get the wrong +; OldIrql. The bottom line is the raising irql and returning old irql has +; to be atomic to the caller. + +kri10: + mov eax, ecx ; (al) = OldIrql + popfd ; restore flags (including interrupts) + + fstRET KfRaiseIrql + + + +;---------------------------- +; +;Code for using direct hardware access (8-bit interface hw) +; +KriDirectAccessIntMask8: + + mov edx,fs:PcHal.PcrEBI2portAddress0 + mov byte ptr [edx], al + mov edx,fs:PcHal.PcrEBI2portAddress1 + mov byte ptr [edx], ah + shr eax,24 ;get mask bit 24-31 + mov edx,fs:PcHal.PcrEBI2portAddress3 + mov byte ptr [edx], al + mov al, byte ptr [edx] ;flush write buffer + + mov eax, ecx ; (al) = OldIrql + popfd ; restore flags (including interrupts) + + fstRET KfRaiseIrql + + + +;---------------------------- +; +;Code for using RegisterEBI2 Call +;eax=intMask +; +KriRegSetLocalIntMask: + + push esi + push ecx + mov esi,fs:PcHal.PcrEBI2ProcInterruptHandle + lea edx, _EBI2_CallTab + call [edx]+RegSetLocalIntMask + pop esi ;restore esi + pop eax + + popfd ; restore flags (including interrupts) + fstRET KfRaiseIrql + +fstENDP KfRaiseIrql + + + page ,132 + subttl "Lower irql" + +;++ +; +; VOID +; FASTCALL +; KfLowerIrql ( +; IN KIRQL NewIrql +; ) +; +; Routine Description: +; +; This routine is used to lower IRQL to the specified value. +; The IRQL and PIRQL will be updated accordingly. Also, this +; routine checks to see if any software interrupt should be +; generated. The following condition will cause software +; interrupt to be simulated: +; any software interrupt which has higher priority than +; current IRQL's is pending. +; +; NOTE: This routine simulates software interrupt as long as +; any pending SW interrupt level is higher than the current +; IRQL, even when interrupts are disabled. +; +; Arguments: +; +; (cl) = NewIrql - the new irql to be set. +; +; Return Value: +; +; None. +; +;-- + + +cPublicFastCall KfLowerIrql,1 + pushfd ; save caller's eflags + cli + movzx ecx, cl ; get new irql value + mov al, fs:PcIrql ; get old irql value + +if DBG + cmp cl,al + jbe short Kli99 + push ecx ; new irql for debugging + push fs:PcIrql ; old irql for debugging + mov byte ptr fs:PcIrql,HIGH_LEVEL ; avoid recursive error + stdCall _KeBugCheck, <IRQL_NOT_LESS_OR_EQUAL> +Kli99: +endif + cmp al,HARDWARE_LEVEL ; see if hardware was masked + jb short Soft_Ints + + +; +;Disable interrupt locally. Depending on type of hardware this function +;will jump to the appropriate code that was setup priviously via the +;PcrEBI2SetLocalIntMaskFunction pointer +; + mov eax,KiEBI2IntMaskTable[ecx*4] ;get ebi2 bitmask (eax=irql) + jmp dword ptr fs:[PcHal.PcrEBI2LowerIrqlFunction] + + +;---------------------------- +; +;Code for using direct hardware access (32-bit interface hw) +; +KliDirectAccessIntMask32: + + or eax,fs:PcIDR ;mask off irq which disabled + mov edx,fs:PcHal.PcrEBI2portAddress0 + mov dword ptr [edx], eax + mov eax, dword ptr [edx] ;flush write buffer + +Soft_Ints: + mov fs:PcIrql, cl ; save new IRQL +Kli02a: + mov edx, fs:dword ptr PcIRR + and edx,0Eh ; mask for valid IRR bits + jnz short Kli09a ; jump if yes + +Kli08a: + popfd ; restore flags, including ints + fstRET KfLowerIrql ; RETURN + +Kli09a: + movzx eax, SWInterruptLookUpTable[edx] +; +;When we come to Kli10a, (eax) = soft interrupt index +; +Kli10a: + cmp al, fs:PcIrql ; compare with current IRQL + jna short Kli08a ; jump if higher priority + + call ASTSWInterruptHandlerTable[eax*4] ; SIMULATE INTERRUPT + ; to the appropriate handler + jmp short Kli02a ; check for another + + + +;---------------------------- +; +;Code for using direct hardware access (8-bit interface hw) +; +KliDirectAccessIntMask8: + + or eax,fs:PcIDR ;mask off irq which disabled + mov edx,fs:PcHal.PcrEBI2portAddress0 + mov byte ptr [edx], al + mov edx,fs:PcHal.PcrEBI2portAddress1 + mov byte ptr [edx], ah + shr eax,24 ;get mask bit 24-31 + mov edx,fs:PcHal.PcrEBI2portAddress3 + mov byte ptr [edx], al + mov al, byte ptr [edx] ;flush write buffer + + mov fs:PcIrql, cl ; save new IRQL +Kli02: + mov edx, fs:dword ptr PcIRR + and edx,0Eh ; mask for valid IRR bits + jnz short Kli09 ; jump if yes + +Kli08: + popfd ; restore flags, including ints + fstRET KfLowerIrql ; RETURN + +Kli09: + movzx eax, SWInterruptLookUpTable[edx] +; +;When we come to Kli10, (eax) = soft interrupt index +; +Kli10: + cmp al, fs:PcIrql ; compare with current IRQL + jna short Kli08 ; jump if higher priority + + call ASTSWInterruptHandlerTable[eax*4] ; SIMULATE INTERRUPT + ; to the appropriate handler + jmp short Kli02 ; check for another + + +;---------------------------- +; +;Code for using RegisterEBI2 Call +;eax=intMask +; +KliRegSetLocalIntMask: + + or eax,fs:PcIDR ;mask off irq which disabled + push esi + mov esi,fs:PcHal.PcrEBI2ProcInterruptHandle + lea edx, _EBI2_CallTab + call [edx]+RegSetLocalIntMask + pop esi + + mov fs:PcIrql, cl ; save new IRQL +Kli02b: + mov edx, fs:dword ptr PcIRR + and edx,0Eh ; mask for valid IRR bits + jnz short Kli09b ; jump if yes + +Kli08b: + popfd ; restore flags, including ints + fstRET KfLowerIrql ; RETURN + +Kli09b: + movzx eax, SWInterruptLookUpTable[edx] +; +;When we come to Kli10b, (eax) = soft interrupt index +; +Kli10b: + cmp al, fs:PcIrql ; compare with current IRQL + jna short Kli08b ; jump if higher priority + + call ASTSWInterruptHandlerTable[eax*4] ; SIMULATE INTERRUPT + ; to the appropriate handler + jmp short Kli02b ; check for another +fstENDP KfLowerIrql + +cPublicProc _HalpEndSoftwareInterrupt,1 +cPublicFpo 1,0 + mov ecx, [esp+4] + fstCall KfLowerIrql + stdRet _HalpEndSoftwareInterrupt +stdENDP _HalpEndSoftwareInterrupt + + + +;++ +; +; VOID +; HalpEndSystemInterrupt +; IN KIRQL NewIrql, +; IN ULONG Vector +; ) +; +; Routine Description: +; +; This routine is used to lower IRQL to the specified value. +; The IRQL and PIRQL will be updated accordingly. Also, this +; routine checks to see if any software interrupt should be +; generated. The following condition will cause software +; interrupt to be simulated: +; any software interrupt which has higher priority than +; current IRQL's is pending. +; +; NOTE: This routine simulates software interrupt as long as +; any pending SW interrupt level is higher than the current +; IRQL, even when interrupts are disabled. +; +; Arguments: +; +; NewIrql - the new irql to be set. +; +; Vector - Vector number of the interrupt +; +; Note that esp+8 is the beginning of interrupt/trap frame and upon +; entering to this routine the interrupts are off. +; +; Return Value: +; +; None. +; +;-- +HeiNewIrql equ byte ptr [esp + 4] +HeiVector equ byte ptr [esp + 8] + +cPublicProc _HalEndSystemInterrupt,2 + + lea eax, _EBI2_Lock +EndIntAcquire: + cli + ACQUIRE_SPINLOCK eax, EndIntSpin +; + movzx eax, HeiVector + ; to EOI + sub eax, PRIMARY_VECTOR_BASE ; get EBI2 Interrupt number + push eax ; EOI the interrupt + CALL_EBI2 MaskableIntEOI,2 + +if DBG + or eax, eax + je EOI_OK + DisplPanel HalEndSystemInterruptEnter +EOI_OK: +endif ;DBG +; + lea eax, _EBI2_Lock +EndIntRelease: + RELEASE_SPINLOCK eax + + mov ecx, dword ptr HeiNewIrql + fstCall KfLowerIrql + stdRet _HalEndSystemInterrupt + +EndIntSpin: + SPIN_ON_SPINLOCK eax, EndIntAcquire + + +stdENDP _HalEndSystemInterrupt + +;++ +; +; VOID +; ASTDispatchInterrupt( +; VOID +; ); +; +; Routine Description: +; +; This is HalpDispatchInterrupt from IXSWINT.ASM. It's a pre-ship +; fix for a stack overflow condition found on an AST machine. +; This function assumes that the caller will re-check for a DPC +; interrupt and loop, whereas the normal HalpDispatchInterrupt calls +; lowerirql. +; +; Arguments: +; Return Value: +;-- + + ENTER_DR_ASSIST ahdpi_a, ahdpi_t + + align dword + public _ASTDispatchInterrupt +_ASTDispatchInterrupt proc +; +; Create IRET frame on stack +; + pop eax + pushfd + push cs + push eax + +; +; Save machine state on trap frame +; + + ENTER_INTERRUPT ahdpi_a, ahdpi_t +.FPO ( FPO_LOCALS+1, 0, 0, 0, 0, FPO_TRAPFRAME ) + +; Save previous IRQL and set new priority level + + push PCR[PcIrql] ; save previous IRQL + mov byte ptr PCR[PcIrql], DISPATCH_LEVEL; set new irql + btr dword ptr PCR[PcIRR], DISPATCH_LEVEL; clear the pending bit in IRR + +; +; Now it is safe to enable interrupt to allow higher priority interrupt +; to come in. +; + + sti + +; +; Go do Dispatch Interrupt processing +; + stdCall _KiDispatchInterrupt + +; +; Do interrupt exit processing +; + cli + pop eax ; saved irql + mov PCR[PcIrql], al ; restore it + + SPURIOUS_INTERRUPT_EXIT ; exit interrupt without EOI + ; (return to loop in LowerIrql) +_ASTDispatchInterrupt endp + + page ,132 + subttl "Specific Raise irql functions" +;++ +; +; VOID +; KIRQL +; KeRaiseIrqlToDpcLevel ( +; ) +; +; Routine Description: +; +; This routine is used to raise IRQL to DPC level. +; The APIC TPR is used to block all lower-priority HW interrupts. +; +; Arguments: +; +; Return Value: +; +; OldIrql - the addr of a variable which old irql should be stored +; +;-- + +cPublicProc _KeRaiseIrqlToDpcLevel,0 + + mov ecx, DISPATCH_LEVEL + jmp @KfRaiseIrql + +stdENDP _KeRaiseIrqlToDpcLevel + +;++ +; +; VOID +; KIRQL +; KeRaiseIrqlToSynchLevel ( +; ) +; +; Routine Description: +; +; This routine is used to raise IRQL to SYNC level. +; The APIC TPR is used to block all lower-priority HW interrupts. +; +; Arguments: +; +; Return Value: +; +; OldIrql - the addr of a variable which old irql should be stored +; +;-- + +cPublicProc _KeRaiseIrqlToSynchLevel,0 + + mov ecx, SYNCH_LEVEL + jmp @KfRaiseIrql + +stdENDP _KeRaiseIrqlToSynchLevel + + + page ,132 + subttl "Get current irql" + +;++ +; +; KIRQL +; KeGetCurrentIrql (VOID) +; +; Routine Description: +; +; This routine returns to current IRQL. +; +; Arguments: +; +; None. +; +; Return Value: +; +; The current IRQL. +; +;-- + +cPublicProc _KeGetCurrentIrql,0 + movzx eax, byte ptr fs:PcIrql ; Current irql is in the PCR + stdRET _KeGetCurrentIrql +stdENDP _KeGetCurrentIrql + + +;++ +; +; VOID +; HalpDisableAllInterrupts (VOID) +; +; Routine Description: +; +; This routine is called during a system crash. The hal needs all +; interrupts disabled. +; +; Arguments: +; +; None. +; +; Return Value: +; +; None - all interrupts are masked off +; +;-- + +cPublicProc _HalpDisableAllInterrupts,0 + + ; + ; Raising to HIGH_LEVEL disables interrupts for the ast HAL + ; + + mov ecx, HIGH_LEVEL + fstCall KfRaiseIrql + stdRET _HalpDisableAllInterrupts + +stdENDP _HalpDisableAllInterrupts + + + +;++ +; +; EBI2_InitLocalMaskFunctionPtr +; +; Routine Description: +; +; This routine is called during processor initialization (P1). +; It will setup the data structure used by RaiseIrql and LowerIrql. +; +; Arguments: +; +; None. +; +; Return Value: +; +; None +; +;-- + + + Public EBI2_InitLocalIntFunctions +EBI2_InitLocalIntFunctions Proc + +; +; Get EBI2 Revision#. This version of HAL requires EBI2 rev >= 2.9 +; If 2.9 then use RegSetLocalIntMask; Else, use directly access hw +; to set LocalIntMask. +; + lea eax, _EBI2_revision + cmp [eax].major,2 + jb EBI2_InitLocalIntRet + + cmp [eax].minor,9 + jb EBI2_InitLocalIntRet +; +; Get Processor's Interrupt handler for each processor +; + mov eax,offset EBI2_ProcIntHandle + push eax + mov eax,fs:PcHal.PcrEBI2ProcessorID + push eax ; push the processor number + CALL_EBI2 GetProcIntHandle,3 + or eax, eax + jnz EBI2_InitLocalIntRet + mov eax,EBI2_ProcIntHandle + mov dword ptr fs:PcHal.PcrEBI2ProcInterruptHandle,eax ;save int hdlr + +; +;Set function pointer for Raise and Lower Irql functions to use +;RegSetLocalIntMask as default +; + mov eax,offset FLAT:KriRegSetLocalIntMask + mov fs:PcHal.PcrEBI2RaiseIrqlFunction,eax + + mov eax,offset FLAT:KliRegSetLocalIntMask + mov fs:PcHal.PcrEBI2LowerIrqlFunction,eax +; +;Check for Rev.minor >= 10. If it is then use direct hardware access +;to set LocalIntMask. +; + lea eax, _EBI2_revision + cmp [eax].minor,10 + jb EBI2_InitLocalIntRet2 + +; +; Get Processor's LocalMaskInfo for each processor +; + mov eax,fs:PcHal.PcrEBI2ProcessorID + push eax ; push the processor number + mov eax,offset EBI2_maskInfo + push eax + CALL_EBI2 GetLocalIntMaskInfo,3 + or eax, eax + jnz EBI2_InitLocalIntRet + mov eax,EBI2_MaskInfo.portAddress0 + mov dword ptr fs:PcHal.PcrEBI2portAddress0,eax + mov eax,EBI2_MaskInfo.portAddress1 + mov dword ptr fs:PcHal.PcrEBI2portAddress1,eax + mov eax,EBI2_MaskInfo.portAddress2 + mov dword ptr fs:PcHal.PcrEBI2portAddress2,eax + mov eax,EBI2_MaskInfo.portAddress3 + mov dword ptr fs:PcHal.PcrEBI2portAddress3,eax + + mov eax,EBI2_MaskInfo.flags + and eax,PORT_TYPE_MASK + cmp eax,PORT_TYPE_MEMORY + jne short EBI2_InitLocalIntRet ;else set error exit + + mov eax,EBI2_MaskInfo.flags + and eax,PORT_WIDTH_MASK + cmp eax,THIRTY_TWO_BIT_PORT + je short EBI2_ILIF32 + cmp eax,EIGHT_BIT_PORTS + je short EBI2_ILIF08 + jmp short EBI2_InitLocalIntRet ;else set error exit + +EBI2_ILIF08: +; +;Set function pointer for Raise and Lower Irql to use +;direct hw access for setting LocalIntMask (8-bit hw). +; + mov eax,offset FLAT:KriDirectAccessIntMask8 + mov fs:PcHal.PcrEBI2RaiseIrqlFunction,eax + + mov eax,offset FLAT:KliDirectAccessIntMask8 + mov fs:PcHal.PcrEBI2LowerIrqlFunction,eax + jmp short EBI2_InitLocalIntRet2 + +EBI2_ILIF32: +; +;Set function pointer for Raise and Lower Irql to use +;direct hw access for setting LocalIntMask. (32-bit hw) +; + mov eax,offset FLAT:KriDirectAccessIntMask32 + mov fs:PcHal.PcrEBI2RaiseIrqlFunction,eax + + mov eax,offset FLAT:KliDirectAccessIntMask32 + mov fs:PcHal.PcrEBI2LowerIrqlFunction,eax + + +EBI2_InitLocalIntRet2: + xor eax,eax ;return status + +EBI2_InitLocalIntRet: + ret + +EBI2_InitLocalIntFunctions Endp + + +_TEXT ends + end diff --git a/private/ntos/nthals/halast/i386/astmp.inc b/private/ntos/nthals/halast/i386/astmp.inc new file mode 100644 index 000000000..ebb46a101 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astmp.inc @@ -0,0 +1,207 @@ +;++ +; +; Module Name: +; +; astmp.inc +; +; Abstract: +; +; ASTMP include file +; +; Author: +; Quang Phan (v-quangp) 25-Jul-1992 +; +; Modification: +; Quang Phan (v-quangp) 15-Sep-1993: +; Save MMIOtable and SPIsource in Pcr area. +; Quang Phan (v-quangp) 15-Dec-1992: +; Added new functions to the EBI2 call table. +; +;-- +;***************************** +; +; The kernel leaves some space (64 byte) of the PCR for the HAL to use +; as it needs. Currently this space is used for some efficiency in +; some of the MP specific code and is highly implementation +; dependant. +; +PcHalData struc + PcrEBI2ProcessorID dd 0 ; EBI2 ProcessorID + PcrCpuLedRateCount dd 0 ; Cur. cnt for sampling CPU LED + PcrEBI2ProcInterruptHandle dd 0 ; EBI2 Processor Interrupt handle + PcrEBI2RaiseIrqlFunction dd 0 ; EBI2 ProcessorID + PcrEBI2LowerIrqlFunction dd 0 ; EBI2 ProcessorID + PcrEBI2portAddress0 dd 0 ; EBI2 Addr for Port0 + PcrEBI2portAddress1 dd 0 ; EBI2 Addr for Port1 + PcrEBI2portAddress2 dd 0 ; EBI2 Addr for Port2 + PcrEBI2portAddress3 dd 0 ; EBI2 Addr for Port3 + PcrEBI2MMIOtable dd 0 ; Addr of EBI2MMIO_Table + PcrEBI2SPIsource dd 0 ; SPI sources +PcHalData ends +; +;EBI2 Function call table: +; +ebi_2_func_tbl struc + GetNumProcs dd ? ;Func # 1 + GetProcConf dd ? ;Func # 2 + StartProc dd ? ;Func # 3 + StopProc dd ? ;Func # 4 + GetProcID dd ? ;Func # 5 + EnableRAMCache dd ? ;Func # 6 + DisableRAMCache dd ? ;Func # 7 + FlushRAMCache dd ? ;Func # 8 + ControlCacheRegion dd ? ;Func # 9 + GetCacheControlInfo dd ? ;Func # 10 + SetPanelUPS dd ? ;Func # 11 + GetPanelUPS dd ? ;Func # 12 + SetPanelProcGraphMode dd ? ;Func # 13 + GetPanelProcGraphMode dd ? ;Func # 14 + SetPanelProcGraphValue dd ? ;Func # 15 + GetPanelProcGraphValue dd ? ;Func # 16 + LogProcIdle dd ? ;Func # 17 + LogProcBusy dd ? ;Func # 18 + GetPanelAttnSwitchLatch dd ? ;Func # 19 + GetPanelOffSwitchLatch dd ? ;Func # 20 + GetPanelKeyPos dd ? ;Func # 21 + GetPanelAlphaNumInfo dd ? ;Func # 22 + GetPanelAlphaNum dd ? ;Func # 23 + SetPanelAlphaNum dd ? ;Func # 24 + SetPanelOffSwitchMode dd ? ;Func # 25 + GetPanelOffSwitchMode dd ? ;Func # 26 + GetIntSybsysType dd ? ;Func # 27 + SetGlobalIntMask dd ? ;Func # 28 + GetGlobalIntMask dd ? ;Func # 29 + SetLocalIntMask dd ? ;Func # 30 + GetLocalIntMask dd ? ;Func # 31 + SetAdvIntMode dd ? ;Func # 32 + SetIRQVectorAssign dd ? ;Func # 33 + GetIRQVectorAssign dd ? ;Func # 34 + GetNumPowerSupplies dd ? ;Func # 35 + GetPowerSupplyInfo dd ? ;Func # 36 + DeInitEBI dd ? ;Func # 37 + SetLSIVector dd ? ;Func # 38 + GetLSIVector dd ? ;Func # 39 + SetSPIVector dd ? ;Func # 40 + GetSPIVector dd ? ;Func # 41 + SetIPIVector dd ? ;Func # 42 + GetIPIVector dd ? ;Func # 43 + SetIPIID dd ? ;Func # 44 + GetIPIID dd ? ;Func # 45 + GenIPI dd ? ;Func # 46 + GenerateLSI dd ? ;Func # 47 + GetNMISource dd ? ;Func # 48 + GetSPISource dd ? ;Func # 49 + GetLocalIRQStatus dd ? ;Func # 50 + MaskableIntEOI dd ? ;Func # 51 + NonMaskableIntEOI dd ? ;Func # 52 + CancelInterrupt dd ? ;Func # 53 + GetSysTimer dd ? ;Func # 54 + GetSysTimerFreq dd ? ;Func # 55 + GetNumMemBlocks dd ? ;Func # 56 + GetNumMemBlocks16 dd ? ;Func # 57 + GetMemInfoTable dd ? ;Func # 58 + GetMemInfoTable16 dd ? ;Func # 59 + GetMemoryErrorInfo dd ? ;Func # 60 + GetRevision dd ? ;Func # 61 + GetMMIOTableLen dd ? ;Func # 62 + GetMMIOTable dd ? ;Func # 63 + InitEBI dd ? ;Func # 64 + GetThermalState dd ? ;Func # 65 + ShutdownPowerSupply dd ? ;Func # 66 + SimulatePowerFail dd ? ;Func # 67 + SetPanelSwitchVisibility dd ? ;Func # 68 + GetPanelSwitchVisibility dd ? ;Func # 69 + GetGlobalIRQStatus dd ? ;Func # 70 + FastSetLocalIntMask dd ? ;Func # 71 + GetProcIntHandle dd ? ;Func # 72 + RegSetLocalIntMask dd ? ;Func # 73 + GetLocalIntMaskInfo dd ? ;Func # 74 + AST_Invalid_Func dd 22 DUP (?) + OEM0 dd ? ;Func #97 + OEM_Invalid_Func dd 31 DUP (?) +ebi_2_func_tbl ends + +; +;***************************** +; Equates. +cr equ 0ah +lf equ 0dh +MaskAllIrqs equ 0700FFFBh ; EBI2's mask for all irqs + ; (but irq2 for chaining) +NOT_ASSIGNED equ 0FFh ;used in IrqlToProcessor table, + ;(irql not assigned to any proc yet) +; +;##qp: Temp fix the stall scale to a fix number for now. +; +DefaultStallScaleFactor equ 9 ; temp default value for Stall scale +WarmResetVector equ 0467h +CpuLedSamplingRate equ 10 ; 15ms * X + +TIME_INCREMENT EQU 100144 + +;***************************** +; +; +; The following equates used for debugging HAL (ifdef'ed by DBG). The +; hex number will be displayed to the front panel as 'H xx' +; e.g. "DisplPanel HalEnableSystemInterruptEnter" will display as 'H 10' +; where HalEnableSystemInterruptEnter is equated to 010h. +; +HalEnableSystemInterruptEnter equ 010h +HalEnableSystemInterruptExit equ 011h +HalEnableSystemInterruptError equ 012h +HalDisableSystemInterruptEnter equ 015h +HalDisableSystemInterruptExit equ 016h +HalDisableSystemInterruptError equ 017h +HalEndSystemInterruptEnter equ 018h +HalEndSystemInterruptExit equ 019h +HalLowerIrqlEnter equ 020h +HalLowerIrqlExit equ 021h +HalRaiseIrqlEnter equ 022h +HalRaiseIrqlExit equ 023h +HalBeginSystemInterruptEnter equ 024h +HalBeginSystemInterruptExit equ 025h +HalStartProfileInterruptEnter equ 026h +HalStartProfileInterruptExit equ 027h +HalStopProfileInterruptEnter equ 028h +HalStopProfileInterruptExit equ 029h +HalClockInterruptEnter equ 030h +HalStartNextProcEnter equ 040h +HalStartNextProcExit equ 041h +HalStartNextProcProblem equ 0c0h +HalSpuriousInterrupt equ 0c1h +HalDisableInterruptProblem equ 0c2h +HalRaiseIrqlProblem equ 0c3h +HalSpuriousInterrupt2 equ 0c4h +HalSpuriousInterrupt3 equ 0c5h +HalSpuriousInterrupt4 equ 0c6h +; +;*** MACRO *** +; +;DisplPanel displays 'DisplCode' in hex to the front panel display + +DisplPanel macro DisplCode + if DBG + stdCall _DisplPanel,<DisplCode> + endif ;DBG + endm +; +;CALL_EBI2 setups the MMIOTable argument, calls the specified EBI function +;'EBI2Function', and then cleans up the stack according to the number of +;arguments 'NumArg' +; +CALL_EBI2 macro EBI2Function,NumArg + lea eax,_EBI2_MMIOTable + push eax + lea edx, _EBI2_CallTab + call [edx]+EBI2Function + add esp,NumArg * 4 ;clean stack + endm +; +CALL_FastEBI2 macro EBI2Function,NumArg + lea edx, _EBI2_CallTab + call [edx]+EBI2Function + add esp,NumArg * 4 ;clean stack + endm +; +;end diff --git a/private/ntos/nthals/halast/i386/astmpint.c b/private/ntos/nthals/halast/i386/astmpint.c new file mode 100644 index 000000000..42cbe4bd6 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astmpint.c @@ -0,0 +1,163 @@ +/*++ + +Copyright (c) 1991 Microsoft Corporation + +Module Name: + + astmpint.c + +Abstract: + + This module implements the HAL HalGetInterruptVector routine + for an x86 system + +Author: + + John Vert (jvert) 17-Jul-1991 + +Environment: + + Kernel mode + +Revision History: + + Bob Beard 7-Aug-92 For AST Manhattan system +--*/ +#include "halp.h" + +extern CCHAR HalpBusIntToIRQL[]; + +ULONG HalpDefaultInterruptAffinity; + +BOOLEAN +HalpTranslateSystemBusAddress( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN PHYSICAL_ADDRESS BusAddress, + IN OUT PULONG AddressSpace, + OUT PPHYSICAL_ADDRESS TranslatedAddress + ); + +ULONG +HalpGetSystemInterruptVector( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN ULONG BusInterruptLevel, + IN ULONG BusInterruptVector, + OUT PKIRQL Irql, + OUT PKAFFINITY Affinity + ); + + +#ifdef ALLOC_PRAGMA +#pragma alloc_text(PAGE,HalpGetSystemInterruptVector) +#endif + + +BOOLEAN +HalpTranslateSystemBusAddress( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN PHYSICAL_ADDRESS BusAddress, + IN OUT PULONG AddressSpace, + OUT PPHYSICAL_ADDRESS TranslatedAddress + ) + +/*++ + +Routine Description: + + This function translates a bus-relative address space and address into + a system physical address. + +Arguments: + + BusAddress - Supplies the bus-relative address + + AddressSpace - Supplies the address space number. + Returns the host address space number. + + AddressSpace == 0 => memory space + AddressSpace == 1 => I/O space + + TranslatedAddress - Supplies a pointer to return the translated address + +Return Value: + + A return value of TRUE indicates that a system physical address + corresponding to the supplied bus relative address and bus address + number has been returned in TranslatedAddress. + + A return value of FALSE occurs if the translation for the address was + not possible + +--*/ + +{ + UNREFERENCED_PARAMETER( BusHandler ); + + if (BusAddress.HighPart != 0 || *AddressSpace > 1) { + return (FALSE); + } + + TranslatedAddress->LowPart = BusAddress.LowPart; + TranslatedAddress->HighPart = 0; + + return(TRUE); +} + + + +ULONG +HalpGetSystemInterruptVector( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN ULONG BusInterruptLevel, + IN ULONG BusInterruptVector, + OUT PKIRQL Irql, + OUT PKAFFINITY Affinity + ) + +/*++ + +Routine Description: + +Arguments: + + BusInterruptLevel - Supplies the bus specific interrupt level. + + BusInterruptVector - Supplies the bus specific interrupt vector. + + Irql - Returns the system request priority. + + Affinity - Returns the system wide irq affinity. + +Return Value: + + Returns the system interrupt vector corresponding to the specified device. + +--*/ +{ + ULONG SystemVector; + + UNREFERENCED_PARAMETER( BusHandler ); + UNREFERENCED_PARAMETER( BusInterruptVector ); + + SystemVector = BusInterruptLevel + PRIMARY_VECTOR_BASE; + if (SystemVector < PRIMARY_VECTOR_BASE || + SystemVector > PRIMARY_VECTOR_BASE + HIGHEST_LEVEL_FOR_8259 || + HalpIDTUsage[SystemVector].Flags & IDTOwned ) { + + // + // This is an illegal BusInterruptVector and cannot be connected. + // + + return(0); + } + + *Irql = (KIRQL) HalpBusIntToIRQL[BusInterruptLevel]; + *Affinity = HalpDefaultInterruptAffinity; + ASSERT(HalpDefaultInterruptAffinity); + return SystemVector; +} + diff --git a/private/ntos/nthals/halast/i386/astnls.h b/private/ntos/nthals/halast/i386/astnls.h new file mode 100644 index 000000000..d63073815 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astnls.h @@ -0,0 +1,29 @@ +/*++ + +Copyright (c) 1993 Microsoft Corporation + +Module Name: + + astnls.h + +Abstract: + + Strings which are used in the HAL + + English + +--*/ + + +#define MSG_NMI_EBI2_ERR "EBI2 Problem: Cannot get NMI Source\n" +#define MSG_NMI_SYS_IO_ERR "NMI: System I/O error\n" +#define MSG_NMI_SW_GEN_NMI "NMI: Software generated NMI\n" +#define MSG_NMI_MEMORY_ERR "NMI: Memory error\n" +#define MSG_NMI_PROCESSOR_ERR "NMI: Processor error\n" +#define MSG_NMI_POWER_FAILURE "NMI: Power Failure\n" +#define MSG_NMI_BUS_ERR "NMI: Bus Address/Data error\n" +#define MSG_NMI_TIMEOUT_ERR "NMI: System Timeout error\n" +#define MSG_NMI_SHUTDOWN "NMI: Shutdown Button\n" +#define MSG_NMI_ATTENTION "NMI: Attention Button\n" +#define MSG_NMI_NO_NMI_FOUND "NMI: No NMI found\n" +#define MSG_NMI_UNKOWN "NMI: Unkown NMI error\n" diff --git a/private/ntos/nthals/halast/i386/astnmi.c b/private/ntos/nthals/halast/i386/astnmi.c new file mode 100644 index 000000000..c8e5af31b --- /dev/null +++ b/private/ntos/nthals/halast/i386/astnmi.c @@ -0,0 +1,168 @@ +/*++ + +Copyright (c) 1991 Microsoft Corporation + +Module Name: + + astnmi.c + +Abstract: + + -Provides standard x86 NMI handler + -This code is AST specific. + +Author: + + kenr + +Revision History: + + Quang Phan (v-quangp) 17-Dec-92: Check for other NMI sources and + print out the proper messages. + +--*/ +#include "halp.h" +#include "bugcodes.h" +#include "astebiii.h" +#include "astdisp.h" +#include "astnls.h" + +extern VOID* EBI2_MMIOTable[]; +extern EBI_II EBI2_CallTab; + + +#define SYSTEM_CONTROL_PORT_A 0x92 +#define SYSTEM_CONTROL_PORT_B 0x61 +#define EISA_EXTENDED_NMI_STATUS 0x461 + +UCHAR EisaNMIMsg[] = MSG_NMI_EISA_IOCHKERR; + + +VOID +HalHandleNMI( + IN OUT PVOID NmiInfo + ) +/*++ + +Routine Description: + + Called DURING an NMI. The system will BugCheck when an NMI occurs. + This function can return the proper bugcheck code, bugcheck itself, + or return success which will cause the system to iret from the nmi. + + This function is called during an NMI - no system services are available. + In addition, you don't want to touch any spinlock which is normally + used since we may have been interrupted while owning it, etc, etc... + +Warnings: + + Do NOT: + Make any system calls + Attempt to acquire any spinlock used by any code outside the NMI handler + Change the interrupt state. Do not execute any IRET inside this code + + Passing data to non-NMI code must be done using manual interlocked + functions. (xchg instructions). + +Arguments: + + NmiInfo - Pointer to NMI information structure (TBD) + - NULL means no NMI information structure was passed + +Return Value: + + BugCheck code + +--*/ +{ + UCHAR StatusByte; + UCHAR EisaPort; + UCHAR c; + ULONG port, i; + ULONG EBI2NMISource; + PUCHAR p; + + HalDisplayString (MSG_HARDWARE_ERROR1); + HalDisplayString (MSG_HARDWARE_ERROR2); + + StatusByte = READ_PORT_UCHAR((PUCHAR) SYSTEM_CONTROL_PORT_B); + + if (StatusByte & 0x80) { + HalDisplayString (MSG_NMI_PARITY); + } + + if (StatusByte & 0x40) { + HalDisplayString (MSG_NMI_CHANNEL_CHECK); + } + + if (HalpBusType == MACHINE_TYPE_EISA) { + // + // This is an Eisa machine, check for extnded nmi information... + // + + StatusByte = READ_PORT_UCHAR((PUCHAR) EISA_EXTENDED_NMI_STATUS); + + if (StatusByte & 0x80) { + HalDisplayString (MSG_NMI_FAIL_SAFE); + } + + if (StatusByte & 0x40) { + HalDisplayString (MSG_NMI_BUS_TIMEOUT); + } + + if (StatusByte & 0x20) { + HalDisplayString (MSG_NMI_SOFTWARE_NMI); + } + + // + // Look for any Eisa expansion board. See if it asserted NMI. + // + + for (EisaPort = 1; EisaPort <= 0xf; EisaPort++) { + port = (EisaPort << 12) + 0xC80; + WRITE_PORT_UCHAR ((PUCHAR) port, 0xff); + StatusByte = READ_PORT_UCHAR ((PUCHAR) port); + + if ((StatusByte & 0x80) == 0) { + // + // Found valid Eisa board, Check to see if it's + // if IOCHKERR is asserted. + // + + StatusByte = READ_PORT_UCHAR ((PUCHAR) port+4); + if (StatusByte & 0x2) { + c = (EisaPort > 9 ? 'A'-10 : '0') + EisaPort; + for (i=0; EisaNMIMsg[i]; i++) { + if (EisaNMIMsg[i] == '%') { + EisaNMIMsg[i] = c; + break; + } + } + HalDisplayString (EisaNMIMsg); + } + } + } + } + + if ( (EBI2_CallTab.GetNMISource)( EBI2_MMIOTable, &EBI2NMISource ) ) + { HalDisplayString (MSG_NMI_EBI2_ERR); } + + switch (EBI2NMISource) { + case NMI_SYS_IO_ERROR: p = MSG_NMI_SYS_IO_ERR; break; + case NMI_SW_GEN_NMI: p = MSG_NMI_SW_GEN_NMI; break; + case NMI_MEMORY_ERROR: p = MSG_NMI_MEMORY_ERR; break; + case NMI_PROC_ERROR: p = MSG_NMI_PROCESSOR_ERR; break; + case NMI_POWERFAIL: p = MSG_NMI_POWER_FAILURE; break; + case NMI_BUS_PARITY: p = MSG_NMI_BUS_ERR; break; + case NMI_BUS_TIMEOUT: p = MSG_NMI_TIMEOUT_ERR; break; + case NMI_FP_SHUTDOWN: p = MSG_NMI_SHUTDOWN; break; + case NMI_FP_ATTENTION: p = MSG_NMI_ATTENTION; break; + case NMI_NONE_FOUND: p = MSG_NMI_NO_NMI_FOUND; break; + default: p = MSG_NMI_UNKOWN; break; + } + + HalDisplayString (p); + + HalDisplayString (MSG_HALT); + KeEnterKernelDebugger(); +} diff --git a/private/ntos/nthals/halast/i386/astproc.c b/private/ntos/nthals/halast/i386/astproc.c new file mode 100644 index 000000000..2cf10da6e --- /dev/null +++ b/private/ntos/nthals/halast/i386/astproc.c @@ -0,0 +1,366 @@ +/*++ + +Copyright (c) 1991 Microsoft Corporation +Copyright (c) 1992 AST Research Inc. + +Module Name: + + spsproc.c + +Abstract: + + AST EBI2 Start Next Processor c code. + + This module implements the initialization of the system dependent + functions that define the Hardware Architecture Layer (HAL) for an + AST Manhattan EBI2 system. + +Author: + + Ken Reneris (kenr) 22-Jan-1991 + +Environment: + + Kernel mode only. + +Revision History: + + Bob Beard (v-bobb) 3-Aug-1992 + +--*/ + +#include "halp.h" +#include "astdisp.h" + +UCHAR HalName[] = "AST Manhattan MP HAL"; + +VOID +HalpMapCR3 ( + IN ULONG VirtAddress, + IN PVOID PhysicalAddress, + IN ULONG Length + ); + +ULONG +HalpBuildTiledCR3 ( + IN PKPROCESSOR_STATE ProcessorState + ); + +VOID +HalpFreeTiledCR3 ( + VOID + ); + + +#define MAX_PT 8 +#define LOW_MEMORY 0x000100000 +extern __cdecl StartPx_PMStub(); + +PUCHAR MpLowStub; // pointer to low memory bootup stub +PVOID MpLowStubPhysicalAddress; // pointer to low memory bootup stub +PUCHAR MppIDT; // pointer to physical memory 0:0 +PVOID MpFreeCR3[MAX_PT]; // remember pool memory to free + +extern ULONG HalpIpiClock; // bitmask of processors to ipi + + + +BOOLEAN +HalpInitMP ( + IN ULONG Phase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock + ) +/*++ + +Routine Description: + Allows MP initialization from HalInitSystem. + +Arguments: + Same as HalInitSystem + +Return Value: + none. + +--*/ +{ + PKPCR pPCR; + + pPCR = KeGetPcr(); + + if (Phase == 0) { + MppIDT = HalpMapPhysicalMemory (0, 1); + + + // + // Allocate some low memory for processor bootup stub + // + + MpLowStubPhysicalAddress = (PVOID)HalpAllocPhysicalMemory (LoaderBlock, + LOW_MEMORY, 1, FALSE); + + if (!MpLowStubPhysicalAddress) + return TRUE; + + MpLowStub = (PCHAR) HalpMapPhysicalMemory (MpLowStubPhysicalAddress, 1); + return TRUE; + + } +} + +VOID +HalReportResourceUsage ( + VOID + ) +/*++ + +Routine Description: + The registery is now enabled - time to report resources which are + used by the HAL. + +Arguments: + +Return Value: + +--*/ +{ + ANSI_STRING AHalName; + UNICODE_STRING UHalName; + + HalInitSystemPhase2(); + + RtlInitAnsiString (&AHalName, HalName); + RtlAnsiStringToUnicodeString (&UHalName, &AHalName, TRUE); + + HalpReportResourceUsage ( + &UHalName, // descriptive name + Eisa // Manhattan's are Eisa machines + ); + + RtlFreeUnicodeString (&UHalName); +} + + + +BOOLEAN +HalAllProcessorsStarted ( + VOID + ) +{ + return TRUE; +} + + + +VOID +HalpResetAllProcessors ( + VOID + ) +{ + // Just return, that will invoke the standard PC reboot code +} + +ULONG +HalpBuildTiledCR3 ( + IN PKPROCESSOR_STATE ProcessorState + ) +/*++ + +Routine Description: + When the x86 processor is reset it starts in real-mode. In order to + move the processor from real-mode to protected mode with flat addressing + the segment which loads CR0 needs to have it's linear address mapped + to machine the phyiscal location of the segment for said instruction so + the processor can continue to execute the following instruction. + + This function is called to built such a tiled page directory. In + addition, other flat addresses are tiled to match the current running + flat address for the new state. Once the processor is in flat mode, + we move to a NT tiled page which can then load up the remaining processors + state. + +Arguments: + ProcessorState - The state the new processor should start in. + +Return Value: + Physical address of Tiled page directory + + +--*/ +{ +#define GetPdeAddress(va) ((PHARDWARE_PTE)((((((ULONG)(va)) >> 22) & 0x3ff) << 2) + (PUCHAR)MpFreeCR3[0])) +#define GetPteAddress(va) ((PHARDWARE_PTE)((((((ULONG)(va)) >> 12) & 0x3ff) << 2) + (PUCHAR)pPageTable)) + +// bugbug kenr 27mar92 - fix physical memory usage! + + MpFreeCR3[0] = ExAllocatePool (NonPagedPool, PAGE_SIZE); + RtlZeroMemory (MpFreeCR3[0], PAGE_SIZE); + + // + // Map page for real mode stub (one page) + // + HalpMapCR3 ((ULONG) MpLowStubPhysicalAddress, + MpLowStubPhysicalAddress, + PAGE_SIZE); + + // + // Map page for protect mode stub (one page) + // + HalpMapCR3 ((ULONG) &StartPx_PMStub, NULL, 0x1000); + + + // + // Map page(s) for processors GDT + // + HalpMapCR3 (ProcessorState->SpecialRegisters.Gdtr.Base, NULL, + ProcessorState->SpecialRegisters.Gdtr.Limit); + + + // + // Map page(s) for processors IDT + // + HalpMapCR3 (ProcessorState->SpecialRegisters.Idtr.Base, NULL, + ProcessorState->SpecialRegisters.Idtr.Limit); + + return MmGetPhysicalAddress (MpFreeCR3[0]).LowPart; +} + + +VOID +HalpMapCR3 ( + IN ULONG VirtAddress, + IN PVOID PhysicalAddress, + IN ULONG Length + ) +/*++ + +Routine Description: + Called to build a page table entry for the passed page directory. + Used to build a tiled page directory with real-mode & flat mode. + +Arguments: + VirtAddress - Current virtual address + PhysicalAddress - Optional. Physical address to be mapped to, if passed + as a NULL then the physical address of the passed + virtual address is assumed. + Length - number of bytes to map + +Return Value: + none. + +--*/ +{ + ULONG i; + PHARDWARE_PTE PTE; + PVOID pPageTable; + PHYSICAL_ADDRESS pPhysicalPage; + + + while (Length) { + PTE = GetPdeAddress (VirtAddress); + if (!PTE->PageFrameNumber) { + pPageTable = ExAllocatePool (NonPagedPool, PAGE_SIZE); + RtlZeroMemory (pPageTable, PAGE_SIZE); + + for (i=0; i<MAX_PT; i++) { + if (!MpFreeCR3[i]) { + MpFreeCR3[i] = pPageTable; + break; + } + } + ASSERT (i<MAX_PT); + + pPhysicalPage = MmGetPhysicalAddress (pPageTable); + PTE->PageFrameNumber = (pPhysicalPage.LowPart >> PAGE_SHIFT); + PTE->Valid = 1; + PTE->Write = 1; + } + + pPhysicalPage.LowPart = PTE->PageFrameNumber << PAGE_SHIFT; + pPhysicalPage.HighPart = 0; + pPageTable = MmMapIoSpace (pPhysicalPage, PAGE_SIZE, TRUE); + + PTE = GetPteAddress (VirtAddress); + + if (!PhysicalAddress) { + PhysicalAddress = (PVOID)MmGetPhysicalAddress ((PVOID)VirtAddress).LowPart; + } + + PTE->PageFrameNumber = ((ULONG) PhysicalAddress >> PAGE_SHIFT); + PTE->Valid = 1; + PTE->Write = 1; + + MmUnmapIoSpace (pPageTable, PAGE_SIZE); + + PhysicalAddress = 0; + VirtAddress += PAGE_SIZE; + if (Length > PAGE_SIZE) { + Length -= PAGE_SIZE; + } else { + Length = 0; + } + } +} + + + +VOID +HalpFreeTiledCR3 ( + VOID + ) +/*++ + +Routine Description: + Free's any memory allocated when the tiled page directory was built. + +Arguments: + none + +Return Value: + none +--*/ +{ + ULONG i; + + for (i=0; MpFreeCR3[i]; i++) { + ExFreePool (MpFreeCR3[i]); + MpFreeCR3[i] = 0; + } +} + +VOID +HalpInitOtherBuses ( + VOID + ) +{ + // no other buses +} + + +NTSTATUS +HalpGetMcaLog ( + OUT PMCA_EXCEPTION Exception, + OUT PULONG ReturnedLength + ) +{ + return STATUS_NOT_SUPPORTED; +} + +NTSTATUS +HalpMcaRegisterDriver( + IN PMCA_DRIVER_INFO DriverInfo + ) +{ + return STATUS_NOT_SUPPORTED; +} + + +ULONG +FASTCALL +HalSystemVectorDispatchEntry ( + IN ULONG Vector, + OUT PKINTERRUPT_ROUTINE **FlatDispatch, + OUT PKINTERRUPT_ROUTINE *NoConnection + ) +{ + return FALSE; +} diff --git a/private/ntos/nthals/halast/i386/astproca.asm b/private/ntos/nthals/halast/i386/astproca.asm new file mode 100644 index 000000000..401c0dd3b --- /dev/null +++ b/private/ntos/nthals/halast/i386/astproca.asm @@ -0,0 +1,371 @@ + title "MP primitives for AST Manhattan EBI2" +;++ +; +;Copyright (c) 1991 Microsoft Corporation +;Copyright (c) 1992 AST Research Inc. +; +;Module Name: +; +; spsproca.asm +; +;Abstract: +; +; AST Manhattan Start Next Processor assemble code +; +; This module along with astproc.c implement the code to start +; off additional processors on the AST Manhattan. +; +;Author: +; +; Ken Reneris (kenr) 12-Jan-1992 +; +;Revision History: +; +; Bob Beard (v-bobb) 4-Aug-1992 +; +;-- + + + +.386p + .xlist +include hal386.inc +include callconv.inc +include i386\kimacro.inc +include mac386.inc +include i386\astebi2.inc +include i386\astmp.inc + .list + + EXTRNP _HalpBuildTiledCR3,1 + EXTRNP _HalpFreeTiledCR3,0 + EXTRNP _DisplPanel,1 + + extrn _MppIDT:DWORD + extrn _MpLowStub:DWORD + extrn _MpLowStubPhysicalAddress:DWORD + extrn _MpCount:DWORD + extrn _EBI2_CallTab:DWORD + extrn _EBI2_MMIOTable:DWORD + + +; +; Internal defines and structures +; + +PxParamBlock struc + SPx_flag dd ? + SPx_TiledCR3 dd ? + SPx_P0EBP dd ? + SPx_ProcNum dd ? + SPx_PB db processorstatelength dup (?) +PxParamBlock ends + + +_TEXT SEGMENT PARA PUBLIC 'CODE' ; Start 32 bit code + ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING + +;++ +; +; BOOLEAN +; HalStartNextProcessor ( +; IN PLOADER_BLOCK pLoaderBlock, +; IN PKPROCESSOR_STATE pProcessorState +; ) +; +; Routine Description: +; +; This routine is called by the kernel durning kernel initialization +; to obtain more processors. It is called until no more processors +; are available. +; +; If another processor exists this function is to initialize it to +; the passed in processorstate structure, and return TRUE. +; +; If another processor does not exists, then a FALSE is returned. +; +; Also note that the loader block has been setup for the next processor. +; The new processor logical thread number can be obtained from it, if +; required. +; +; Arguments: +; pLoaderBlock, - Loader block which has been intialized for the +; next processor. +; +; pProcessorState - The processor state which is to be loaded into +; the next processor. +; +; +; Return Value: +; +; TRUE - ProcessorNumber was dispatched. +; FALSE - A processor was not dispatched. no other processors exists. +; +;-- + +pLoaderBlock equ dword ptr [ebp+8] ; zero based +pProcessorState equ dword ptr [ebp+12] + +; +; Local variables +; + +PxFrame equ [ebp - size PxParamBlock] + + +cPublicProc _HalStartNextProcessor ,2 + + push ebp ; save ebp + mov ebp, esp ; + + sub esp, size PxParamBlock ; Make room for local vars + + + push esi + push edi + push ebx + + xor eax, eax + mov PxFrame.SPx_flag, eax + + cmp _MpCount, eax + je snp_exit ; exit FALSE + + mov esi, OFFSET FLAT:StartPx_RMStub + mov ecx, StartPx_RMStub_Len + mov edi, _MpLowStub ; Copy RMStub to low memory + add edi, size PxParamBlock + rep movsb + + lea edi, PxFrame.SPx_PB + mov esi, pProcessorState + mov ecx, processorstatelength ; Copy processorstate + rep movsb ; to PxFrame + + stdCall _HalpBuildTiledCR3,<pProcessorState> + + mov PxFrame.SPx_TiledCR3, eax + mov PxFrame.SPx_P0EBP, ebp + + mov eax, pLoaderBlock ; lookup processor # we are + mov eax, [eax].LpbPrcb ; starting + movzx eax, byte ptr [eax].PbNumber + mov PxFrame.SPx_ProcNum, eax + + mov ecx, size PxParamBlock ; copy param block + lea esi, PxFrame ; to low memory stub + mov edi, _MpLowStub + mov eax, edi + rep movsb + + add eax, size PxParamBlock + mov ebx, OFFSET FLAT:StartPx_RMStub + sub eax, ebx ; (eax) = adjusted pointer + mov bx, word ptr [PxFrame.SPx_PB.PsContextFrame.CsSegCs] + mov [eax.SPrxFlatCS], bx ; patch realmode stub with + mov [eax.SPrxPMStub], offset _StartPx_PMStub ; valid long jump + + mov ebx, _MppIDT + add ebx, WarmResetVector + + cli + push dword ptr [ebx] ; Save current vector + push ebx + + mov eax, _MpLowStubPhysicalAddress + shl eax, 12 ; seg:0 + add eax, size PxParamBlock + mov dword ptr [ebx], eax ; start Px here + + + push PxFrame.SPx_ProcNum + CALL_EBI2 StartProc,2 + +ifdef DBG + or eax,eax + je Start_Ok + push 0ffh + DisplPanel HalStartNextProcProblem + add esp,4 + int 3 +Start_Ok: +endif + +loop_till_started: + cmp PxFrame.SPx_flag, 0 + jz loop_till_started + + pop ebx + pop dword ptr [ebx] ; restore vector + + sti + + stdCall _HalpFreeTiledCR3 ; free memory used for tiled + ; CR3 + + dec _MpCount ; one less + mov eax, 1 ; return TRUE + +snp_exit: + pop ebx + pop edi + pop esi + mov esp, ebp + pop ebp + stdRET _HalStartNextProcessor +stdENDP _HalStartNextProcessor + + +_TEXT ends ; end 32 bit code + + +_TEXT16 SEGMENT DWORD PUBLIC USE16 'CODE' ; start 16 bit code + + +;++ +; +; VOID +; StartPx_RMStub +; +; Routine Description: +; +; When a new processor is started, it starts in real-mode and is +; sent to a copy of this function which has been copied into low memory. +; (below 1m and accessable from real-mode). +; +; Once CR0 has been set, this function jmp's to a StartPx_PMStub +; +; Arguments: +; none +; +; Return Value: +; does not return, jumps to StartPx_PMStub +; +;-- + public StartPx_RMStub + +StartPx_RMStub proc + cli + + db 066h ; load the GDT + lgdt fword ptr cs:[SPx_PB.PsSpecialRegisters.SrGdtr] + + db 066h ; load the IDT + lidt fword ptr cs:[SPx_PB.PsSpecialRegisters.SrIdtr] + + mov eax, cs:[SPx_TiledCR3] + mov cr3, eax + + mov ebp, dword ptr cs:[SPx_P0EBP] + mov ecx, dword ptr cs:[SPx_PB.PsContextFrame.CsSegDs] + mov ebx, dword ptr cs:[SPx_PB.PsSpecialRegisters.SrCr3] + mov eax, dword ptr cs:[SPx_PB.PsSpecialRegisters.SrCr0] + + mov cr0, eax ; into prot mode + + db 066h + db 0eah ; reload cs:eip +SPrxPMStub dd 0 +SPrxFlatCS dw 0 + +StartPx_RMStub_Len equ $ - StartPx_RMStub +StartPx_RMStub endp + + +_TEXT16 ends ; End 16 bit code + +_TEXT SEGMENT ; Start 32 bit code + + +;++ +; +; VOID +; StartPx_PMStub +; +; Routine Description: +; +; This function completes the processor's state loading, and signals +; the requesting processor that the state has been loaded. +; +; Arguments: +; ebx - requested CR3 for this processors_state +; cx - requested ds for this processors_state +; ebp - EBP of P0 +; +; Return Value: +; does not return - completes the loading of the processors_state +; +;-- + align 16 ; to make sure we don't cross a page boundry + ; before reloading CR3 + + public _StartPx_PMStub +_StartPx_PMStub proc + + ; process is now in the load image copy of this function. + ; (ie, it's not the low memory copy) + + mov cr3, ebx ; get real CR3 + mov ds, cx ; set real ds + + lea esi, PxFrame.SPx_PB.PsSpecialRegisters + + lldt word ptr ds:[esi].SrLdtr ; load ldtr + ltr word ptr ds:[esi].SrTr ; load tss + + lea edi, PxFrame.SPx_PB.PsContextFrame + mov es, word ptr ds:[edi].CsSegEs ; Set other selectors + mov fs, word ptr ds:[edi].CsSegFs + mov gs, word ptr ds:[edi].CsSegGs + mov ss, word ptr ds:[edi].CsSegSs + + add esi, SrKernelDr0 + .errnz (SrKernelDr1 - SrKernelDr0 - 1 * 4) + .errnz (SrKernelDr2 - SrKernelDr0 - 2 * 4) + .errnz (SrKernelDr3 - SrKernelDr0 - 3 * 4) + .errnz (SrKernelDr6 - SrKernelDr0 - 4 * 4) + .errnz (SrKernelDr7 - SrKernelDr0 - 5 * 4) + lodsd + mov dr0, eax ; load dr0-dr7 + lodsd + mov dr1, eax + lodsd + mov dr2, eax + lodsd + mov dr3, eax + lodsd + mov dr6, eax + lodsd + mov dr7, eax + + mov esp, dword ptr ds:[edi].CsEsp + mov esi, dword ptr ds:[edi].CsEsi + mov ecx, dword ptr ds:[edi].CsEcx + + push dword ptr ds:[edi].CsEflags + popfd ; load eflags + + push dword ptr ds:[edi].CsEip ; make a copy of remaining + push dword ptr ds:[edi].CsEax ; registers which need + push dword ptr ds:[edi].CsEbx ; loaded + push dword ptr ds:[edi].CsEdx + push dword ptr ds:[edi].CsEdi + push dword ptr ds:[edi].CsEbp + + + ; eax, ebx, edx are still free +spxpm01: + inc [PxFrame.SPx_flag] ; Signal p0 that we are + ; done with it's data + ; Set remaining registers + pop ebp + pop edi + pop edx + pop ebx + pop eax + ret ; Set eip + +_StartPx_PMStub endp + +_TEXT ends ; end 32 bit code + end diff --git a/private/ntos/nthals/halast/i386/astspi.asm b/private/ntos/nthals/halast/i386/astspi.asm new file mode 100644 index 000000000..427b6544f --- /dev/null +++ b/private/ntos/nthals/halast/i386/astspi.asm @@ -0,0 +1,152 @@ + title "Special Interrupt" +;++ +; +;Copyright (c) 1992 AST Research Inc. +; +;Module Name: +; +; astspi.asm +; +;Abstract: +; +; AST Manhattan SPI code. +; Provides the HAL support for Special Interrupts for the +; MP Manhattan implementation. +; +;Author: +; +; Bob Beard (v-bobb) 14-Aug-1992 +; +;Revision History: +; +;-- +.386p + .xlist + +; +; Normal includes +; + +include hal386.inc +include callconv.inc +include i386\astebi2.inc +include i386\astmp.inc +include i386\kimacro.inc + + EXTRNP _DisplPanel,1 + EXTRNP Kei386EoiHelper,0,IMPORT + EXTRNP _HalBeginSystemInterrupt,3 + EXTRNP _HalEndSystemInterrupt,2 + extrn _EBI2_CallTab:DWORD + extrn _EBI2_MMIOTable:DWORD + extrn _HalpIRQLtoVector:BYTE + + + +_DATA SEGMENT DWORD PUBLIC 'DATA' + +_EBI2_SpiSource dd 0 ; Global variable indicating SPI source +_EBI2_SetIrq13Packet dd 3 dup (0) ;Parameter packet for OEMfunc SetIrq13Latch + +_DATA ends + + page ,132 + subttl "Post InterProcessor Interrupt" +_TEXT SEGMENT DWORD PUBLIC 'CODE' + ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING + + +;++ +; +; HalpSpiInterrupt +; +;Routine Description: +; +; Determine type of SPI interrupt that occurred. +; EOI the interrupt. +; Defer all works to the device driver by latching IRQ13 +; +;Arguments: +; +; None +; Interrupt is disabled +; +;Return Value: +; +; None. +; +;-- + ENTER_DR_ASSIST Hsi_a, Hsi_t +cPublicProc _HalpSPInterrupt,0 + +; +; Save Machine state in trap frame +; + + ENTER_INTERRUPT Hsi_a, Hsi_t + +; +; (esp) - base of trap frame +; + + +; +; get the SPI interrupt source and store in _EBI2_SpiSource +; + push offset _EBI2_SpiSource + CALL_EBI2 GetSPISource, 2 + +if DBG + int 3 + or eax,eax + jz Spi_10 + int 3 +Spi_10: +endif ;DBG + +; +;Defer any processing to the device driver by set IRQ13 latche +; + mov eax,_EBI2_SpiSource ;save SPI sources + mov fs:PcHal.PcrEBI2SPIsource,eax ; + + mov eax,offset _EBI2_SetIrq13Packet + mov [eax].OEM0_subfunc,SET_IRQ13_LATCH + mov [eax].OEM0_parm1dd,IRQ13_LATCH_ON ;latch mode + mov [eax].OEM0_parm2dd,0 ;set to processor 0 + push eax + CALL_EBI2 OEM0, 2 + +if DBG + or eax,eax + jz Spi_20 + int 3 +Spi_20: +endif ;DBG + + + movzx eax, _HalpIRQLtoVector[POWER_LEVEL] + push eax + sub esp,4 ; space for OldIrql + stdCall _HalBeginSystemInterrupt,<POWER_LEVEL,eax,esp> + or al,al ; check for spurious interrupt + jz Spi_100 + + +; +; (esp) = OldIrql +; (esp+4) = Vector +; (esp+8) = base of trap frame + + INTERRUPT_EXIT + + +Spi_100: + add esp,8 ; spurious + EXIT_ALL ,,NoPreviousMode ; no EOI or lowering irql + +stdENDP _HalpSPInterrupt + +_TEXT ENDS + + END diff --git a/private/ntos/nthals/halast/i386/aststall.asm b/private/ntos/nthals/halast/i386/aststall.asm new file mode 100644 index 000000000..184407832 --- /dev/null +++ b/private/ntos/nthals/halast/i386/aststall.asm @@ -0,0 +1,251 @@ + title "Stall Execution Support" +;++ +; Copyright (c) 1989 Microsoft Corporation +; +; Module Name: +; aststall.asm +; +; Abstract: +; This module implements the code necessary to initialize the per +; microsecond count used by the KeStallExecution. +; This implementation is very specific to the AST Manhattan system. +; +; Author: +; Shie-Lin Tzong (shielint) 12-Jan-1990 +; +; Environment: +; Kernel mode only. +; +; Revision History: +; +; bryanwi 20-Sep-90 +; Add KiSetProfileInterval, KiStartProfileInterrupt, +; KiStopProfileInterrupt procedures. +; KiProfileInterrupt ISR. +; KiProfileList, KiProfileLock are delcared here. +; +; shielint 10-Dec-90 +; Add performance counter support. +; Move system clock to irq8, ie we now use RTC to generate system +; clock. Performance count and Profile use timer 1 counter 0. +; The interval of the irq0 interrupt can be changed by +; KiSetProfileInterval. Performance counter does not care about the +; interval of the interrupt as long as it knows the rollover count. +; Note: Currently I implemented 1 performance counter for the whole +; i386 NT. +; +; John Vert (jvert) 11-Jul-1991 +; Moved from ke\i386 to hal\i386. Removed non-HAL stuff +; +; shie-lin tzong (shielint) 13-March-92 +; Move System clock back to irq0 and use RTC (irq8) to generate +; profile interrupt. Performance counter and system clock use time1 +; counter 0 of 8254. +; +; Landy Wang (corollary!landy) 04-Dec-92 +; Created this module by moving routines from ixclock.asm to here. +; +; Quang Phan (v-quangp) 07-Jan-93 +; Modified for AST MP system. +;-- +.386p + .xlist +include hal386.inc +include callconv.inc ; calling convention macros +include i386\ix8259.inc +include i386\kimacro.inc +include mac386.inc +include i386\ixcmos.inc +include i386\astmp.inc +include i386\astebi2.inc + .list + EXTRNP _DbgBreakPoint,0,IMPORT + extrn _EBI2_CallTab:DWORD + extrn _EBI2_MMIOTable:DWORD +; +; Constants +; +BaseStallCount EQU 40h ; Init. count +UpperLimitCount EQU 400h ; Upper limit count for debbuging +SysTimerUpperLimit EQU 0FFFFFFC0h ; SysTimer nears wrap arround + +_DATA SEGMENT DWORD PUBLIC 'DATA' + +EBI2_SysTimerCount dd 0 ;loc for EBI2GetSysTimer data + +_DATA ends + +_TEXT SEGMENT DWORD PUBLIC 'CODE' + ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING + + page ,132 + subttl "Initialize Stall Execution Counter" +;++ +; +; VOID +; HalpInitializeStallExecution ( +; IN CCHAR ProcessorNumber +; ) +; +; Routine Description: +; This routine initialize the per Microsecond counter for +; KeStallExecutionProcessor. +; +; This function does not use the interval clock interrupt. Instead, +; it use the global system timer of 1 microsecond available in the +; AST Manhattan system. +; +; Arguments: +; ProcessorNumber - Processor Number +; +; Return Value: +; None. +; +; Note: +;-- + +cPublicProc _HalpInitializeStallExecution ,1 + + pushfd ; save caller's eflag + cli ; make sure interrupts are disabled + push ebx ; save ebx for internal use + mov ecx,BaseStallCount +; +;Sync on transition of the system timer. +; +Kise10: + lea eax, EBI2_SysTimerCount ;ptr to data + push eax + CALL_EBI2 GetSysTimer,2 +if DBG + or eax,eax + je @f + int 3 ;trap for debugging +@@: +endif + mov ebx, EBI2_SysTimerCount ;save last SysTimer + lea eax, EBI2_SysTimerCount ;ptr to data + push eax + CALL_EBI2 GetSysTimer,2 +if DBG + or eax,eax + je @f + int 3 ;trap for debugging +@@: +endif + cmp ebx, EBI2_SysTimerCount ;cmp with last SysTimer + jae Kise10 ;if wrap or the same. + + mov ebx, EBI2_SysTimerCount ;last SysTimer + cmp ebx, SysTimerUpperLimit ; if near wrap around + ja kise10 ; then try again. + + add ebx, 32 ;sample in 32 us. + mov eax, ecx ;init loop count +ALIGN 4 +@@: + sub eax, 1 ; dec loop count + jnz short @b + +; +;Check if system timer roll over. +; + lea eax, EBI2_SysTimerCount ;ptr to data + push eax + CALL_EBI2 GetSysTimer,2 +if DBG + or eax,eax + je short @f + int 3 ;trap for debugging +@@: +endif + cmp EBI2_SysTimerCount, ebx ;cmp with last SysTimer + jb Kise30 ;go increment BaseStallCount + + shr ecx,5 ;/32=count for 1us + mov PCR[PcStallScaleFactor], ecx + +if DBG + cmp ecx, 0 + jnz short @f + stdCall _DbgBreakPoint +@@: + cmp ecx, UpperLimitCount + jb short @f + stdCall _DbgBreakPoint +@@: +endif + pop ebx + popfd ; restore caller's eflags + + stdRET _HalpInitializeStallExecution + + +;------- +; +;SysTimer does not reach the reference yet, increment stall count then retry. +; +Kise30: + inc ecx + jmp Kise10 ;try again + +stdENDP _HalpInitializeStallExecution + + + page ,132 + subttl "Stall Execution" +;++ +; +; VOID +; KeStallExecutionProcessor ( +; IN ULONG MicroSeconds +; ) +; +; Routine Description: +; This function stalls execution for the specified number of microseconds. +; KeStallExecutionProcessor +; +; Arguments: +; MicroSeconds - Supplies the number of microseconds that execution is to be +; stalled. +; +; Return Value: +; None. +; +;-- + +MicroSeconds equ [esp + 4] + +cPublicProc _KeStallExecutionProcessor ,1 + + mov ecx, MicroSeconds ; (ecx) = Microseconds + jecxz short kese10 ; return if no loop needed + + mov eax, PCR[PcStallScaleFactor] ; get per microsecond + ; loop count for the processor + mul ecx ; (eax) = desired loop count + +if DBG +; +; Make sure we the loopcount is less than 4G and is not equal to zero +; + cmp edx, 0 + jz short @f + int 3 + +@@: cmp eax,0 + jnz short @f + int 3 +@@: +endif + +ALIGN 4 +@@: sub eax, 1 ; (eax) = (eax) - 1 + jnz short @b +kese10: + stdRET _KeStallExecutionProcessor + +stdENDP _KeStallExecutionProcessor + +_TEXT ends + end diff --git a/private/ntos/nthals/halast/i386/astsyint.asm b/private/ntos/nthals/halast/i386/astsyint.asm new file mode 100644 index 000000000..e30022ed2 --- /dev/null +++ b/private/ntos/nthals/halast/i386/astsyint.asm @@ -0,0 +1,592 @@ +;++ +; +;Copyright (c) 1991 Microsoft Corporation +;Copyright (c) 1992 AST Research Inc. +; +;Module Name: +; +; astsyint.asm +; +;Abstract: +; +; This module implements the HAL routines to enable/disable system +; interrupts, for the AST MP (Manhattan) implementation +; +;Author: +; +; John Vert (jvert) 22-Jul-1991 +; Quang Phan (v-quangp) 24-Jul-1992 +; +;Environment: +; +; Kernel Mode +; +;Revision History: +; +; Quang Phan (v-quangp) 15-Dec-1992: +; Used different display codes for different spurious interrupt status. +; +;-- + + +.386p + .xlist +include hal386.inc +include callconv.inc +include i386\ix8259.inc +include i386\kimacro.inc +include mac386.inc +include i386\astebi2.inc +include i386\astmp.inc + .list + + EXTRNP _KeBugCheck,1,IMPORT + extrn KiEBI2IntMaskTable:DWORD + extrn _HalpIRQLtoEBIBitMask:DWORD + extrn _EBI2_CallTab:DWORD + extrn _EBI2_MMIOTable:DWORD + extrn _HalpInitializedProcessors:DWORD + extrn _HalpIRQLtoVector:BYTE + EXTRNP _DisplPanel,1 + EXTRNP _KeRaiseIrql,2 + EXTRNP KfRaiseIrql,1,,FASTCALL + +_DATA SEGMENT DWORD PUBLIC 'DATA' + +; +;spinlock for EBI2 access +; + align dword + public _EBI2_Lock +_EBI2_Lock dd 0 ;for Enable/DisableSystemInterrupt +EBI2_GlobalIntMask dd 0 ;loc for EBI2GetGlobalIntMask data + +;HalpInterruptToProc table is used by HAL to figure out which interrupt +;(irql) will be assigned to which processor. The current implementation +;assigns interrupts to processors on a round-robin basis. +; + public IrqlAssignToProcTable ;InterruptToProcessor assignment table +IrqlAssigntoProcTable label dword + dd 32 dup(0FFh) ;irql -> ProcID +CurrentAssignProcessor dd 0 ; Current proc. assigned to irql +; +; HalDismissSystemInterrupt does an indirect jump through this table so it +; can quickly execute specific code for different interrupts. +; + public HalpSpecialDismissTable +HalpSpecialDismissTable label dword + dd offset FLAT:HalpDismissNormal ; irql 0 + dd offset FLAT:HalpDismissNormal ; irql 1 + dd offset FLAT:HalpDismissNormal ; irql 2 + dd offset FLAT:HalpDismissNormal ; irql 3 + dd offset FLAT:HalpDismissNormal ; irql 4 + dd offset FLAT:HalpDismissNormal ; irql 5 + dd offset FLAT:HalpDismissNormal ; irql 6 + dd offset FLAT:HalpDismissNormal ; irql 7 + dd offset FLAT:HalpDismissNormal ; irql 8 + dd offset FLAT:HalpDismissNormal ; irql 9 + dd offset FLAT:HalpDismissNormal ; irql 10 + dd offset FLAT:HalpDismissNormal ; irql 11 + dd offset FLAT:HalpDismissIrq07 ; irql 12 (irq7) + dd offset FLAT:HalpDismissNormal ; irql 13 + dd offset FLAT:HalpDismissNormal ; irql 14 + dd offset FLAT:HalpDismissNormal ; irql 15 + dd offset FLAT:HalpDismissNormal ; irql 16 + dd offset FLAT:HalpDismissIrq0f ; irql 17 (irq15) + dd offset FLAT:HalpDismissNormal ; irql 18 + dd offset FLAT:HalpDismissNormal ; irql 19 + dd offset FLAT:HalpDismissNormal ; irql 20 + dd offset FLAT:HalpDismissNormal ; irql 21 + dd offset FLAT:HalpDismissNormal ; irql 22 + dd offset FLAT:HalpDismissNormal ; irql 23 + dd offset FLAT:HalpDismissNormal ; irql 24 + dd offset FLAT:HalpDismissNormal ; irql 25 + dd offset FLAT:HalpDismissNormal ; irql 26 + dd offset FLAT:HalpDismissNormal ; irql 27 + dd offset FLAT:HalpDismissNormal ; irql 28 + dd offset FLAT:HalpDismissNormal ; irql 29 + dd offset FLAT:HalpDismissNormal ; irql 30 + dd offset FLAT:HalpDismissNormal ; irql 31 +; +;Translation table from system IRQL to EBI's IntNum used in MaskableIntEOI. +; + Public HalpIRQLtoEBIIntNumber + align 4 +HalpIRQLtoEBIIntNumber Label Dword + dd 0 ;IRQL 0 (Unused Mask) + dd 0 ;IRQL 1 + dd IRQ_25 ;IRQL 2 (EBI IRQ-25) + dd 0 ;IRQL 3 + dd 0 ;IRQL 4 + dd 0 ;IRQL 5 + dd 0 ;IRQL 6 + dd 0 ;IRQL 7 + dd 0 ;IRQL 8 + dd 0 ;IRQL 9 + dd 0 ;IRQL 10 + dd 0 ;IRQL 11 + dd IRQ_7 ;IRQL 12 + dd IRQ_6 ;IRQL 13 + dd IRQ_5 ;IRQL 14 + dd IRQ_4 ;IRQL 15 + dd IRQ_3 ;IRQL 16 + dd IRQ_15 ;IRQL 17 + dd IRQ_14 ;IRQL 18 + dd IRQ_13 ;IRQL 19 + dd IRQ_12 ;IRQL 20 + dd IRQ_11 ;IRQL 21 + dd IRQ_10 ;IRQL 22 + dd IRQ_9 ;IRQL 23 + dd IRQ_8 ;IRQL 24 + dd IRQ_2 ;IRQL 25 + dd IRQ_1 ;IRQL 26 + dd IRQ_8 ;IRQL 27 + dd IRQ_0 ;IRQL 28 + dd IRQ_26 ;IRQL 29 (IPI) + dd IRQ_24 ;IRQL 30 (SPI) + dd 0 ;IRQL 31 +; + +_DATA ENDS + +_TEXT SEGMENT DWORD PUBLIC 'CODE' + ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING + + +;++ +;BOOLEAN +;HalBeginSystemInterrupt( +; IN KIRQL Irql +; IN CCHAR Vector, +; OUT PKIRQL OldIrql +; ) +; +; +; +;Routine Description: +; +; This routine is used to dismiss the specified vector number. It is called +; before any interrupt service routine code is executed. +; +;Arguments: +; +; Irql - Supplies the IRQL to raise to +; +; Vector - Supplies the vector of the interrupt to be dismissed +; +; OldIrql- Location to return OldIrql +; +; +;Return Value: +; +; FALSE - Interrupt is spurious and should be ignored +; +; TRUE - Interrupt successfully dismissed and Irql raised. +; +;-- +align dword +HbsiIrql equ byte ptr [esp+4] +HbsiVector equ byte ptr [esp+8] +HbsiOldIrql equ dword ptr [esp+12] + +cPublicProc _HalBeginSystemInterrupt,3 + + movzx eax,HbsiIrql ; (eax) = System Irql + movzx ecx,byte ptr fs:PcIrql ; (ecx) = Current Irql + +if DBG + cmp eax, 31 ; Irql in table? + ja hbsi00 ; no go handle + + cmp cl, al + ja hbsi00 ; Dismiss as spurious +endif ;DBG + + jmp HalpSpecialDismissTable[eax*4] ; ck for spurious int's + +hbsi00: +; +; Interrupt is out of range. There's no EOI here since it wouldn't +; have been out of range if it occured on either interrupt controller +; which is known about. +; + DisplPanel HalSpuriousInterrupt + int 3 + mov eax,0 ; return FALSE + stdRET _HalBeginSystemInterrupt + +; +; +;------------------- +;Normal handler +;------------------- +; +HalpDismissNormal2: + movzx eax,HbsiIrql ; (eax) = System Irql + movzx ecx,byte ptr fs:PcIrql ; (ecx) = Current Irql +HalpDismissNormal: + mov dl, _HalpIRQLtoVector[eax] ; Does irql match interrupt + cmp dl, HbsiVector ; vector? + jne short hbsi10 ; no, (then it's higher) go raise + + mov edx, HbsiOldIrql ; (edx) = OldIrql address + mov fs:PcIrql, al ; Set new irql + mov byte ptr[edx], cl ; return OldIrql +; mov dword ptr[edx], ecx + + mov eax, 1 ; set return value to true + sti + stdRET _HalBeginSystemInterrupt + +hbsi10: + mov edx, HbsiOldIrql ; (edx) = OldIrql address + stdCall _KeRaiseIrql <eax, edx> + mov eax, 1 ; set return value to true + sti + stdRET _HalBeginSystemInterrupt + + + +; +;------------------- +;Handler for irq0Fh +;------------------- +; +HalpDismissIrq0f: +; +; Check to see if this is a spurious interrupt by reading the global IRQ status +; + + sub esp, 8 ;alloc room in stack for 2 dword + mov eax,esp + add eax,4 + push eax ;ptr to GlobalIRR + mov eax,esp + add eax,4 + push eax ;ptr to GlobalISR + CALL_EBI2 GetGlobalIRQStatus,3 + +if DBG + or eax,eax + je BeginSysInt4_OK + int 3 ;trap for debugging +BeginSysInt4_OK: +endif + + bt dword ptr [esp],IRQ_15 ;chk In-Service for irq15 + pop eax ;dummy pop to adj stack + pop eax ;.. + jc short HalpDismissNormal2 ; =1: NOT a spurious int +; +;Else, is a spurious interrupt. In this case, we have to send EOI to +;the ADI to dismiss the interrupt. +; + DisplPanel HalSpuriousInterrupt2 + push IRQ_15 ;EOI Irq_15 + CALL_EBI2 MaskableIntEOI,2 + +if DBG + or eax,eax + je BeginSysInt3_OK + int 3 ;trap for debugging +BeginSysInt3_OK: +endif +; + mov eax, 0 ; return FALSE + stdRET _HalBeginSystemInterrupt +; +;------------------- +;Handler for irq07 +;------------------- +; +HalpDismissIrq07: +; +; Check to see if this is a spurious interrupt by reading the global IRQ status +; + + sub esp, 8 ;alloc room in stack for 2 dword + mov eax,esp + add eax, 4 + push eax ;ptr to GlobalIRR + mov eax,esp + add eax, 4 + push eax ;ptr to GlobalISR + CALL_EBI2 GetGlobalIRQStatus,3 + +if DBG + or eax,eax + je BeginSysInt2_OK + int 3 ;trap for debugging +BeginSysInt2_OK: +endif + + bt dword ptr [esp],IRQ_7 ; chk In-Service for irq7 + pop eax ;dummy pop to adj stack + pop eax ;.. + jc HalpDismissNormal2 ; =1: NOT a spurious int +; +;Else, is a spurious interrupt. In this case, we have to send EOI to +;the ADI to dismiss the interrupt. +; + DisplPanel HalSpuriousInterrupt3 + push IRQ_7 ;EOI Irq_7 + CALL_EBI2 MaskableIntEOI,2 + +if DBG + or eax,eax + je BeginSysInt1_OK + int 3 ;trap for debugging +BeginSysInt1_OK: +endif +; + mov eax, 0 ; return FALSE + stdRET _HalBeginSystemInterrupt + + +stdENDP _HalBeginSystemInterrupt + +;++ +;VOID +;HalDisableSystemInterrupt( +; IN CCHAR Vector, +; IN KIRQL Irql +; ) +; +; +; +;Routine Description: +; +; Disables a system interrupt. +; +;Arguments: +; +; Vector - Supplies the vector of the interrupt to be disabled +; +; Irql - Supplies the interrupt level of the interrupt to be disabled +; +;Return Value: +; +; None. +; +;-- +cPublicProc _HalDisableSystemInterrupt,2 + + movzx ecx, byte ptr [esp+4] ;get vector + sub ecx, PRIMARY_VECTOR_BASE + jc DisSysIntError ;jump if not H/W interrupt + cmp ecx, CLOCK2_LEVEL + jnc DisSysIntError + movzx ecx, byte ptr [esp+8] ;get IRQL (ecx) + mov ecx, HalpIRQLtoEBIIntNumber[ecx*4] ;get ebi2 int# (edx) + cli + bts fs:PcIDR, ecx ;disable int locally + jc DisSysIntExit ;jump if already disabled + + lea eax, _EBI2_Lock +DisSysIntAquire: + ACQUIRE_SPINLOCK eax, DisSysIntSpin +; +;Mark the appropirate entry in the Irql assign table to NOT_ASSIGNED. +; + movzx eax, byte ptr [esp+8] ;get IRQL + mov IrqlAssignToProcTable[eax*4],NOT_ASSIGNED +; +;Get the global interrupt mask +; + lea eax, EBI2_GlobalIntMask + push eax + CALL_EBI2 GetGlobalIntMask,2 + +if DBG + or eax,eax + je DisableSysInt4_OK + int 3 ;trap for debugging +DisableSysInt4_OK: +endif + +; +;Disable interrupt globally at PIC +; + bts EBI2_GlobalIntMask,ecx ;disable int at global mask + push EBI2_GlobalIntMask + CALL_EBI2 SetGlobalIntMask,2 + +if DBG + or eax,eax + je DisableSysInt1_OK + int 3 ;trap for debugging +DisableSysInt1_OK: +endif +; +;Disable interrupt locally +; + mov cl, fs:PcIrql + fstCall KfRaiseIrql + + lea eax, _EBI2_Lock +DisSysIntRelease: + RELEASE_SPINLOCK eax + +DisSysIntExit: +;## DisplPanel HalDisableSystemInterruptExit + sti + stdRET _HalDisableSystemInterrupt + +DisSysIntError: + DisplPanel HalDisableSystemInterruptError +if DBG + int 3 +endif + sti + xor eax,eax + ret + +DisSysIntSpin: + SPIN_ON_SPINLOCK eax, DisSysIntAquire + +stdENDP _HalDisableSystemInterrupt + +;++ +; +;BOOLEAN +;HalEnableSystemInterrupt( +; IN ULONG Vector, +; IN KIRQL Irql, +; IN KINTERRUPT_MODE InterruptMode +; ) +; +; +;Routine Description: +; +; Enables a system interrupt +; +;Arguments: +; +; Vector - Supplies the vector of the interrupt to be enabled +; +; Irql - Supplies the interrupt level of the interrupt to be enabled. +; +;Return Value: +; +; None. +; +;-- +cPublicProc _HalEnableSystemInterrupt,3 +;## DisplPanel HalEnableSystemInterruptEnter +; int 3 + movzx eax, byte ptr [esp+4] ;get vector + sub eax, PRIMARY_VECTOR_BASE + jc EnbSysIntError ;jump if not H/W interrupt +; cmp eax, CLOCK2_LEVEL +; jnc EnbSysIntError +; +;Determine if this irq is to be assigned to this processor. +;Irqs are to be assigned to the available processors on a round-robin +;basis +; + movzx ecx, byte ptr [esp+8] ;get IRQL + cmp ecx,PROFILE_LEVEL + jae HESI_010 ;skip for PROFILE irql and above. +; +;To have the fpanel switch work properly, irq13 must be assigned to P0. +;This is because EBI2 clears switch status when asthal eoi SPI interrupt. +;The current implementation is that switch status will be read and saved +;by SPI handler. +; + cmp eax,13 ;irq13 vector? + jne HSEI_006 + mov eax,fs:PcHal.PcrEBI2ProcessorID + or eax,eax + jne EnbSysIntExit + mov IrqlAssignToProcTable[ecx*4],eax ;update IrqlAssingnTable + jmp short HESI_010 ;go assign irq13 to P0 + +HSEI_006: + cmp IrqlAssignToProcTable[ecx*4],NOT_ASSIGNED + jne EnbSysIntExit ;skip if irql already assigned + mov eax,CurrentAssignProcessor + cmp eax,fs:PcHal.PcrEBI2ProcessorID + jne EnbSysIntExit + mov IrqlAssignToProcTable[ecx*4],eax ;update IrqlAssingnTable + cmp _HalpInitializedProcessors,1 + je HESI_010 ;skip if only one processor + inc eax ;1-base count + cmp eax,_HalpInitializedProcessors + jae HESI_008 + inc CurrentAssignProcessor + jmp HESI_010 +HESI_008: + mov CurrentAssignProcessor,0 ;reset to 0 + +HESI_010: + mov eax, HalpIRQLtoEBIIntNumber[ecx*4] ;get ebi2 int # + cli + btr fs:PcIDR, eax ;enable int locally + jnc EnbSysIntExit ;jump if already enabled +; + lea eax, _EBI2_Lock +EnbSysIntAquire: + ACQUIRE_SPINLOCK eax, EnbSysIntSpin +; +;Enable interrupt locally +; + mov cl, fs:PcIrql + fstCall KfRaiseIrql + +; +;Get the global interrupt mask +; + lea eax, EBI2_GlobalIntMask + push eax + CALL_EBI2 GetGlobalIntMask,2 + +if DBG + or eax,eax + je EnableSysInt4_OK + int 3 ;trap for debugging +EnableSysInt4_OK: +endif + +; +;Enable interrupt globally at PIC +; + mov eax,EBI2_GlobalIntMask ;current Global mask + and eax,fs:PcIDR ;enable int according PcIDR + and eax,0FFFFh ;EBI allows only irqs + push eax + CALL_EBI2 SetGlobalIntMask,2 + +if DBG + or eax,eax + je EnableSysInt3_OK + int 3 ;trap for debugging +EnableSysInt3_OK: +endif + +EnbSysIntRelease: + lea eax, _EBI2_Lock + RELEASE_SPINLOCK eax + +EnbSysIntExit: +;## DisplPanel HalEnableSystemInterruptExit + sti + mov eax, 1 + stdRET _HalEnableSystemInterrupt + +EnbSysIntError: + DisplPanel HalEnableSystemInterruptError +if DBG + int 3 +endif + sti + xor eax,eax + stdRET _HalEnableSystemInterrupt + +EnbSysIntSpin: + SPIN_ON_SPINLOCK eax, EnbSysIntAquire + +stdENDP _HalEnableSystemInterrupt + + +_TEXT ENDS + END diff --git a/private/ntos/nthals/halast/i386/halp.h b/private/ntos/nthals/halast/i386/halp.h new file mode 100644 index 000000000..49a60e028 --- /dev/null +++ b/private/ntos/nthals/halast/i386/halp.h @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "halx86\i386\halp.h" diff --git a/private/ntos/nthals/halast/i386/ix8259.inc b/private/ntos/nthals/halast/i386/ix8259.inc new file mode 100644 index 000000000..b9e0a196a --- /dev/null +++ b/private/ntos/nthals/halast/i386/ix8259.inc @@ -0,0 +1,5 @@ +; +; Include code from halx86 +; This is a cpp style symbolic link + +include ..\halx86\i386\ix8259.inc diff --git a/private/ntos/nthals/halast/i386/ixbeep.asm b/private/ntos/nthals/halast/i386/ixbeep.asm new file mode 100644 index 000000000..f53bd3e58 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixbeep.asm @@ -0,0 +1,5 @@ +; +; Include code from halx86 +; This is a cpp style symbolic link + +include ..\halx86\i386\ixbeep.asm diff --git a/private/ntos/nthals/halast/i386/ixbusdat.c b/private/ntos/nthals/halast/i386/ixbusdat.c new file mode 100644 index 000000000..a42039752 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixbusdat.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixbusdat.c" diff --git a/private/ntos/nthals/halast/i386/ixcmos.asm b/private/ntos/nthals/halast/i386/ixcmos.asm new file mode 100644 index 000000000..7f4e7393e --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixcmos.asm @@ -0,0 +1,5 @@ +; +; Include code from halx86 +; This is a cpp style symbolic link + +include ..\halx86\i386\ixcmos.asm diff --git a/private/ntos/nthals/halast/i386/ixcmos.inc b/private/ntos/nthals/halast/i386/ixcmos.inc new file mode 100644 index 000000000..2fe289fb0 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixcmos.inc @@ -0,0 +1,5 @@ +; +; Include code from halx86 +; This is a cpp style symbolic link + +include ..\halx86\i386\ixcmos.inc diff --git a/private/ntos/nthals/halast/i386/ixdat.c b/private/ntos/nthals/halast/i386/ixdat.c new file mode 100644 index 000000000..f6b0e34de --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixdat.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixdat.c" diff --git a/private/ntos/nthals/halast/i386/ixenvirv.c b/private/ntos/nthals/halast/i386/ixenvirv.c new file mode 100644 index 000000000..e194820ba --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixenvirv.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixenvirv.c" diff --git a/private/ntos/nthals/halast/i386/ixfirm.c b/private/ntos/nthals/halast/i386/ixfirm.c new file mode 100644 index 000000000..f666e405c --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixfirm.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixfirm.c" diff --git a/private/ntos/nthals/halast/i386/ixhwsup.c b/private/ntos/nthals/halast/i386/ixhwsup.c new file mode 100644 index 000000000..ea91dc8d0 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixhwsup.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixhwsup.c" diff --git a/private/ntos/nthals/halast/i386/ixidle.asm b/private/ntos/nthals/halast/i386/ixidle.asm new file mode 100644 index 000000000..9bdd670f3 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixidle.asm @@ -0,0 +1,5 @@ +; +; Include code from halx86 +; This is a cpp style symbolic link + +include ..\halx86\i386\ixidle.asm diff --git a/private/ntos/nthals/halast/i386/ixinfo.c b/private/ntos/nthals/halast/i386/ixinfo.c new file mode 100644 index 000000000..7f211f7a9 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixinfo.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixinfo.c" diff --git a/private/ntos/nthals/halast/i386/ixisa.h b/private/ntos/nthals/halast/i386/ixisa.h new file mode 100644 index 000000000..f67b35f49 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixisa.h @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixisa.h" diff --git a/private/ntos/nthals/halast/i386/ixisabus.c b/private/ntos/nthals/halast/i386/ixisabus.c new file mode 100644 index 000000000..c1edfb067 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixisabus.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixisabus.c" diff --git a/private/ntos/nthals/halast/i386/ixisasup.c b/private/ntos/nthals/halast/i386/ixisasup.c new file mode 100644 index 000000000..58c426544 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixisasup.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixisasup.c" diff --git a/private/ntos/nthals/halast/i386/ixkdcom.c b/private/ntos/nthals/halast/i386/ixkdcom.c new file mode 100644 index 000000000..29bb8308e --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixkdcom.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixkdcom.c" diff --git a/private/ntos/nthals/halast/i386/ixkdcom.h b/private/ntos/nthals/halast/i386/ixkdcom.h new file mode 100644 index 000000000..22f1aac09 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixkdcom.h @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixkdcom.h" diff --git a/private/ntos/nthals/halast/i386/ixphwsup.c b/private/ntos/nthals/halast/i386/ixphwsup.c new file mode 100644 index 000000000..a1cdab598 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixphwsup.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixphwsup.c" diff --git a/private/ntos/nthals/halast/i386/ixreboot.c b/private/ntos/nthals/halast/i386/ixreboot.c new file mode 100644 index 000000000..15d7bd898 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixreboot.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixreboot.c" diff --git a/private/ntos/nthals/halast/i386/ixswint.asm b/private/ntos/nthals/halast/i386/ixswint.asm new file mode 100644 index 000000000..68b302dfe --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixswint.asm @@ -0,0 +1,5 @@ +; +; Include code from halx86 +; This is a cpp style symbolic link + +include ..\halx86\i386\ixswint.asm diff --git a/private/ntos/nthals/halast/i386/ixthunk.c b/private/ntos/nthals/halast/i386/ixthunk.c new file mode 100644 index 000000000..6f15aad73 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixthunk.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixthunk.c" diff --git a/private/ntos/nthals/halast/i386/ixusage.c b/private/ntos/nthals/halast/i386/ixusage.c new file mode 100644 index 000000000..519ec31f3 --- /dev/null +++ b/private/ntos/nthals/halast/i386/ixusage.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\ixusage.c" diff --git a/private/ntos/nthals/halast/i386/spprofil.asm b/private/ntos/nthals/halast/i386/spprofil.asm new file mode 100644 index 000000000..8bc9f5e3e --- /dev/null +++ b/private/ntos/nthals/halast/i386/spprofil.asm @@ -0,0 +1,5 @@ +; +; Include code from halx86 +; This is a cpp style symbolic link + +include ..\halsp\i386\spprofil.asm diff --git a/private/ntos/nthals/halast/i386/spspin.asm b/private/ntos/nthals/halast/i386/spspin.asm new file mode 100644 index 000000000..0d70c442f --- /dev/null +++ b/private/ntos/nthals/halast/i386/spspin.asm @@ -0,0 +1,5 @@ +; +; Include code from halsp +; This is a cpp style symbolic link + +include ..\halsp\i386\spspin.asm diff --git a/private/ntos/nthals/halast/i386/xxbiosa.asm b/private/ntos/nthals/halast/i386/xxbiosa.asm new file mode 100644 index 000000000..bc0173a17 --- /dev/null +++ b/private/ntos/nthals/halast/i386/xxbiosa.asm @@ -0,0 +1,5 @@ +; +; Include code from halx86 +; This is a cpp style symbolic link + +include ..\halx86\i386\xxbiosa.asm diff --git a/private/ntos/nthals/halast/i386/xxbiosc.c b/private/ntos/nthals/halast/i386/xxbiosc.c new file mode 100644 index 000000000..60cf92748 --- /dev/null +++ b/private/ntos/nthals/halast/i386/xxbiosc.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\xxbiosc.c" diff --git a/private/ntos/nthals/halast/i386/xxdisp.c b/private/ntos/nthals/halast/i386/xxdisp.c new file mode 100644 index 000000000..d48977df0 --- /dev/null +++ b/private/ntos/nthals/halast/i386/xxdisp.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\xxdisp.c" diff --git a/private/ntos/nthals/halast/i386/xxflshbf.c b/private/ntos/nthals/halast/i386/xxflshbf.c new file mode 100644 index 000000000..b054121cf --- /dev/null +++ b/private/ntos/nthals/halast/i386/xxflshbf.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\xxflshbf.c" diff --git a/private/ntos/nthals/halast/i386/xxioacc.asm b/private/ntos/nthals/halast/i386/xxioacc.asm new file mode 100644 index 000000000..8445c3404 --- /dev/null +++ b/private/ntos/nthals/halast/i386/xxioacc.asm @@ -0,0 +1,5 @@ +; +; Include code from halx86 +; This is a cpp style symbolic link + +include ..\halx86\i386\xxioacc.asm diff --git a/private/ntos/nthals/halast/i386/xxkdsup.c b/private/ntos/nthals/halast/i386/xxkdsup.c new file mode 100644 index 000000000..6e569b5ac --- /dev/null +++ b/private/ntos/nthals/halast/i386/xxkdsup.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\xxkdsup.c" diff --git a/private/ntos/nthals/halast/i386/xxmemory.c b/private/ntos/nthals/halast/i386/xxmemory.c new file mode 100644 index 000000000..920714540 --- /dev/null +++ b/private/ntos/nthals/halast/i386/xxmemory.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\xxmemory.c" diff --git a/private/ntos/nthals/halast/i386/xxstubs.c b/private/ntos/nthals/halast/i386/xxstubs.c new file mode 100644 index 000000000..8421fb30a --- /dev/null +++ b/private/ntos/nthals/halast/i386/xxstubs.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\xxstubs.c" diff --git a/private/ntos/nthals/halast/i386/xxtime.c b/private/ntos/nthals/halast/i386/xxtime.c new file mode 100644 index 000000000..92abb2aeb --- /dev/null +++ b/private/ntos/nthals/halast/i386/xxtime.c @@ -0,0 +1,5 @@ +// +// Include code from halx86 +// This is a cpp style symbolic link + +#include "..\halx86\i386\xxtime.c" diff --git a/private/ntos/nthals/halast/makefile b/private/ntos/nthals/halast/makefile new file mode 100644 index 000000000..6ee4f43fa --- /dev/null +++ b/private/ntos/nthals/halast/makefile @@ -0,0 +1,6 @@ +# +# DO NOT EDIT THIS FILE!!! Edit .\sources. if you want to add a new source +# file to this component. This file merely indirects to the real make file +# that is shared by all the components of NT OS/2 +# +!INCLUDE $(NTMAKEENV)\makefile.def diff --git a/private/ntos/nthals/halast/makefile.inc b/private/ntos/nthals/halast/makefile.inc new file mode 100644 index 000000000..cb912aa51 --- /dev/null +++ b/private/ntos/nthals/halast/makefile.inc @@ -0,0 +1,2 @@ +obj\i386\hal.def: hal.src + $(TARGET_CPP) /EP -Di386 $(C_DEFINES) hal.src > obj\i386\hal.def diff --git a/private/ntos/nthals/halast/sources b/private/ntos/nthals/halast/sources new file mode 100644 index 000000000..ea2bfddce --- /dev/null +++ b/private/ntos/nthals/halast/sources @@ -0,0 +1,102 @@ + +!IF 0 + +Copyright (c) 1989 Microsoft Corporation + +Module Name: + + sources. + +Abstract: + + This file specifies the target component being built and the list of + sources files needed to build that component. Also specifies optional + compiler switches and libraries that are unique for the component being + built. + + +Author: + + Steve Wood (stevewo) 12-Apr-1990 + +NOTE: Commented description of this file is in \nt\bak\bin\sources.tpl + +!ENDIF + +MAJORCOMP=ntos +MINORCOMP=hal + +TARGETNAME=halast +TARGETPATH=\nt\public\sdk\lib + +!IF $(386) + +TARGETTYPE=HAL +NT_UP=0 + +!ELSE + +TARGETTYPE=DRIVER + +!ENDIF + +INCLUDES=..\..\inc;..\..\ke;..\..\io;.. + +SOURCES= + +i386_SOURCES=hal.rc \ + drivesup.c \ + bushnd.c \ + rangesup.c \ + i386\ixbeep.asm \ + i386\ixbusdat.c \ + i386\ixdat.c \ + i386\ixisabus.c \ + i386\ixcmos.asm \ + i386\ixenvirv.c \ + i386\ixfirm.c \ + i386\ixhwsup.c \ + i386\ixidle.asm \ + i386\ixinfo.c \ + i386\ixisasup.c \ + i386\ixkdcom.c \ + i386\ixphwsup.c \ + i386\ixreboot.c \ + i386\ixswint.asm \ + i386\ixthunk.c \ + i386\ixusage.c \ + i386\xxbiosa.asm \ + i386\xxbiosc.c \ + i386\xxdisp.c \ + i386\xxioacc.asm \ + i386\xxkdsup.c \ + i386\xxmemory.c \ + i386\xxstubs.c \ + i386\xxtime.c \ + i386\spspin.asm \ + i386\spprofil.asm \ + i386\astdetct.c \ + i386\astebi.c \ + i386\asthal.c \ + i386\astipirq.c \ + i386\astebini.c \ + i386\astipi.asm \ + i386\astclock.asm \ + i386\astirql.asm \ + i386\astsyint.asm \ + i386\astproc.c \ + i386\astmpint.c \ + i386\astspi.asm \ + i386\aststall.asm \ + i386\astproca.asm \ + i386\astnmi.c + +DLLDEF=obj\*\hal.def + +MSC_WARNING_LEVEL=/W3 /WX + +!IF $(386) + +NTTARGETFILES=$(TARGETPATH)\i386\halast.lib + +!ENDIF |