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| author | Adam <you@example.com> | 2020-05-17 05:51:50 +0200 |
|---|---|---|
| committer | Adam <you@example.com> | 2020-05-17 05:51:50 +0200 |
| commit | e611b132f9b8abe35b362e5870b74bce94a1e58e (patch) | |
| tree | a5781d2ec0e085eeca33cf350cf878f2efea6fe5 /private/ntos/nthals/halavant | |
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Diffstat (limited to 'private/ntos/nthals/halavant')
52 files changed, 3753 insertions, 0 deletions
diff --git a/private/ntos/nthals/halavant/alpha/addrsup.c b/private/ntos/nthals/halavant/alpha/addrsup.c new file mode 100644 index 000000000..5f3d69f09 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/addrsup.c @@ -0,0 +1,587 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + addrsup.c + +Abstract: + + This module contains the platform dependent code to create bus addreses + and QVAs for the Avanti system. + +Author: + + Joe Notarangelo 22-Oct-1993 + +Environment: + + Kernel mode + +Revision History: + + Eric Rehm (Digital) 03-Jan-1994 + Added PCIBus(0) and dense space support to all routines. + +--*/ + +#include "halp.h" +#include "eisa.h" +#include "avantdef.h" + +typedef PVOID QUASI_VIRTUAL_ADDRESS; + +QUASI_VIRTUAL_ADDRESS +HalCreateQva( + IN PHYSICAL_ADDRESS PA, + IN PVOID VA + ); + + +BOOLEAN +HalpTranslateSystemBusAddress( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN PHYSICAL_ADDRESS BusAddress, + IN OUT PULONG AddressSpace, + OUT PPHYSICAL_ADDRESS TranslatedAddress + ) + + +/*++ + +Routine Description: + + This function returns the system physical address for a specified I/O bus + address. The return value is suitable for use in a subsequent call to + MmMapIoSpace. + +Arguments: + + BusHandler - Registered BUSHANDLER for the target configuration space + Supplies the bus handler (bus no, interface type). + + RootHandler - Registered BUSHANDLER for the orginating + HalTranslateBusAddress request. + + BusAddress - Supplies the bus relative address. + + AddressSpace - Supplies the address space number for the device: 0 for + memory and 1 for I/O space. If the desired access mode is user mode, + then bit 1 must be TRUE. + + TranslatedAddress - Supplies a pointer to return the translated address + + +Notes: + + This is a variation of what began in the MIPS code. The intel code often + assumes that if an address is in I/O space, the bottom 32 bits of the + physical address can be used "like" a virtual address, and are returned + to the user. This doesn't work on MIPs machines where physical + addresses can be larger than 32 bits. + + Since we are using superpage addresses for I/O on Alpha, we can do + almost what is done on intel. If AddressSpace is equal to 0 or 1, then + we assume the user is doing kernel I/O and we call + HalCreateQva to build a Quasi Virtual Address and return + that to the caller. We then set AddressSpace to a 1, so that the caller + will not call MmMapIoSpace. The Caller will use the low 32 bits of the + physical address we return as the VA. (Which we built a QVA in). + If the caller wants to access EISA I/O or Memory through user mode, then + the caller must set bit 1 in AddressSpace to a 1 (AddressSpace=2 or 3, + depending on whether EISA I/O or Memory), then the caller is returned the + 34 bit Physical address. The caller will then call MmMapIoSpace, or + ZwMapViewOfSection which in turn calls HalCreateQva to build a QVA out + of a VA mapped through the page tables. + + **** Note **** + + The QVA in user mode can only be used via the user-mode access macros. + + + +Return Value: + + A return value of TRUE indicates that a system physical address + corresponding to the supplied bus relative address and bus address + number has been returned in TranslatedAddress. + + A return value of FALSE occurs if the translation for the address was + not possible + +--*/ + +{ + INTERFACE_TYPE InterfaceType = BusHandler->InterfaceType; + ULONG BusNumber = BusHandler->BusNumber; + + PVOID va = 0; // note, this is used for a placeholder + + // + // The only buses available on Avanti are an ISA bus and a PCI bus. + // We support any translations for EISA devices as well, though + // if they are true EISA devices they won't even be able to plug into + // the connectors! + // + + if (InterfaceType != Isa && + InterfaceType != Eisa && + InterfaceType != PCIBus) { + + // + // Not on this system return nothing. + // + + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + } + + // + // Determine the address based on whether the bus address is in I/O space + // or bus memory space. + // + + switch ( (ADDRESS_SPACE_TYPE)(*AddressSpace) ) { + + case BusMemory: { + + // + // The address is in PCI memory space, kernel mode. + // + + switch( InterfaceType ) { + + case Isa: { + + // + // Can't go above 16MB (24 Bits) for Isa Buses + // + if( BusAddress.LowPart >= __16MB ){ + + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + + } + + break; + + } // case Isa + + case PCIBus: { + + if ( BusAddress.LowPart > PCI_MAX_DENSE_MEMORY_ADDRESS ) { + + // + // Unsupported dense PCI bus address. + // +#if HALDBG + DbgPrint ("Unsupported PCI address %x:%x\n", + BusAddress.HighPart, + BusAddress.LowPart); +#endif + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + } + else if( BusAddress.LowPart >= PCI_MIN_DENSE_MEMORY_ADDRESS && + BusAddress.LowPart <= PCI_MAX_DENSE_MEMORY_ADDRESS ) { + +#if HALDBG + DbgPrint ("Translating PCI kernel dense address %x:%x\n", + BusAddress.HighPart, + BusAddress.LowPart); +#endif + // + // Bus Address is in dense PCI memory space + // + + // + // QVA, as such, is simply the PCI bus address + // + + TranslatedAddress->LowPart = BusAddress.LowPart; + + // + // clear high longword for QVA + // + + TranslatedAddress->HighPart = 0; + + // + // dont let the user call MmMapIoSpace + // + + *AddressSpace = 1; + + return (TRUE); + + + } + + // + // Bus Address is in sparse PCI memory space + // + + +#if HALDBG + DbgPrint ("Translating PCI kernel sparse address %x:%x\n", + BusAddress.HighPart, + BusAddress.LowPart); +#endif + + break; + } // case PCIBus + + case Eisa: { + break; + } // case Eisa + + } // switch( InterfaceType ) + + // + // Start with the base physical address and add the + // bus address by converting it to the physical address. + // + + TranslatedAddress->QuadPart = APECS_PCI_MEMORY_BASE_PHYSICAL; + TranslatedAddress->QuadPart += ((ULONGLONG)BusAddress.LowPart << IO_BIT_SHIFT); + + // + // Now call HalCreateQva. This will create a QVA + // that we'll return to the caller. Then we will implicitly set + // AddressSpace to a 1. The caller then will not call MmMapIoSpace + // and will use the address we return as a VA. + // + + TranslatedAddress->LowPart = + (ULONG) HalCreateQva( *TranslatedAddress, va); + + // + // clear high longword for QVA + // + + TranslatedAddress->HighPart = 0; + + // + // don't let the user call MmMapIoSpace + // + + *AddressSpace = 1; + + return(TRUE); + + } // case BusMemory + + + case BusIo: { + + // + // The address is in PCI I/O space, kernel mode. + // + + switch( InterfaceType ) { + + case Isa: { + // + // Can't go above 64KB (16 Bits) for Isa Buses + // + if( BusAddress.LowPart >= __64K ){ + + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + + } + break; + } // case Isa + + case PCIBus: { + + // + // PCI IO space is always below 16MB (24 Bits) BusAddress + // If the address cannot be mapped, just return FALSE. + // + // IMPORTANT: For now we have set HAXR2 to 0(see ebinitnt.c) + // + if( BusAddress.LowPart >= __16MB ){ + + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + + } + // + // if the BusAddress.LowPart is > 64K then we use the HAXR2 + // register. + // + break; + } // case PCIBus + + case Eisa: { + break; + } // case Eisa + + } // switch( InterfaceType ) + + + // + // Start with the base physical address and add the + // bus address by converting it to the physical address. + // + + TranslatedAddress->QuadPart = APECS_PCI_IO_BASE_PHYSICAL; + TranslatedAddress->QuadPart += ((ULONGLONG)BusAddress.LowPart << IO_BIT_SHIFT); + + // + // Now call HalCreateQva. This will create a QVA + // that we'll return to the caller. Then we will implicitly set + // AddressSpace to a 1. The caller then will not call MmMapIoSpace + // and will use the address we return as a VA. + + TranslatedAddress->LowPart = (ULONG) HalCreateQva( *TranslatedAddress, + va); + + TranslatedAddress->HighPart = 0; // clear high longword for QVA + + *AddressSpace = 1; // Make sure user doesn't call + // MmMapIoSpace. + + return(TRUE); + + } // case BusIo + + case UserBusMemory: { + + // + // The address is in PCI memory space, user mode. + // + + // + // Start with the base physical address and add the + // bus address by converting it to the physical address. + // + + TranslatedAddress->QuadPart = APECS_PCI_MEMORY_BASE_PHYSICAL; + TranslatedAddress->QuadPart += ((ULONGLONG)BusAddress.LowPart << IO_BIT_SHIFT); + + *AddressSpace = 0; // Let the user call MmMapIoSpace + + return(TRUE); + + } + + case UserBusIo: { + + // + // The address is in PCI I/O space, user mode. + // + + // + // Start with the base physical address and add the + // bus address by converting it to the physical address. + // + + TranslatedAddress->QuadPart = APECS_PCI_IO_BASE_PHYSICAL; + TranslatedAddress->QuadPart += ((ULONGLONG)BusAddress.LowPart << IO_BIT_SHIFT); + + *AddressSpace = 0; // Make sure user can call + // MmMapIoSpace. + + return(TRUE); + + } + + + case KernelPciDenseMemory: + case UserPciDenseMemory: + { + + // + // The address is in PCI memory space, user mode. + // Note that ISA and EISA buses can also request this space + // + + // + // Start with the base physical address and add the + // bus address by converting it to the physical address. + // + + TranslatedAddress->QuadPart = APECS_PCI_DENSE_BASE_PHYSICAL; + TranslatedAddress->QuadPart += BusAddress.LowPart; + + *AddressSpace = 0; // Let the user call MmMapIoSpace + + return(TRUE); + + } + + default: { + + // + // Unsupported address space. + + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + + } + + + } +} + +PVOID +HalCreateQva( + IN PHYSICAL_ADDRESS PA, + IN PVOID VA + ) + +/*++ + +Routine Description: + + This function is called two ways. First, from HalTranslateBusAddress, + if the caller is going to run in kernel mode and use superpages. + The second way is if the user is going to access in user mode. + MmMapIoSpace or ZwViewMapOfSection will call this. + + If the input parameter VA is zero, then we assume super page and build + a QUASI virtual address that is only usable by calling the hal I/O + access routines. + + if the input parameter VA is non-zero, we assume the user has either + called MmMapIoSpace or ZwMapViewOfSection and will use the user mode + access macros. + + If the PA is not a sparse I/O space address (PCI I/O, PCI Memory), + then return the VA as the QVA. + +Arguments: + + PA - the physical address generated by HalTranslateBusAddress + + VA - the virtual address returned by MmMapIoSpace + +Return Value: + + The returned value is a quasi virtual address in that it can be + added to and subtracted from, but it cannot be used to access the + bus directly. The top bits are set so that we can trap invalid + accesses in the memory management subsystem. All access should be + done through the Hal Access Routines in *ioacc.s if it was a superpage + kernel mode access. If it is usermode, then the user mode access + macros must be used. + +--*/ +{ + + PVOID qva; + + if( (PA.QuadPart >= APECS_COMANCHE_BASE_PHYSICAL) + && (PA.QuadPart < APECS_PCI_DENSE_BASE_PHYSICAL) + ) + { + + // + // The physical address is within one of the sparse I/O spaces. + // + + if (VA == 0) { + + qva = (PVOID)(PA.QuadPart >> IO_BIT_SHIFT); + + } else { + + qva = (PVOID)((ULONG)VA >> IO_BIT_SHIFT); + } + + qva = (PVOID)((ULONG)qva | QVA_ENABLE); + + return(qva); + } + + // + // It is not a sparse I/O space address, return the VA as the QVA + // + + return(VA); + +} + +PVOID +HalDereferenceQva( + PVOID Qva, + INTERFACE_TYPE InterfaceType, + ULONG BusNumber + ) +/*++ + +Routine Description: + + This function performs the inverse of the HalCreateQva for I/O addresses + that are memory-mapped (i.e. the quasi-virtual address was created from + a virtual address rather than a physical address). + +Arguments: + + Qva - Supplies the quasi-virtual address to be converted back to a + virtual address. + + InterfaceType - Supplies the interface type of the bus to which the + Qva pertains. + + BusNumber - Supplies the bus number of the bus to which the Qva pertains. + +Return Value: + + The Virtual Address from which the quasi-address was originally created + is returned. + +--*/ +{ + + + // + // For Avanti we have only bus types: + // + // Isa + // PCIBus + // + // We will allow Eisa as an alias for Isa. All other values not named + // above will be considered bogus. + // + + switch (InterfaceType ){ + + case Isa: + case Eisa: + case PCIBus: + + // + // Support dense space: check to see if it's really + // a sparse space QVA. + // + + if ( ((ULONG) Qva & QVA_SELECTORS) == QVA_ENABLE ) + { + return( (PVOID)( (ULONG)Qva << IO_BIT_SHIFT ) ); + } + else + { + return (Qva); + } + break; + + + default: + + return NULL; + + } + + +} diff --git a/private/ntos/nthals/halavant/alpha/adjust.c b/private/ntos/nthals/halavant/alpha/adjust.c new file mode 100644 index 000000000..47c267fb8 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/adjust.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\adjust.c" + diff --git a/private/ntos/nthals/halavant/alpha/allstart.c b/private/ntos/nthals/halavant/alpha/allstart.c new file mode 100644 index 000000000..42f70b7ca --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/allstart.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\allstart.c" + diff --git a/private/ntos/nthals/halavant/alpha/alphaio.s b/private/ntos/nthals/halavant/alpha/alphaio.s new file mode 100644 index 000000000..d2fe61a53 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/alphaio.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\alphaio.s" + diff --git a/private/ntos/nthals/halavant/alpha/apecs.c b/private/ntos/nthals/halavant/alpha/apecs.c new file mode 100644 index 000000000..06eb91348 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/apecs.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\apecs.c" + diff --git a/private/ntos/nthals/halavant/alpha/apecserr.c b/private/ntos/nthals/halavant/alpha/apecserr.c new file mode 100644 index 000000000..441154cc9 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/apecserr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\apecserr.c" + diff --git a/private/ntos/nthals/halavant/alpha/apecsio.s b/private/ntos/nthals/halavant/alpha/apecsio.s new file mode 100644 index 000000000..27bb7caa7 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/apecsio.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\apecsio.s" + diff --git a/private/ntos/nthals/halavant/alpha/avantdef.h b/private/ntos/nthals/halavant/alpha/avantdef.h new file mode 100644 index 000000000..43ce52fa0 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/avantdef.h @@ -0,0 +1,181 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + avantdef.h + +Abstract: + + This module specifies platform-specific definitions for the + Avanti modules. + +Author: + + Joe Notarangelo 25-Oct-1993 + +Revision History: + + +--*/ + +#ifndef _AVANTIDEF_ +#define _AVANTIDEF_ + +#include "alpharef.h" +#include "apecs.h" +#include "isaaddr.h" + +#define NUMBER_ISA_SLOTS 3 +#define NUMBER_PCI_SLOTS 2 +#define NUMBER_COMBO_SLOTS 1 + +// Highest Virtual local PCI Slot is 13 == IDSEL PCI_AD[24] + +#define PCI_MAX_LOCAL_DEVICE 13 + +// Highest PCI interrupt vector is in ISA Vector Space + +#define PCI_MAX_INTERRUPT_VECTOR (MAXIMUM_ISA_VECTOR - ISA_VECTORS) + +// +// Define the per-processor data structures allocated in the PCR +// for each EV4 processor. +// + +#if !defined (_LANGUAGE_ASSEMBLY) + +typedef struct _AVANTI_PCR{ + ULONGLONG HalpCycleCount; // 64-bit per-processor cycle count + EV4ProfileCount ProfileCount; // Profile counter state, do not move + EV4IrqStatus IrqStatusTable[MaximumIrq]; // Irq status table +} AVANTI_PCR, *PAVANTI_PCR; + +#define HAL_PCR ( (PAVANTI_PCR)(&(PCR->HalReserved)) ) + +#define PCI_SPARSE_IO_BASE_QVA ((ULONG)(HAL_MAKE_QVA(APECS_PCI_IO_BASE_PHYSICAL))) + +// +// PCI-E/ISA Bridge chip configuration space base is at physical address +// 0x1e0000000. The equivalent QVA is: +// ((0x1e0000000 + cache line offset) >> IO_BIT_SHIFT) | QVA_ENABLE +// +// N.B.: The PCI configuration space address is what we're really referring +// to, here; both symbols are useful. +// +#define PCI_REVISION (0x0100 >> IO_BIT_SHIFT) + +#define PCI_CONFIGURATION_BASE_QVA 0xaf000000 +#define PCI_BRIDGE_CONFIGURATION_BASE_QVA 0xaf000000 +#define PCI_CONFIG_CYCLE_TYPE_0 0x0 // Local PCI device +#define PCI_CONFIG_CYCLE_TYPE_1 0x1 // Nested PCI device + +#define PCI_ISA_BRIDGE_HEADER_OFFSET_P2 (0x00070000 >> IO_BIT_SHIFT) // AD[18] +#define PCI_ISA_BRIDGE_HEADER_OFFSET_P1 (0x00800000 >> IO_BIT_SHIFT) // AD[18] + +// +// PCI-ISA Bridge Non-Configuration control register offsets. +// +#define SIO_II_EDGE_LEVEL_CONTROL_1 (0x9a00 >> IO_BIT_SHIFT) +#define SIO_II_EDGE_LEVEL_CONTROL_2 (0x9a20 >> IO_BIT_SHIFT) + +// +// PCI Sparse I/O space offsets for unique functions on Avanti. +// + +#define PCI_INDEX (0x04c0 >> IO_BIT_SHIFT) +#define PCI_DATA (0x04e0 >> IO_BIT_SHIFT) +#define PCI_INT_REGISTER 0x14 +#define PCI_INT_LEVEL_REGISTER 0x15 +#define PCI_ISA_CONTROL_REGISTER 0x16 +#define DISABLE_PINTA_0 0x0f +#define DISABLE_PINTA_1 0xf0 +#define DISABLE_PINTA_2 0x0f +#define ENABLE_PINTA_0_AT_IRQ9 0x0d +#define ENABLE_PINTA_1_AT_IRQ10 0xb0 +#define ENABLE_PINTA_2_AT_IRQ15 0x07 +#define L2EEN0_LEVEL 0x10 +#define L2EEN1_LEVEL 0x20 +#define L2EEN2_LEVEL 0x40 +#define ENABLE_FLOPPY_WRITE 0x10 +#define DISABLE_IDE_DMA 0x08 +#define DISABLE_SCSI_TERMINATION 0x04 +#define DISABLE_SCSI_IRQL_11 0x02 +#define DISABLE_MOUSE_IRQL_12 0x00 + +// +// PCI-ISA Bridge Configuration register offsets. +// +#define PCI_VENDOR_ID (0x0000 >> IO_BIT_SHIFT) +#define PCI_DEVICE_ID (0x0040 >> IO_BIT_SHIFT) +#define PCI_COMMAND (0x0080 >> IO_BIT_SHIFT) +#define PCI_DEVICE_STATUS (0x00c0 >> IO_BIT_SHIFT) +#define PCI_REVISION (0x0100 >> IO_BIT_SHIFT) +#define PCI_CONTROL (0x0800 >> IO_BIT_SHIFT) +#define PCI_ARBITER_CONTROL (0x0820 >> IO_BIT_SHIFT) +#define ISA_ADDR_DECODER_CONTROL (0x0900 >> IO_BIT_SHIFT) +#define UTIL_BUS_CHIP_SELECT_ENAB_A (0x09c0 >> IO_BIT_SHIFT) +#define UTIL_BUS_CHIP_SELECT_ENAB_B (0x09e0 >> IO_BIT_SHIFT) +#define PIRQ0_ROUTE_CONTROL (0x0c00 >> IO_BIT_SHIFT) +#define PIRQ1_ROUTE_CONTROL (0x0c20 >> IO_BIT_SHIFT) +#define PIRQ2_ROUTE_CONTROL (0x0c40 >> IO_BIT_SHIFT) +#define PIRQ3_ROUTE_CONTROL (0x0c60 >> IO_BIT_SHIFT) + +// +// SIO-II value for setting edge/level operation in the control words. +// +#define IRQ0_LEVEL_SENSITIVE 0x01 +#define IRQ1_LEVEL_SENSITIVE 0x02 +#define IRQ2_LEVEL_SENSITIVE 0x04 +#define IRQ3_LEVEL_SENSITIVE 0x08 +#define IRQ4_LEVEL_SENSITIVE 0x10 +#define IRQ5_LEVEL_SENSITIVE 0x20 +#define IRQ6_LEVEL_SENSITIVE 0x40 +#define IRQ7_LEVEL_SENSITIVE 0x80 +#define IRQ8_LEVEL_SENSITIVE 0x01 +#define IRQ9_LEVEL_SENSITIVE 0x02 +#define IRQ10_LEVEL_SENSITIVE 0x04 +#define IRQ11_LEVEL_SENSITIVE 0x08 +#define IRQ12_LEVEL_SENSITIVE 0x10 +#define IRQ13_LEVEL_SENSITIVE 0x20 +#define IRQ14_LEVEL_SENSITIVE 0x40 +#define IRQ15_LEVEL_SENSITIVE 0x80 + +// +// Values for enabling an IORQ route control setting. +// +#define PIRQX_ROUTE_IRQ3 0x03 +#define PIRQX_ROUTE_IRQ4 0x04 +#define PIRQX_ROUTE_IRQ5 0x05 +#define PIRQX_ROUTE_IRQ6 0x06 +#define PIRQX_ROUTE_IRQ7 0x07 +#define PIRQX_ROUTE_IRQ9 0x09 +#define PIRQX_ROUTE_IRQ10 0x0a +#define PIRQX_ROUTE_IRQ11 0x0b +#define PIRQX_ROUTE_IRQ12 0x0c +#define PIRQX_ROUTE_IRQ14 0x0d +#define PIRQX_ROUTE_IRQ15 0x0f +#define PIRQX_ROUTE_ENABLE 0x00 + +#endif //!_LANGUAGE_ASSEMBLY + +// +// Define primary (and only) CPU on an Avanti system +// + +#define HAL_PRIMARY_PROCESSOR ((ULONG)0x0) +#define HAL_MAXIMUM_PROCESSOR ((ULONG)0x0) + +// +// Define the default processor clock frequency used before the actual +// value can be determined. +// + +#define DEFAULT_PROCESSOR_FREQUENCY_MHZ (200) + +#endif // _AVANTIDEF_ + + + + diff --git a/private/ntos/nthals/halavant/alpha/bios.c b/private/ntos/nthals/halavant/alpha/bios.c new file mode 100644 index 000000000..3a9d3aa50 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/bios.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\bios.c" + diff --git a/private/ntos/nthals/halavant/alpha/busdata.c b/private/ntos/nthals/halavant/alpha/busdata.c new file mode 100644 index 000000000..cc2a153c1 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/busdata.c @@ -0,0 +1,125 @@ +/*++ + + +Copyright (c) 1989 Microsoft Corporation +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + busdata.c + +Abstract: + + This module contains get/set bus data routines. + +Author: + + Darryl E. Havens (darrylh) 11-Apr-1990 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#include "halp.h" + +// +// External Function Prototypes +// + +ULONG +HalpNoBusData ( + IN PVOID BusHandler, + IN PVOID RootHandler, + IN ULONG SlotNumber, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length + ); + +#ifdef ALLOC_PRAGMA +#pragma alloc_text(INIT,HalpRegisterInternalBusHandlers) +#endif + + +VOID +HalpRegisterInternalBusHandlers ( + VOID + ) +/*++ + +Routine Description: + + This function registers the bushandlers for buses on the system + that will always be present on the system. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + PBUS_HANDLER Bus; + + // + // Initalize BusHandler data before registering any handlers + // + + HalpInitBusHandler (); + + // + // Build the processor internal bus 0 + // + + HaliRegisterBusHandler (ProcessorInternal, // Bus Type + -1, // No config space + 0, // Bus Number + -1, // No parent bus type + 0, // No parent bus number + 0, // No extension data + NULL, // No install handler + &Bus); // Bushandler return + + Bus->GetInterruptVector = HalpGetSystemInterruptVector; + + // + // Build internal-bus 0, or system level bus + // + + HaliRegisterBusHandler (Internal, // Bus Type + -1, // No config space + 0, // Bus Number + -1, // No parent bus type + 0, // No parent bus number + 0, // No extension data + NULL, // No install handler + &Bus); // Bushandler return + + Bus->GetInterruptVector = HalpGetSystemInterruptVector; + Bus->TranslateBusAddress = HalpTranslateSystemBusAddress; + + // + // Build Isa bus #0 + // + + HaliRegisterBusHandler (Isa, // Bus Type + -1, // No config space + 0, // Internal bus #0 + Internal, // Parent bus type + 0, // Parent bus number + 0, // No extension data + NULL, // No install handler + &Bus); // Bushandler return + + Bus->GetBusData = HalpNoBusData; + Bus->AdjustResourceList = HalpAdjustIsaResourceList; + +} diff --git a/private/ntos/nthals/halavant/alpha/cache.c b/private/ntos/nthals/halavant/alpha/cache.c new file mode 100644 index 000000000..561528477 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/cache.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\cache.c" + diff --git a/private/ntos/nthals/halavant/alpha/chipset.h b/private/ntos/nthals/halavant/alpha/chipset.h new file mode 100644 index 000000000..0a72ef8cb --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/chipset.h @@ -0,0 +1 @@ +#include "apecs.h" diff --git a/private/ntos/nthals/halavant/alpha/ebinitnt.c b/private/ntos/nthals/halavant/alpha/ebinitnt.c new file mode 100644 index 000000000..d11f3c79d --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ebinitnt.c @@ -0,0 +1,857 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation +Copyright (c) 1994 Digital Equipment Corporation + + +Module Name: + + ebinitnt.c + +Abstract: + + + This module implements the platform-specific initialization for + an Avanti system. + +Author: + + Joe Notarangelo 25-Oct-1993 + +Environment: + + Kernel mode only. + +Revision History: + +--*/ + +#include "halp.h" +#include "pcrtc.h" +#include "avantdef.h" +#include "halpcsl.h" +#include "eisa.h" +#include "pci.h" +#include "pcip.h" +#include "iousage.h" + +#include "fwcallbk.h" + +#include <ntverp.h> // to get the product build number. +// +// Define extern global buffer for the Uncorrectable Error Frame. +// declared in halalpha\inithal.c +// + +extern PERROR_FRAME PUncorrectableError; + +#if DBG +VOID +DumpEpic( + VOID + ); +#endif // DBG + +// +// Define global data for builtin device interrupt enables. +// + +USHORT HalpBuiltinInterruptEnable; + + +// irql mask and tables +// +// irql 0 - passive +// irql 1 - sfw apc level +// irql 2 - sfw dispatch level +// irql 3 - device low +// irql 4 - device high +// irql 5 - clock +// irql 6 - real time, ipi, performance counters +// irql 7 - error, mchk, nmi, halt +// +// +// IDT mappings: +// For the built-ins, GetInterruptVector will need more info, +// or it will have to be built-in to the routines, since +// these don't match IRQL levels in any meaningful way. +// +// 0 passive 8 perf cntr 1 +// 1 apc 9 +// 2 dispatch 10 PIC +// 3 11 +// 4 12 errors +// 5 clock 13 +// 6 perf cntr 0 14 halt +// 7 nmi 15 +// +// This is assuming the following prioritization: +// nmi +// halt +// errors +// performance counters +// clock +// pic + +// +// The hardware interrupt pins are used as follows for Avanti +// +// IRQ_H[0] = EPIC Error +// IRQ_H[1] = unused +// IRQ_H[2] = PIC +// IRQ_H[3] = NMI +// IRQ_H[4] = Clock +// IRQ_H[5] = Halt + +// +// For information purposes: here is what the IDT division looks like: +// +// 000-015 Built-ins (we only use 8 entries; NT wants 10) +// 016-031 ISA +// 048-063 EISA +// 080-095 PCI +// 112-127 Turbo Channel +// 128-255 unused, as are all other holes +// + +// +// Define the bus type, this value allows us to distinguish between +// EISA and ISA systems. +// +ULONG HalpBusType = MACHINE_TYPE_ISA; + +// +// These globals make available the specifics of the Avanti platform +// we're running in. +// +BOOLEAN ApecsPass2; +BOOLEAN SioCStep; + +// +// This is the PCI Memory space that cannot be used by anyone +// and therefore the HAL says it is reserved for itself +// + +ADDRESS_USAGE +AvantiPCIMemorySpace = { + NULL, CmResourceTypeMemory, PCIUsage, + { + __8MB, __32MB - __8MB, // Start=8MB; Length=24Mb (8 through 32) + 0,0 + } +}; + +// +// Define global data used to communicate new clock rates to the clock +// interrupt service routine. +// + +ULONG HalpCurrentTimeIncrement; +ULONG HalpNextRateSelect; +ULONG HalpNextTimeIncrement; +ULONG HalpNewTimeIncrement; + + +VOID +HalpInitializeHAERegisters( + VOID + ); + +VOID +HalpClearInterrupts( + ); + +VOID +HalpParseLoaderBlock( + PLOADER_PARAMETER_BLOCK LoaderBlock + ); + + +BOOLEAN +HalpInitializeInterrupts ( + VOID + ) + +/*++ + +Routine Description: + + This function initializes interrupts for an Alpha system. + +Arguments: + + None. + +Return Value: + + A value of TRUE is returned if the initialization is successfully + completed. Otherwise a value of FALSE is returned. + +--*/ + +{ + + UCHAR DataByte; + ULONG DataLong; + ULONG Index; + ULONG Irq; + KIRQL Irql; + UCHAR Priority; + ULONG Vector; + + // + // Initialize HAL processor parameters based on estimated CPU speed. + // This must be done before HalpStallExecution is called. Compute integral + // megahertz first to avoid rounding errors due to imprecise cycle clock + // period values. + // + + HalpInitializeProcessorParameters(); + + // + // Connect the Stall interrupt vector to the clock. When the + // profile count is calculated, we then connect the normal + // clock. + // + + PCR->InterruptRoutine[CLOCK2_LEVEL] = HalpStallInterrupt; + + // + // Clear all pending interrupts + // + + HalpClearInterrupts(); + + // + // Start the peridodic interrupt from the RTC + // + HalpProgramIntervalTimer(MAXIMUM_RATE_SELECT); + +//jnfix, wkc - init the Eisa interrupts after the chip, don't init the +// PIC here, fix halenablesysteminterrupt to init the pic +// interrrupt, as in sable + + // + // Initialize the PCI/ISA interrupt controller. + // + + HalpInitializePCIInterrupts(); + + // + // Initialize the 21064 interrupts. + // + + HalpInitialize21064Interrupts(); + + HalpEnable21064SoftwareInterrupt( Irql = APC_LEVEL ); + HalpEnable21064SoftwareInterrupt( Irql = DISPATCH_LEVEL ); + HalpEnable21064HardwareInterrupt( Irq = 4, + Irql = CLOCK_LEVEL, + Vector = CLOCK_VECTOR, + Priority = 0 ); + HalpEnable21064HardwareInterrupt( Irq = 3, + Irql = HIGH_LEVEL, + Vector = EISA_NMI_VECTOR, + Priority = 0 ); + HalpEnable21064HardwareInterrupt( Irq = 2, + Irql = DEVICE_LEVEL, + Vector = PIC_VECTOR, + Priority = 0 ); + + return TRUE; + +} + + +VOID +HalpClearInterrupts( + ) +/*++ + +Routine Description: + + This function no longer does anything. + +Arguments: + + None. + +Return Value: + + None. + +--*/ + +{ + return; +} + + +VOID +HalpSetTimeIncrement( + VOID + ) +/*++ + +Routine Description: + + This routine is responsible for setting the time increment for an EV4 + based machine via a call into the kernel. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + + // + // Set the time increment value. + // + + HalpCurrentTimeIncrement = MAXIMUM_INCREMENT; + HalpNextTimeIncrement = MAXIMUM_INCREMENT; + HalpNextRateSelect = 0; + KeSetTimeIncrement( MAXIMUM_INCREMENT, MINIMUM_INCREMENT ); + +} + +// +// Define global data used to calibrate and stall processor execution. +// + +ULONG HalpProfileCountRate; + +VOID +HalpInitializeClockInterrupts( + VOID + ) + +/*++ + +Routine Description: + + This function is called during phase 1 initialization to complete + the initialization of clock interrupts. For EV4, this function + connects the true clock interrupt handler and initializes the values + required to handle profile interrupts. + +Arguments: + + None. + +Return Value: + + None. + +--*/ + +{ + + // + // Compute the profile interrupt rate. + // + + HalpProfileCountRate = ((1000 * 1000 * 10) / KeQueryTimeIncrement()); + + // + // Set the time increment value and connect the real clock interrupt + // routine. + // + + PCR->InterruptRoutine[CLOCK2_LEVEL] = HalpClockInterrupt; + + return; +} + +VOID +HalpEstablishErrorHandler( + VOID + ) +/*++ + +Routine Description: + + This routine performs the initialization necessary for the HAL to + begin servicing machine checks. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + BOOLEAN ReportCorrectables; + + // + // Connect the machine check handler via the PCR. + // + + PCR->MachineCheckError = HalMachineCheck; + + // + // Initialize error handling for APECS. + // + + HalpInitializeMachineChecks( ReportCorrectables = FALSE ); + + return; +} + +VOID +HalpInitializeMachineDependent( + IN ULONG Phase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock + ) +/*++ + +Routine Description: + + This function performs any EV4-specific initialization based on + the current phase on initialization. + +Arguments: + + Phase - Supplies an indicator for phase of initialization, phase 0 or + phase 1. + + LoaderBlock - supplies a pointer to the loader block. + +Return Value: + + None. + +--*/ +{ + ULONG PciBridgeHeaderOffset; + ULONG SioRevision; + COMANCHE_EDSR Edsr; + + if( Phase == 0 ){ + + // + // Phase 0 Initialization. + // + + // + // Parse the Loader Parameter block looking for PCI entry to determine + // if PCI parity should be disabled + // + + HalpParseLoaderBlock( LoaderBlock ); + + // + // Re-establish the error handler, to reflect the parity checking + // + + HalpEstablishErrorHandler(); + + // + // Find out what sort of APECS chip set we have in this Avanti. Clear + // the structure, first. + // + Edsr.all = 0; + Edsr.all = READ_COMANCHE_REGISTER( &((PCOMANCHE_CSRS) + (APECS_COMANCHE_BASE_QVA))->ErrorAndDiagnosticStatusRegister); + ApecsPass2 = (Edsr.Pass2 ? TRUE : FALSE); + +#ifdef HALDBG + DbgPrint("HalpInitializeMachineDependent: ApecsPass2 is %x\n",ApecsPass2); +#endif + + // + // Determine if we have a SIO-II, rather than SIO. If the result + // is 0x3, it's SIO-II, else the result will be 0x0. + // + + if (ApecsPass2) { + PciBridgeHeaderOffset = PCI_ISA_BRIDGE_HEADER_OFFSET_P2; + } else { + PciBridgeHeaderOffset = PCI_ISA_BRIDGE_HEADER_OFFSET_P1; + } + SioRevision = READ_CONFIG_UCHAR((PCHAR)(PCI_CONFIGURATION_BASE_QVA + | PciBridgeHeaderOffset | PCI_REVISION), + PCI_CONFIG_CYCLE_TYPE_0); + SioCStep = (SioRevision == 0x3 ? TRUE : FALSE); + +#ifdef HALDBG + DbgPrint("HalpInitializeMachineDependent: SioCStep is %x\n",SioCStep); +#endif + + HalpInitializeHAERegisters(); + + } else { + + // + // Phase 1 Initialization. + // + + // + // Initialize the existing bus handlers. + // + + HalpRegisterInternalBusHandlers(); + + // + // Initialize PCI Bus. + // + + HalpInitializePCIBus (LoaderBlock); + + // + // Initialize profiler. + // + + HalpInitializeProfiler(); + + } + + return; + +} + + +VOID +HalpStallInterrupt ( + VOID + ) + +/*++ + +Routine Description: + + This function serves as the stall calibration interrupt service + routine. It is executed in response to system clock interrupts + during the initialization of the HAL layer. + +Arguments: + + None. + +Return Value: + + None. + +--*/ + +{ + + HalpAcknowledgeClockInterrupt(); + + return; +} + + +ULONG +HalSetTimeIncrement ( + IN ULONG DesiredIncrement + ) + +/*++ + +Routine Description: + + This function is called to set the clock interrupt rate to the frequency + required by the specified time increment value. + +Arguments: + + DesiredIncrement - Supplies desired number of 100ns units between clock + interrupts. + +Return Value: + + The actual time increment in 100ns units. + +--*/ + +{ + ULONG NewTimeIncrement; + ULONG NextRateSelect; + KIRQL OldIrql; + + // + // Raise IRQL to the highest level, set the new clock interrupt + // parameters, lower IRQl, and return the new time increment value. + // + KeRaiseIrql(HIGH_LEVEL, &OldIrql); + if (DesiredIncrement < MINIMUM_INCREMENT) { + DesiredIncrement = MINIMUM_INCREMENT; + } + if (DesiredIncrement > MAXIMUM_INCREMENT) { + DesiredIncrement = MAXIMUM_INCREMENT; + } + + // + // Find the allowed increment that is less than or equal to + // the desired increment. + // + if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS4) { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS4; + NextRateSelect = RTC_RATE_SELECT4; + } else if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS3) { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS3; + NextRateSelect = RTC_RATE_SELECT3; + } else if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS2) { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS2; + NextRateSelect = RTC_RATE_SELECT2; + } else { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS1; + NextRateSelect = RTC_RATE_SELECT1; + } + + HalpNextRateSelect = NextRateSelect; + HalpNewTimeIncrement = NewTimeIncrement; + + KeLowerIrql(OldIrql); + + return NewTimeIncrement; +} + + +VOID +HalpInitializeHAERegisters( + VOID + ) +/*++ + +Routine Description: + + This function initializes the HAE registers in the EPIC/APECS chipset. + It also register the holes in the PCI memory space if any. + +Arguments: + + none + +Return Value: + + none + +--*/ +{ + // + // We set HAXR1 to 0. This means no address extension + // + + WRITE_EPIC_REGISTER( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr1, 0); + + // + // We set HAXR2 to 0. Which means we have the following + // PCI IO addresses: + // 0 to 64KB VALID. HAXR2 Not used in address translation + // 64K to 16MB VALID. HAXR2 is used in the address translation + // + + WRITE_EPIC_REGISTER( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr2, 0); + + // + // Report that the apecs mapping to the Io subsystem + // + + HalpRegisterAddressUsage (&AvantiPCIMemorySpace); + +#if DBG + DumpEpic(); +#endif // DBG +} + + +VOID +HalpResetHAERegisters( + VOID + ) +/*++ + +Routine Description: + + This function resets the HAE registers in the EPIC/APECS chipset to 0. + This is routine called during a shutdown so that the prom + gets a predictable environment. + +Arguments: + + none + +Return Value: + + none + +--*/ +{ + WRITE_EPIC_REGISTER( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr1, 0 ); + WRITE_EPIC_REGISTER( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr2, 0 ); +} + +VOID +HalpGetMachineDependentErrorFrameSizes( + PULONG RawProcessorSize, + PULONG RawSystemInfoSize + ) +/*++ + +Routine Description: + + This function returns the size of the system specific structures. + + +Arguments: + + RawProcessorSize - Pointer to a buffer that will receive the + size of the processor specific error information buffer. + + RawSystemInfoSize - Pointer to a buffer that will receive the + size of the system specific error information buffer. + +Return Value: + + none + +--*/ +{ + *RawProcessorSize = sizeof(PROCESSOR_EV4_UNCORRECTABLE); + *RawSystemInfoSize = sizeof(APECS_UNCORRECTABLE_FRAME); + return; +} + + +VOID +HalpGetSystemInfo(SYSTEM_INFORMATION *SystemInfo) +/*++ + +Routine Description: + + This function fills in the System information. + + +Arguments: + + SystemInfo - Pointer to the SYSTEM_INFORMATION buffer that needs + to be filled in. + +Return Value: + + none + +--*/ +{ + char systemtype[] = "Avanti"; + EXTENDED_SYSTEM_INFORMATION FwExtSysInfo; + + + VenReturnExtendedSystemInformation(&FwExtSysInfo); + + RtlCopyMemory(SystemInfo->FirmwareRevisionId, + FwExtSysInfo.FirmwareVersion, + 16); + + RtlCopyMemory(SystemInfo->SystemType,systemtype, 8); + + SystemInfo->ClockSpeed = + ((1000 * 1000) + (PCR->CycleClockPeriod >> 1)) / PCR->CycleClockPeriod; + + SystemInfo->SystemRevision = PCR->SystemRevision; + + RtlCopyMemory(SystemInfo->SystemSerialNumber, + PCR->SystemSerialNumber, + 16); + + SystemInfo->SystemVariant = PCR->SystemVariant; + + + SystemInfo->PalMajorVersion = PCR->PalMajorVersion; + SystemInfo->PalMinorVersion = PCR->PalMinorVersion; + + SystemInfo->OsRevisionId = VER_PRODUCTBUILD; + + // + // For now fill in dummy values. + // + SystemInfo->ModuleVariant = 1UL; + SystemInfo->ModuleRevision = 1UL; + SystemInfo->ModuleSerialNumber = 0; + + return; +} + +VOID +HalpInitializeUncorrectableErrorFrame ( + VOID + ) +/*++ + +Routine Description: + + This function Allocates an Uncorrectable Error frame for this + system and initializes the frame with certain constant/global + values. + + This is routine called during machine dependent system + Initialization. + +Arguments: + + none + +Return Value: + + none + +--*/ +{ + PROCESSOR_EV4_UNCORRECTABLE processorFrame; + APECS_UNCORRECTABLE_FRAME AvantiUnCorrrectable; + + // + // If the Uncorrectable error buffer is not set then simply return + // + if(PUncorrectableError == NULL) + return; + + PUncorrectableError->Signature = ERROR_FRAME_SIGNATURE; + + PUncorrectableError->FrameType = UncorrectableFrame; + + // + // ERROR_FRAME_VERSION is define in errframe.h and will + // change as and when there is a change in the errframe.h. + // This Version number helps the service, that reads this + // information from the dumpfile, to check if it knows about + // this frmae version type to decode. If it doesn't know, it + // will dump the entire frame to the EventLog with a message + // "Error Frame Version Mismatch". + // + + PUncorrectableError->VersionNumber = ERROR_FRAME_VERSION; + + // + // The sequence number will always be 1 for Uncorrectable errors. + // + + PUncorrectableError->SequenceNumber = 1; + + // + // The PerformanceCounterValue field is not used for Uncorrectable + // errors. + // + + PUncorrectableError->PerformanceCounterValue = 0; + + // + // We will fill in the UncorrectableFrame.SystemInfo here. + // + + HalpGetSystemInfo(&PUncorrectableError->UncorrectableFrame.System); + + PUncorrectableError->UncorrectableFrame.Flags.SystemInformationValid = 1; + + return; +} diff --git a/private/ntos/nthals/halavant/alpha/ebintsup.c b/private/ntos/nthals/halavant/alpha/ebintsup.c new file mode 100644 index 000000000..4306a1469 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ebintsup.c @@ -0,0 +1,447 @@ +/*++ + +Copyright (c) 1990 Microsoft Corporation +Copyright (c) 1992, 1993 Digital Equipment Corporation + +Module Name: + + ebintsup.c + +Abstract: + + The module provides the interrupt support for EB66/Mustang, and + Avanti systems. + +Author: + + Eric Rehm (DEC) 29-December-1993 + +Revision History: + + +--*/ + + +#include "halp.h" +#include "eisa.h" +#include "ebsgdma.h" +#include "avantdef.h" +#include "pcrtc.h" +#include "pintolin.h" + +// +// Reference the boolean variable for SIO-II vs. SIO, i.e., the +// Avanti pass 2 MLB, and the boolean for the APECS pass 2 on the +// Avanti pass 2 daughter card. +// +extern BOOLEAN SioCStep; +extern BOOLEAN ApecsPass2; + +// +// Declare the interrupt handler for the PCI and ISA bus. +// + +BOOLEAN +HalpSioDispatch( + VOID + ); + +// +// The following is the interrupt object used for DMA controller interrupts. +// DMA controller interrupts occur when a memory parity error occurs or a +// programming error occurs to the DMA controller. +// + +KINTERRUPT HalpEisaNmiInterrupt; + +// +// The following function initializes NMI handling. +// + +VOID +HalpInitializeNMI( + VOID + ); + +// +// The following function is called when an ISA NMI occurs. +// + +BOOLEAN +HalHandleNMI( + IN PKINTERRUPT Interrupt, + IN PVOID ServiceContext + ); + + +BOOLEAN +HalpInitializePCIInterrupts ( + VOID + ) + +/*++ + +Routine Description: + + This routine initializes the structures necessary for EISA & PCI operations + and connects the intermediate interrupt dispatcher. It also initializes the + ISA interrupt controller; in the case of the SIO-II in Avanti, the + integral interrupt controller is compatible with the EISA interrupt + contoller used on Jensen. + +Arguments: + + None. + +Return Value: + + If the second level interrupt dispatcher is connected, then a value of + TRUE is returned. Otherwise, a value of FALSE is returned. + +--*/ + +{ + + ULONG PciIsaBridgeHeaderOffset; + KIRQL oldIrql; + + + // + // Initialize the EISA NMI interrupt. + // + + HalpInitializeNMI(); + + + // + // Directly connect the ISA interrupt dispatcher to the level for + // ISA bus interrupt. + // + // N.B. This vector is reserved for exclusive use by the HAL (see + // interrupt initialization. + // + + PCR->InterruptRoutine[PIC_VECTOR] = HalpSioDispatch; + HalEnableSystemInterrupt(PIC_VECTOR, ISA_DEVICE_LEVEL, LevelSensitive); + + + // + // Intitialize interrupt controller + // + + KeRaiseIrql(ISA_DEVICE_LEVEL, &oldIrql); + + // + // We must declare the right form for the APECS PCI/ISA bridge + // configuration space device selector for use in the initialization + // of the interrupts. + // + if (ApecsPass2) { + PciIsaBridgeHeaderOffset = PCI_ISA_BRIDGE_HEADER_OFFSET_P2; + } else { + PciIsaBridgeHeaderOffset = PCI_ISA_BRIDGE_HEADER_OFFSET_P1; + } + +// +// Now done completely in the Firmware - wkc +// + +#if 0 + if (SioCStep) { + + // + // Pass2 MLB pin to line table + // + + (PVOID) HalpPCIPinToLineTable = (PVOID) AvantiPCIPinToLineTable; + + // + // Setup the Avanti interrupt assignments for the C-Step SIO; this + // is done with registers that are internal to the SIO-II, PIRQ0, + // PIRQ1, PIRQ2, and PIRQ3. They're at offsets 0x60, 0x61, 0x62, + // and 0x63 of the SIO-II's configuration registers. The effect + // of these registers is to steer the PCI interrupts into the IRQx + // inputs of the SIO's internal cascaded 82C59 interrupt controllers. + // These controllers are then programmed in their usual fashion. + // + // Set up interrupts from PCI slots 0, 1, and 2, compatible with + // Avanti pass 1 MLB, i.e., steer the interrupt from each PCI + // slot or device into the default IRQL from pass 1 Avanti; enable + // the routings. + // + WRITE_CONFIG_UCHAR((PCHAR)(PCI_CONFIGURATION_BASE_QVA + | PciIsaBridgeHeaderOffset | PIRQ0_ROUTE_CONTROL), + PIRQX_ROUTE_IRQ10 | PIRQX_ROUTE_ENABLE, + PCI_CONFIG_CYCLE_TYPE_0); + + WRITE_CONFIG_UCHAR((PCHAR)(PCI_CONFIGURATION_BASE_QVA + | PciIsaBridgeHeaderOffset | PIRQ1_ROUTE_CONTROL), + PIRQX_ROUTE_IRQ15 | PIRQX_ROUTE_ENABLE, + PCI_CONFIG_CYCLE_TYPE_0); + + WRITE_CONFIG_UCHAR((PCHAR)(PCI_CONFIGURATION_BASE_QVA + | PciIsaBridgeHeaderOffset | PIRQ2_ROUTE_CONTROL), + PIRQX_ROUTE_IRQ9 | PIRQX_ROUTE_ENABLE, + PCI_CONFIG_CYCLE_TYPE_0); + + // + // Set up interrupt from SCSI (IRQ11), and enable the routing. + // + WRITE_CONFIG_UCHAR((PCHAR)(PCI_CONFIGURATION_BASE_QVA + | PciIsaBridgeHeaderOffset | PIRQ3_ROUTE_CONTROL), + PIRQX_ROUTE_IRQ11 | PIRQX_ROUTE_ENABLE, + PCI_CONFIG_CYCLE_TYPE_0); + + // + // Select "level" operation for PCI PIRQx interrupt lines, and + // "edge" for ISA devices, e.g., mouse at IRQL12. Default is "edge" + // so no mention means "edge". + // + WRITE_REGISTER_UCHAR((PCHAR)(PCI_SPARSE_IO_BASE_QVA + | SIO_II_EDGE_LEVEL_CONTROL_2), + IRQ11_LEVEL_SENSITIVE | IRQ10_LEVEL_SENSITIVE | + IRQ9_LEVEL_SENSITIVE | IRQ15_LEVEL_SENSITIVE); + + } else { + + // + // Pass1 MLB pin to line table + // + + (PVOID) HalpPCIPinToLineTable = (PVOID) AvantiPCIPinToLineTableP1; + + // + // + // Anything prior to a C-step SIO chip has a funny MUX register pair + // for PCI interrupts. + // + // Avanti Pass1 only: Intialize PCI Interrupt translation mux + // + // Select PCI Int Register. + // + + WRITE_REGISTER_UCHAR((PUCHAR)(PCI_SPARSE_IO_BASE_QVA | PCI_INDEX), + PCI_INT_REGISTER); // PCI Index Register 0x14 + // + // Enable interrupts from PCI slots 0 and 1 + // + + WRITE_REGISTER_UCHAR((PUCHAR)(PCI_SPARSE_IO_BASE_QVA | PCI_DATA), + ENABLE_PINTA_0_AT_IRQ9 | + ENABLE_PINTA_1_AT_IRQ10); + + // + // Select PCI Int/Level Register. + // + + WRITE_REGISTER_UCHAR((PUCHAR)(PCI_SPARSE_IO_BASE_QVA | PCI_INDEX), + PCI_INT_LEVEL_REGISTER); // PCI Index Register 0x15 + // + // Enable interrupts from PCI slot 2; select "level" operation for + // all three interrupt lines. + // + + WRITE_REGISTER_UCHAR((PUCHAR)(PCI_SPARSE_IO_BASE_QVA | PCI_DATA), + ENABLE_PINTA_2_AT_IRQ15 | + L2EEN0_LEVEL | L2EEN1_LEVEL | L2EEN2_LEVEL); + } +// end AVANTI_PROTO1 + +#endif // wkc + + HalpInitializeSioInterrupts(); + + // + // Restore IRQL level. + // + + KeLowerIrql(oldIrql); + + // + // Initialize the DMA mode registers to a default value. + // Disable all of the DMA channels except channel 4 which is the + // cascade of channels 0-3. + // + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Dma1BasePort.AllMask, + 0x0F + ); + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Dma2BasePort.AllMask, + 0x0E + ); + + return(TRUE); +} + +VOID +HalpInitializeNMI( + VOID + ) +/*++ + +Routine Description: + + This function is called to intialize SIO NMI interrupts. + +Arguments: + + None. + +Return Value: + + None. +--*/ +{ + UCHAR DataByte; + + // + // Initialize the SIO NMI interrupt. + // + + KeInitializeInterrupt( &HalpEisaNmiInterrupt, + HalHandleNMI, + NULL, + NULL, + EISA_NMI_VECTOR, + EISA_NMI_LEVEL, + EISA_NMI_LEVEL, + LevelSensitive, + FALSE, + 0, + FALSE + ); + + // + // Don't fail if the interrupt cannot be connected. + // + + KeConnectInterrupt( &HalpEisaNmiInterrupt ); + + // + // Clear the Eisa NMI disable bit. This bit is the high order of the + // NMI enable register. + // + + DataByte = 0; + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable, + DataByte + ); + +} + +BOOLEAN +HalHandleNMI( + IN PKINTERRUPT Interrupt, + IN PVOID ServiceContext + ) +/*++ + +Routine Description: + + This function is called when an EISA NMI occurs. It print the appropriate + status information and bugchecks. + +Arguments: + + Interrupt - Supplies a pointer to the interrupt object + + ServiceContext - Bug number to call bugcheck with. + +Return Value: + + Returns TRUE. + +--*/ +{ + UCHAR StatusByte; + + StatusByte = + READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiStatus); + + if (StatusByte & 0x80) { + HalDisplayString ("NMI: Parity Check / Parity Error\n"); + } + + if (StatusByte & 0x40) { + HalDisplayString ("NMI: Channel Check / IOCHK\n"); + } + + // + // This is an Sio machine, no extnded nmi information, so just do it. + // + + + KeBugCheck(NMI_HARDWARE_FAILURE); + return(TRUE); +} + +UCHAR +HalpAcknowledgeEisaInterrupt( + PVOID ServiceContext + ) +/*++ + +Routine Description: + + Acknowledge the EISA interrupt from the programmable interrupt controller. + Return the vector number of the highest priority pending interrupt. + +Arguments: + + ServiceContext - Service context of the interrupt service supplies + a pointer to the EISA interrupt acknowledge register. + +Return Value: + + Return the value of the highest priority pending interrupt. + +--*/ +{ + UCHAR InterruptVector; + + // + // Read the interrupt vector from the PIC. + // + + InterruptVector = READ_PORT_UCHAR(ServiceContext); + + return( InterruptVector ); + +} + +VOID +HalpAcknowledgeClockInterrupt( + VOID + ) +/*++ + +Routine Description: + + Acknowledge the clock interrupt from the interval timer. The interval + timer for EB66 comes from the Dallas real-time clock. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + + // + // Acknowledge the clock interrupt by reading the control register C of + // the Real Time Clock. + // + + HalpReadClockRegister( RTC_CONTROL_REGISTERC ); + + return; +} diff --git a/private/ntos/nthals/halavant/alpha/ebmapio.c b/private/ntos/nthals/halavant/alpha/ebmapio.c new file mode 100644 index 000000000..850894769 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ebmapio.c @@ -0,0 +1,153 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + ebmapio.c + +Abstract: + + This module contains the functions to map HAL-accessed I/O addresses + on the Avanti system. + +Author: + + Joe Notarangelo 25-Oct-1993 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#include "halp.h" +#include "avantdef.h" + +// +// Define global data used to locate the EISA control space. +// + +PVOID HalpEisaControlBase; +PVOID HalpEisaIntAckBase; +PVOID HalpCMOSRamBase; + + +BOOLEAN +HalpMapIoSpace ( + VOID + ) + +/*++ + +Routine Description: + + This routine maps the HAL I/O space for an Avanti + system using the Quasi VA. + +Arguments: + + None. + +Return Value: + + If the initialization is successfully completed, than a value of TRUE + is returned. Otherwise, a value of FALSE is returned. + +--*/ + +{ + PVOID PciIoSpaceBase; + + // + // CMOS ram addresses encoded in nvram.c - kept for commonality + // in environ.c + // + + HalpCMOSRamBase = (PVOID) 0; + + // + // Map base addresses in QVA space. + // + + PciIoSpaceBase = HAL_MAKE_QVA( APECS_PCI_IO_BASE_PHYSICAL ); + + HalpEisaControlBase = PciIoSpaceBase; + HalpEisaIntAckBase = HAL_MAKE_QVA( APECS_PCI_INTACK_BASE_PHYSICAL ); + + // + // Map the real-time clock registers. + // + + HalpRtcAddressPort = (PVOID)((ULONG)PciIoSpaceBase + RTC_ISA_ADDRESS_PORT); + HalpRtcDataPort = (PVOID)((ULONG)PciIoSpaceBase + RTC_ISA_DATA_PORT); + + return TRUE; + +} + +ULONG +HalpMapDebugPort( + IN ULONG ComPort, + OUT PULONG ReadQva, + OUT PULONG WriteQva + ) +/*++ + +Routine Description: + + This routine maps the debug com port so that the kernel debugger + may function - if called it is called very earlier in the boot sequence. + +Arguments: + + ComPort - Supplies the number of the com port to use as the debug port. + + ReadQva - Receives the QVA used to access the read registers of the debug + port. + + WriteQva - Receives the QVA used to access the write registers of the + debug port. + +Return Value: + + Returns the base bus address of the device used as the debug port. + +--*/ +{ + ULONG ComPortAddress; + ULONG PortQva; + + // + // Compute the port address, based on the desired com port. + // + + switch( ComPort ){ + + case 1: + + ComPortAddress = COM1_ISA_PORT_ADDRESS; + break; + + case 2: + default: + + ComPortAddress = COM2_ISA_PORT_ADDRESS; + + } + + // + // Return the QVAs for read and write access. + // + + PortQva = (ULONG)HAL_MAKE_QVA(APECS_PCI_IO_BASE_PHYSICAL) + ComPortAddress; + + *ReadQva = PortQva; + *WriteQva = PortQva; + + return ComPortAddress; + +} diff --git a/private/ntos/nthals/halavant/alpha/ebsgdma.c b/private/ntos/nthals/halavant/alpha/ebsgdma.c new file mode 100644 index 000000000..f2f033fad --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ebsgdma.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ebsgdma.c" + diff --git a/private/ntos/nthals/halavant/alpha/ebsysint.c b/private/ntos/nthals/halavant/alpha/ebsysint.c new file mode 100644 index 000000000..fb10ba0d1 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ebsysint.c @@ -0,0 +1,394 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + ebinitnt.c + +Abstract: + + This module implements the HAL enable/disable system interrupt, and + request interprocessor interrupt routines for the Avanti system. + +Author: + + Joe Notarangelo 25-Oct-1993 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#include "halp.h" +#include "avantdef.h" +#include "axp21064.h" + +// +// Define reference to the builtin device interrupt enables. +// + +extern USHORT HalpBuiltinInterruptEnable; + +#ifdef ALLOC_PRAGMA +#pragma alloc_text(PAGE,HalpGetSystemInterruptVector) +#endif + + +VOID +HalDisableSystemInterrupt ( + IN ULONG Vector, + IN KIRQL Irql + ) + +/*++ + +Routine Description: + + This routine disables the specified system interrupt. + +Arguments: + + Vector - Supplies the vector of the system interrupt that is disabled. + + Irql - Supplies the IRQL of the interrupting source. + +Return Value: + + None. + +--*/ + +{ + + ULONG Irq; + KIRQL OldIrql; + + // + // Raise IRQL to the highest level. + // + + KeRaiseIrql(HIGH_LEVEL, &OldIrql); + + // + // If the vector number is within the range of the ISA interrupts, then + // disable the ISA interrrupt. + // + + if (Vector >= ISA_VECTORS && + Vector < MAXIMUM_ISA_VECTOR && + Irql == ISA_DEVICE_LEVEL) { + HalpDisableSioInterrupt(Vector); + } + + // + // If the vector is a performance counter vector or one of the internal + // device vectors then disable the interrupt for the 21064. + // + + switch (Vector) { + + // + // Performance counter 0 interrupt (internal to 21064) + // + + case PC0_VECTOR: + case PC0_SECONDARY_VECTOR: + + HalpDisable21064PerformanceInterrupt( PC0_VECTOR ); + break; + + // + // Performance counter 1 interrupt (internal to 21064) + // + + case PC1_VECTOR: + case PC1_SECONDARY_VECTOR: + + HalpDisable21064PerformanceInterrupt( PC1_VECTOR ); + break; + + } //end switch Vector + + // + // Lower IRQL to the previous level. + // + + KeLowerIrql(OldIrql); + return; +} + +BOOLEAN +HalEnableSystemInterrupt ( + IN ULONG Vector, + IN KIRQL Irql, + IN KINTERRUPT_MODE InterruptMode + ) + +/*++ + +Routine Description: + + This routine enables the specified system interrupt. + +Arguments: + + Vector - Supplies the vector of the system interrupt that is enabled. + + Irql - Supplies the IRQL of the interrupting source. + + InterruptMode - Supplies the mode of the interrupt; LevelSensitive or + Latched. + +Return Value: + + TRUE if the system interrupt was enabled + +--*/ + +{ + BOOLEAN Enabled = FALSE; + ULONG Irq; + KIRQL OldIrql; + + // + // Raise IRQL to the highest level. + // + + KeRaiseIrql(HIGH_LEVEL, &OldIrql); + + // + // If the vector number is within the range of the ISA interrupts, then + // enable the ISA interrrupt and set the Level/Edge register. + // + + if (Vector >= ISA_VECTORS && + Vector < MAXIMUM_ISA_VECTOR && + Irql == ISA_DEVICE_LEVEL) { + HalpEnableSioInterrupt( Vector, InterruptMode ); + Enabled = TRUE; + } + + // + // If the vector is a performance counter vector or one of the + // internal device vectors then perform 21064-specific enable. + // + + switch (Vector) { + + // + // Performance counter 0 (internal to 21064) + // + + case PC0_VECTOR: + case PC0_SECONDARY_VECTOR: + + HalpEnable21064PerformanceInterrupt( PC0_VECTOR, Irql ); + Enabled = TRUE; + break; + + // + // Performance counter 1 (internal to 21064) + // + + case PC1_VECTOR: + case PC1_SECONDARY_VECTOR: + + HalpEnable21064PerformanceInterrupt( PC1_VECTOR, Irql ); + Enabled = TRUE; + break; + + } //end switch Vector + + // + // Lower IRQL to the previous level. + // + + KeLowerIrql(OldIrql); + return Enabled; +} + +ULONG +HalpGetSystemInterruptVector( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN ULONG BusInterruptLevel, + IN ULONG BusInterruptVector, + OUT PKIRQL Irql, + OUT PKAFFINITY Affinity + ) + +/*++ + +Routine Description: + + This function returns the system interrupt vector and IRQL level + corresponding to the specified bus interrupt level and/or vector. The + system interrupt vector and IRQL are suitable for use in a subsequent call + to KeInitializeInterrupt. + + We only use InterfaceType, and BusInterruptLevel. BusInterruptVector + for ISA and ISA are the same as the InterruptLevel, so ignore. + +Arguments: + + BusHandler - Registered BUSHANDLER for the target configuration space + + RootHandler - Registered BUSHANDLER for the orginating HalGetBusData + request. + + BusInterruptLevel - Supplies the bus specific interrupt level. + + BusInterruptVector - Supplies the bus specific interrupt vector. + + Irql - Returns the system request priority. + + Affinity - Returns the affinity for the requested vector + +Return Value: + + Returns the system interrupt vector corresponding to the specified device. + +--*/ + +{ + INTERFACE_TYPE InterfaceType = BusHandler->InterfaceType; + ULONG BusNumber = BusHandler->BusNumber; + + ULONG Vector; + + *Affinity = 1; + + switch (InterfaceType) { + + case ProcessorInternal: + + // + // Handle the internal defined for the processor itself + // and used to control the performance counters in the 21064. + // + + if( (Vector = HalpGet21064PerformanceVector( BusInterruptLevel, + Irql)) != 0 ){ + + // + // Performance counter was successfully recognized. + // + + return Vector; + + } else { + + // + // Unrecognized processor interrupt. + // + + *Irql = 0; + *Affinity = 0; + return 0; + + } //end if Vector + + break; + + case Isa: + + // + // Assumes all ISA devices coming in on same pin + // + + *Irql = ISA_DEVICE_LEVEL; + + // + // The vector is equal to the specified bus level plus the ISA_VECTOR. + // This is assuming that the ISA levels not assigned Interrupt Levels + // in the Beta programming guide are unused in the LCA system. + // Otherwise, need a different encoding scheme. + // + // Not all interrupt levels are actually supported on Beta; + // Should we make some of them illegal here? + + return(BusInterruptLevel + ISA_VECTORS); + break; + + + case Eisa: + + // + // Assumes all EISA devices coming in on same pin + // + + *Irql = EISA_DEVICE_LEVEL; + + // + // The vector is equal to the specified bus level plus the EISA_VECTOR. + // + + return(BusInterruptLevel + EISA_VECTORS); + break; + + case PCIBus: + + // + // Assumes all PCI devices coming in on same pin + // + + *Irql = ISA_DEVICE_LEVEL; + + // + // The vector is equal to the specified bus level plus the ISA_VECTOR + // + + return((BusInterruptLevel) + ISA_VECTORS); + + break; + + + + default: + + // + // Not an interface supported on EB66/Mustang systems + // + + *Irql = 0; + *Affinity = 0; + return(0); + break; + + } //end switch(InterfaceType) + +} + +VOID +HalRequestIpi ( + IN ULONG Mask + ) + +/*++ + +Routine Description: + + This routine requests an interprocessor interrupt on a set of processors. + This routine performs no function on an Avanti because it is a + uni-processor system. + +Arguments: + + Mask - Supplies the set of processors that are sent an interprocessor + interrupt. + +Return Value: + + None. + +--*/ + +{ + + return; +} diff --git a/private/ntos/nthals/halavant/alpha/eisasup.c b/private/ntos/nthals/halavant/alpha/eisasup.c new file mode 100644 index 000000000..0d46ef3e4 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/eisasup.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\eisasup.c" + diff --git a/private/ntos/nthals/halavant/alpha/environ.c b/private/ntos/nthals/halavant/alpha/environ.c new file mode 100644 index 000000000..75015a0a0 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/environ.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\environ.c" + diff --git a/private/ntos/nthals/halavant/alpha/ev4cache.c b/private/ntos/nthals/halavant/alpha/ev4cache.c new file mode 100644 index 000000000..b0cf9e3be --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ev4cache.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev4cache.c" + diff --git a/private/ntos/nthals/halavant/alpha/ev4int.c b/private/ntos/nthals/halavant/alpha/ev4int.c new file mode 100644 index 000000000..8a10705d7 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ev4int.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev4int.c" + diff --git a/private/ntos/nthals/halavant/alpha/ev4ints.s b/private/ntos/nthals/halavant/alpha/ev4ints.s new file mode 100644 index 000000000..6df823ab6 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ev4ints.s @@ -0,0 +1,6 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// +#include "..\halalpha\ev4ints.s" + diff --git a/private/ntos/nthals/halavant/alpha/ev4mchk.c b/private/ntos/nthals/halavant/alpha/ev4mchk.c new file mode 100644 index 000000000..697087c15 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ev4mchk.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev4mchk.c" + diff --git a/private/ntos/nthals/halavant/alpha/ev4mem.s b/private/ntos/nthals/halavant/alpha/ev4mem.s new file mode 100644 index 000000000..f410d09a3 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ev4mem.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev4mem.s" + diff --git a/private/ntos/nthals/halavant/alpha/ev4prof.c b/private/ntos/nthals/halavant/alpha/ev4prof.c new file mode 100644 index 000000000..7ecdfa8b7 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ev4prof.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev4prof.c" + diff --git a/private/ntos/nthals/halavant/alpha/fwreturn.c b/private/ntos/nthals/halavant/alpha/fwreturn.c new file mode 100644 index 000000000..65ae88cb8 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/fwreturn.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\fwreturn.c" + diff --git a/private/ntos/nthals/halavant/alpha/haldebug.c b/private/ntos/nthals/halavant/alpha/haldebug.c new file mode 100644 index 000000000..ce91863ec --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/haldebug.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\haldebug.c" + diff --git a/private/ntos/nthals/halavant/alpha/halpal.s b/private/ntos/nthals/halavant/alpha/halpal.s new file mode 100644 index 000000000..fc89f8370 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/halpal.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\halpal.s" + diff --git a/private/ntos/nthals/halavant/alpha/idle.s b/private/ntos/nthals/halavant/alpha/idle.s new file mode 100644 index 000000000..f517bab2f --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/idle.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\idle.s" + diff --git a/private/ntos/nthals/halavant/alpha/info.c b/private/ntos/nthals/halavant/alpha/info.c new file mode 100644 index 000000000..22aef63a3 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/info.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\info.c" + diff --git a/private/ntos/nthals/halavant/alpha/inithal.c b/private/ntos/nthals/halavant/alpha/inithal.c new file mode 100644 index 000000000..a99cb9a1a --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/inithal.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\inithal.c" + diff --git a/private/ntos/nthals/halavant/alpha/intsup.s b/private/ntos/nthals/halavant/alpha/intsup.s new file mode 100644 index 000000000..a7d9f8f4f --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/intsup.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// +#include "pcrtc.h" +#include "..\halalpha\intsup.s" + diff --git a/private/ntos/nthals/halavant/alpha/ioproc.c b/private/ntos/nthals/halavant/alpha/ioproc.c new file mode 100644 index 000000000..cc65eacde --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/ioproc.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ioproc.c" + diff --git a/private/ntos/nthals/halavant/alpha/iousage.c b/private/ntos/nthals/halavant/alpha/iousage.c new file mode 100644 index 000000000..83cbfb656 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/iousage.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\iousage.c" + diff --git a/private/ntos/nthals/halavant/alpha/machdep.h b/private/ntos/nthals/halavant/alpha/machdep.h new file mode 100644 index 000000000..72294adba --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/machdep.h @@ -0,0 +1,42 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + machdep.h + +Abstract: + + This file includes the platform-dependent include files used to + build the HAL. + +Author: + + Joe Notarangelo 01-Dec-1993 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#ifndef _MACHDEP_ +#define _MACHDEP_ + +// +// Include Avanti platform-specific definitions. +// + +#include "avantdef.h" + +// +// Include scatter/gather definitions. +// + +#include "ebsgdma.h" + +#endif //_MACHDEP_ diff --git a/private/ntos/nthals/halavant/alpha/memory.c b/private/ntos/nthals/halavant/alpha/memory.c new file mode 100644 index 000000000..76b1eb7df --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/memory.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\memory.c" + diff --git a/private/ntos/nthals/halavant/alpha/nvram.c b/private/ntos/nthals/halavant/alpha/nvram.c new file mode 100644 index 000000000..7fb21c1ea --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/nvram.c @@ -0,0 +1,279 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + xxnvram.c + +Abstract: + + This module implements the device-specific routines necessary to + Read and Write the Non Volatile RAM containing the system environment + variables. The routines implemented here are: + + HalpReadNVRamBuffer() - copy data from NVRAM into memory + HalpWriteNVRamBuffer() - write memory data to NVRAM + HalpCopyNVRamBuffer() - move data within the NVRAM + +Author: + + Steve Brooks 5-Oct 93 + + +Revision History: + + + Wim Colgate 20-Dec-93 + + This module has been changed to reflect Avanti's notion of FLASH BUS. + Basically, the offset in the 8K flash buffer is plave into the CMOS + port address, and the data in the CMOS data adress. + +--*/ + + +#include "halp.h" + +#include "arccodes.h" + +// +// Routine prototypes. +// + +ARC_STATUS +HalpReadNVRamBuffer ( + OUT PCHAR DataPtr, + IN PCHAR NvRamPtr, + IN ULONG Length + ); + +ARC_STATUS +HalpWriteNVRamBuffer ( + IN PCHAR NvRamPtr, + IN PCHAR DataPtr, + IN ULONG Length + ); + +ARC_STATUS +HalpCopyNVRamBuffer ( + IN PCHAR NvDestPtr, + IN PCHAR NvSrcPtr, + IN ULONG Length + ); + + +#define CMOS_ADDRESS_PORT HAL_MAKE_QVA( 0x100000000 ) +#define CMOS_DATA_PORT HAL_MAKE_QVA( 0x100100000 ) + +#define CMOS_ADDR_SHIFT 8 + +#define CMOS_WRITE_HARBINGER (1 << 31) + +#define NVRAM_8K_BASE 0x100000 + +#define BANKSET8_CONFIGURATION_REGISTER HAL_MAKE_QVA( 0x180000B00 ) +#define BANKSET8_ENABLE 0x1 + + +static UCHAR +HalpReadCMOSByte( ULONG ByteOffset ) +{ + UCHAR inChar; + ULONG Address; + + // + // Output the offset to the index register. + // + + Address = (ULONG)( (ByteOffset | NVRAM_8K_BASE) << CMOS_ADDR_SHIFT ); + WRITE_EPIC_REGISTER(CMOS_ADDRESS_PORT, Address); + + // + // Now read the data register: + // + + inChar = (UCHAR)READ_EPIC_REGISTER( CMOS_DATA_PORT) & 0xff; + + return inChar; +} + +static VOID +HalpWriteCMOSByte( ULONG ByteOffset, UCHAR Byte ) +{ + ULONG Address; + + // + // Output the offset to the index register. + // + + Address = (ULONG)( (ByteOffset | NVRAM_8K_BASE) << CMOS_ADDR_SHIFT ); + WRITE_EPIC_REGISTER( CMOS_ADDRESS_PORT, CMOS_WRITE_HARBINGER | Address ); + + // + // Now output the data to the data port. + // + + WRITE_EPIC_REGISTER( CMOS_DATA_PORT, (ULONG) Byte) ; +} + +// +// +// + +ARC_STATUS HalpReadNVRamBuffer ( + OUT PCHAR DataPtr, + IN PCHAR NvRamPtr, + IN ULONG Length ) + +/*++ + +Routine Description: + + This routine Reads data from the NVRam into main memory + +Arguments: + + DataPtr - Pointer to memory location to receive data + NvRamPtr - Offset in the CMOS area + Length - Number of bytes of data to transfer + +Return Value: + + ESUCCESS if the operation succeeds. + +--*/ +{ + + ULONG CsrMask; + + // + // Enable Bankset 8 + // + + CsrMask = READ_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER ); + WRITE_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER, + CsrMask | BANKSET8_ENABLE ); + + while ( Length -- ) { + *DataPtr = HalpReadCMOSByte( (ULONG)NvRamPtr ); + NvRamPtr++; + DataPtr++; + } + + // + // Disable Bankset 8 (Restore original state) + // + + WRITE_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER, CsrMask ); + + return(ESUCCESS); +} + +// +// +// +ARC_STATUS HalpWriteNVRamBuffer ( + IN PCHAR NvRamPtr, + IN PCHAR DataPtr, + IN ULONG Length ) + +/*++ + +Routine Description: + + This routine Writes data from memory into the NVRam + +Arguments: + + NvRamPtr - Pointer (qva) to NVRam location to write data into + DataPtr - Pointer to memory location of data to be written + Length - Number of bytes of data to transfer + +Return Value: + + ESUCCESS if the operation succeeds. + +--*/ +{ + ULONG CsrMask; + + // + // Enable Bankset 8 + // + + CsrMask = READ_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER ); + WRITE_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER, + CsrMask | BANKSET8_ENABLE ); + + while ( Length -- ) { + HalpWriteCMOSByte((ULONG)NvRamPtr, *DataPtr); + NvRamPtr ++; + DataPtr ++; + } + + // + // Disable Bankset 8 (Restore original state) + // + + WRITE_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER, CsrMask ); + + return(ESUCCESS); +} + +// +// +// +ARC_STATUS HalpCopyNVRamBuffer ( + IN PCHAR NvDestPtr, + IN PCHAR NvSrcPtr, + IN ULONG Length ) +/*++ + +Routine Description: + + This routine copies data between two locations within the NVRam. It is + the callers responsibility to assure that the destination region does not + overlap the src region i.e. if the regions overlap, NvSrcPtr > NvDestPtr. + +Arguments: + + NvDestPtr - Byte offset into CMOS area for destination + NvSrcPtr - Byte offset into CMOS area for source + Length - Number of bytes of data to transfer + +Return Value: + + ESUCCESS if the operation succeeds. + +--*/ + +{ + UCHAR tmpChar; + + ULONG CsrMask; + + // + // Enable Bankset 8 + // + + CsrMask = READ_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER ); + WRITE_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER, + CsrMask | BANKSET8_ENABLE ); + + while ( Length -- ) + { + tmpChar = HalpReadCMOSByte((ULONG)NvSrcPtr); + HalpWriteCMOSByte((ULONG)NvDestPtr, tmpChar); + NvSrcPtr ++; + NvDestPtr ++; + } + + // + // Disable Bankset 8 (Restore original state) + // + + WRITE_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER, CsrMask ); + + return(ESUCCESS); +} diff --git a/private/ntos/nthals/halavant/alpha/pcibus.c b/private/ntos/nthals/halavant/alpha/pcibus.c new file mode 100644 index 000000000..e9307c1e9 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/pcibus.c @@ -0,0 +1,117 @@ +/*++ + + +Copyright (c) 1993 Microsoft Corporationn, Digital Equipment Corporation + +Module Name: + + pcibus.c + +Abstract: + + Platform-specific PCI bus routines + +Author: + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#include "halp.h" +#include "pci.h" +#include "pcip.h" +#include "machdep.h" + +// +// This references a boolean variable that identifies the APECS revision. +// + +extern BOOLEAN ApecsPass2; + +extern ULONG PCIMaxBus; + + + +PCI_CONFIGURATION_TYPES +HalpPCIConfigCycleType( + IN PBUS_HANDLER BusHandler + ) +{ + if (BusHandler->BusNumber == 0) { + return PciConfigType0; + } else { + return PciConfigType1; + } +} + + +VOID +HalpPCIConfigAddr ( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + PPCI_CFG_CYCLE_BITS pPciAddr + ) +{ + PCI_CONFIGURATION_TYPES ConfigType; + + ConfigType = HalpPCIConfigCycleType(BusHandler); + + if (ConfigType == PciConfigType0) + { + // + // Initialize PciAddr for a type 0 configuration cycle + // + // Device number is mapped to address bits 11:24, which, in APECS + // pass 1, are wired to IDSEL pins. In pass 2, the format of a type + // 0 cycle is the same as the format of a type 1. Note that + // HalpValidPCISlot has already done bounds checking on DeviceNumber. + // + // PciAddr can be intialized for different bus numbers + // with distinct configuration spaces here. + // + + pPciAddr->u.AsULONG = (ULONG) APECS_PCI_CONFIG_BASE_QVA; +#if HALDBG + DbgPrint("HalpPCIConfigAddr: ApecsPass2 is %x\n", ApecsPass2); +#endif // DBG + if (ApecsPass2) { + pPciAddr->u.AsULONG += ( (Slot.u.bits.DeviceNumber) << 11 ); + } else { + pPciAddr->u.AsULONG += ( 1 << (Slot.u.bits.DeviceNumber + 11) ); + } + pPciAddr->u.bits0.FunctionNumber = Slot.u.bits.FunctionNumber; + pPciAddr->u.bits0.Reserved1 = PciConfigType0; + +#if HALDBG + DbgPrint("HalpPCIConfigAddr: Type 0 PCI Config Access @ %x\n", pPciAddr->u.AsULONG); +#endif // DBG + + } + else + { + // + // Initialize PciAddr for a type 1 configuration cycle + // + // + + pPciAddr->u.AsULONG = (ULONG) APECS_PCI_CONFIG_BASE_QVA; + pPciAddr->u.bits1.BusNumber = BusHandler->BusNumber; + pPciAddr->u.bits1.FunctionNumber = Slot.u.bits.FunctionNumber; + pPciAddr->u.bits1.DeviceNumber = Slot.u.bits.DeviceNumber; + pPciAddr->u.bits1.Reserved1 = PciConfigType1; + +#if HALDBG + DbgPrint("Type 1 PCI Config Access @ %x\n", pPciAddr->u.AsULONG); +#endif // DBG + + } + + return; +} + + diff --git a/private/ntos/nthals/halavant/alpha/pcisio.c b/private/ntos/nthals/halavant/alpha/pcisio.c new file mode 100644 index 000000000..cf5f0f462 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/pcisio.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcisio.c" + diff --git a/private/ntos/nthals/halavant/alpha/pcisup.c b/private/ntos/nthals/halavant/alpha/pcisup.c new file mode 100644 index 000000000..360919f42 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/pcisup.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcisup.c" + diff --git a/private/ntos/nthals/halavant/alpha/pcrtc.c b/private/ntos/nthals/halavant/alpha/pcrtc.c new file mode 100644 index 000000000..2e57b87d6 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/pcrtc.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcrtc.c" + diff --git a/private/ntos/nthals/halavant/alpha/pcserial.c b/private/ntos/nthals/halavant/alpha/pcserial.c new file mode 100644 index 000000000..a2f159c48 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/pcserial.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcserial.c" + diff --git a/private/ntos/nthals/halavant/alpha/pcspeakr.c b/private/ntos/nthals/halavant/alpha/pcspeakr.c new file mode 100644 index 000000000..807b6f324 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/pcspeakr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcspeakr.c" + diff --git a/private/ntos/nthals/halavant/alpha/perfcntr.c b/private/ntos/nthals/halavant/alpha/perfcntr.c new file mode 100644 index 000000000..6c0a8f892 --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/perfcntr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\perfcntr.c" + diff --git a/private/ntos/nthals/halavant/alpha/pintolin.h b/private/ntos/nthals/halavant/alpha/pintolin.h new file mode 100644 index 000000000..5723d3fbd --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/pintolin.h @@ -0,0 +1,194 @@ +/*++ + +Copyright (c) 1993 Microsoft Corporation +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + pintolin.h + +Abstract: + + This file includes the platform-dependent Pin To Line Tables + +Author: + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +// +// These tables represent the mapping from slot number and interrupt pin +// into a PCI Interrupt Vector. +// On Mustang and EB66, the interrupt vector is Interrupt Request Register bit +// representing that interrupt + 1. +// On EB66, the value also represents the Interrupt Mask Register Bit, +// since it is identical to the Interrupt Read Register. On Mustang, +// the Interrupt Mask Register only allows masking of all interrupts +// from the two plug-in slots. +// +// Formally, these mappings can be expressed as: +// +// PCIPinToLine: +// SlotNumber.DeviceNumber x InterruptPin -> InterruptLine +// +// LineToVector: +// InterruptLine -> InterruptVector +// +// VectorToIRRBit: +// InterruptVector -> InterruptRequestRegisterBit +// +// VectorToIMRBit: +// InterruptVector -> InterruptMaskRegisterBit +// +// SlotNumberToIDSEL: +// SlotNumber.DeviceNumber -> IDSEL +// +// subject to following invariants (predicates must always be true): +// +// Slot.DeviceNumber in {0,...,15} +// +// InterruptPin in {1, 2, 3, 4} +// +// InterruptRequestRegisterBit in {0,...,15} +// +// InterruptMaskRegisterBit in {0,...,15} +// +// PCIPinToLine(SlotNumber.DeviceNumber, InterruptPin) = +// PCIPinToLineTable[SlotNumber.DeviceNumber, InterruptPin] +// (Table-lookup function initialized below) +// +// LineToVector(InterruptLine) = PCI_VECTORS + InterruptLine +// +// VectorToIRRBit(InterruptVector) = InterruptVector - 1 +// +// VectorToIMRBit(InterruptVector) [see below] +// +// SlotNumberToIDSEL(SlotNumber.DeviceNumber) = (1 << (Slot.DeviceNumber+11)) +// +// where: +// +// SlotNumber.DeviceNumber: +// Alpha AXP Platforms receive interrupts on local PCI buses only, which +// are limited to 16 devices (PCI AD[11]-AD[26]). (We loose AD[17]-AD[31] +// since PCI Config space is a sparse space, requiring a five-bit shift.) +// +// InterruptPin: +// Each virtual slot has up to four interrupt pins INTA#, INTB#, INTC#, INTD#, +// as per the PCI Spec. V2.0, Section 2.2.6. (FYI, only multifunction devices +// use INTB#, INTC#, INTD#.) +// +// PCI configuration space indicates which interrupt pin a device will use +// in the InterruptPin register, which has the values: +// +// INTA# = 1, INTB#=2, INTC#=3, INTD# = 4 +// +// Note that there may be up to 8 functions/device on a PCI multifunction +// device plugged into the option slots, e.g., Slot #0. +// Each function has its own PCI configuration space, addressed +// by the SlotNumber.FunctionNumber field, and will identify which +// interrput pin of the four it will use in its own InterruptPin register. +// +// If the option is a PCI-PCI bridge, interrupts across the bridge will +// somehow be combined to appear on some combination of the four +// interrupt pins that the bridge plugs into. +// +// InterruptLine: +// This PCI Configuration register, unlike x86 PC's, is maintained by +// software and represents offset into PCI interrupt vectors. +// Whenever HalGetBusData or HalGetBusDataByOffset is called, +// HalpPCIPinToLine() computes the correct InterruptLine register value +// by using the HalpPCIPinToLineTable mapping. +// +// InterruptRequestRegisterBit: +// 0xff is used to mark an invalid IRR bit, hence an invalid request +// for a vector. Also, note that the 16 bits of the EB66 IRR must +// be access as two 8-bit reads. +// +// InterruptMaskRegisterBit: +// On EB66, the PinToLine table may also be find the to write the +// InterruptMaskRegister. Formally, we can express this invariant as +// +// VectorToIMRBit(InterrruptVector) = InterruptVector - 1 +// +// On Mustang, the table is useless. The InterruptMaskRegister has +// only two bits the completely mask all interrupts from either +// Slot #0 or Slot#1 (PCI AD[17] and AD[18]): +// +// InterruptVector in {3,4,5,6} then VectorToIMRBit(InterruptVector) = 0 +// InterruptVector in {7,8,9,10} then VectorToIMRBit(InterruptVector) = 1 +// +// IDSEL: +// For accessing PCI configuration space on a local PCI bus (as opposed +// to over a PCI-PCI bridge), type 0 configuration cycles must be generated. +// In this case, the IDSEL pin of the device to be accessed is tied to one +// of the PCI Address lines AD[11] - AD[26]. (The function field in the +// PCI address is used should we be accessing a multifunction device.) +// Anyway, virtual slot 0 represents the device with IDSEL = AD[11], and +// so on. +// + +// +// Interrupt Vector Table Mapping for EB66 +// +// You can limit init table to MAX_PCI_LOCAL_DEVICES entries. +// The highest virtual slot between EB66 and Mustang is 9, so +// MAX_PCI_LOCAL_DEVICE is defined as 9 in the platform dependent +// header file (MUSTDEF.H). HalpValidPCISlot assures us that +// we won't ever try to set an InterruptLine register of a slot +// greater than Virtual slot 9 = PCI_AD[20]. +// + +ULONG *HalpPCIPinToLineTable; + +// +// Interrupt Vector Table Mapping for Avanti +// +// Avanti PCI interrupts are mapped to ISA IRQs in the table below. +// +// Limit init table to 14 entries, which is the +// MAX_PCI_LOCAL_DEVICES_AVANTI. +// We won't ever try to set an InterruptLine register of a slot +// greater than Virtual slot 13 = PCI_AD[24]. +// + +ULONG AvantiPCIPinToLineTable[][4]= +{ + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 0 = PCI_AD[11] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 1 = PCI_AD[12] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 2 = PCI_AD[13] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 3 = PCI_AD[14] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 4 = PCI_AD[15] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 5 = PCI_AD[16] + { 0xb, 0xff, 0xff, 0xff }, // Virtual Slot 6 = PCI_AD[17] SCSI + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 7 = PCI_AD[18] SIO + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 8 = PCI_AD[19] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 9 = PCI_AD[20] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 10 = PCI_AD[21] + { 0xa, 0x9, 0xf, 0xa }, // Virtual Slot 11 = PCI_AD[22] Slot #0 + { 0xf, 0xa, 0x9, 0xf }, // Virtual Slot 12 = PCI_AD[23] Slot #1 + { 0x9, 0xf, 0xa, 0x9 } // Virtual Slot 13 = PCI_AD[24] Slot #2 +}; + +ULONG AvantiPCIPinToLineTableP1[][4]= +{ + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 0 = PCI_AD[11] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 1 = PCI_AD[12] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 2 = PCI_AD[13] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 3 = PCI_AD[14] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 4 = PCI_AD[15] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 5 = PCI_AD[16] + { 0xb, 0xff, 0xff, 0xff }, // Virtual Slot 6 = PCI_AD[17] SCSI + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 7 = PCI_AD[18] SIO + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 8 = PCI_AD[19] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 9 = PCI_AD[20] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 10 = PCI_AD[21] + { 0x9, 0xf, 0xa, 0x9 }, // Virtual Slot 13 = PCI_AD[24] Slot #0 + { 0xa, 0x9, 0xf, 0xa }, // Virtual Slot 11 = PCI_AD[22] Slot #1 + { 0xf, 0xa, 0x9, 0xf } // Virtual Slot 12 = PCI_AD[23] Slot #2 +}; diff --git a/private/ntos/nthals/halavant/alpha/vga.c b/private/ntos/nthals/halavant/alpha/vga.c new file mode 100644 index 000000000..764c585af --- /dev/null +++ b/private/ntos/nthals/halavant/alpha/vga.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\vga.c" + diff --git a/private/ntos/nthals/halavant/drivesup.c b/private/ntos/nthals/halavant/drivesup.c new file mode 100644 index 000000000..38259e5f4 --- /dev/null +++ b/private/ntos/nthals/halavant/drivesup.c @@ -0,0 +1,7 @@ +// +// This file simply includes the common sources from the current HAL +// directory. When the structure is finally changed, the real file should +// be in this directory. +// + +#include "..\drivesup.c" diff --git a/private/ntos/nthals/halavant/hal.rc b/private/ntos/nthals/halavant/hal.rc new file mode 100644 index 000000000..3cba4ad89 --- /dev/null +++ b/private/ntos/nthals/halavant/hal.rc @@ -0,0 +1,11 @@ +#include <windows.h> + +#include <ntverp.h> + +#define VER_FILETYPE VFT_DLL +#define VER_FILESUBTYPE VFT2_UNKNOWN +#define VER_FILEDESCRIPTION_STR "Hardware Abstraction Layer DLL" +#define VER_INTERNALNAME_STR "hal.dll" + +#include "common.ver" + diff --git a/private/ntos/nthals/halavant/hal.src b/private/ntos/nthals/halavant/hal.src new file mode 100644 index 000000000..da778bb9d --- /dev/null +++ b/private/ntos/nthals/halavant/hal.src @@ -0,0 +1,7 @@ +// +// This file simply includes the common sources from the current HAL +// directory. When the structure is finally changed, the real file should +// be in this directory. +// + +#include "..\hal.src" diff --git a/private/ntos/nthals/halavant/makefile b/private/ntos/nthals/halavant/makefile new file mode 100644 index 000000000..6ee4f43fa --- /dev/null +++ b/private/ntos/nthals/halavant/makefile @@ -0,0 +1,6 @@ +# +# DO NOT EDIT THIS FILE!!! Edit .\sources. if you want to add a new source +# file to this component. This file merely indirects to the real make file +# that is shared by all the components of NT OS/2 +# +!INCLUDE $(NTMAKEENV)\makefile.def diff --git a/private/ntos/nthals/halavant/makefile.inc b/private/ntos/nthals/halavant/makefile.inc new file mode 100644 index 000000000..0f5a8b41c --- /dev/null +++ b/private/ntos/nthals/halavant/makefile.inc @@ -0,0 +1,5 @@ +obj\alpha\hal.def: hal.src + rcpp -P -f hal.src -DALPHA=1 $(C_DEFINES) -g obj\alpha\hal.def + +$(TARGETPATH)\alpha\hal.lib: $(TARGETPATH)\alpha\halavant.lib + copy $** $@ diff --git a/private/ntos/nthals/halavant/sources b/private/ntos/nthals/halavant/sources new file mode 100644 index 000000000..0afb762e0 --- /dev/null +++ b/private/ntos/nthals/halavant/sources @@ -0,0 +1,103 @@ +!IF 0 + +Copyright (c) 1993 Microsoft Corporation + +Module Name: + + sources. + +Abstract: + + This file specifies the target component being built and the list of + sources files needed to build that component. Also specifies optional + compiler switches and libraries that are unique for the component being + built. + + +Author: + + David N. Cutler (davec) 12-Apr-1993 + +NOTE: Commented description of this file is in \nt\bak\bin\sources.tpl + +!ENDIF + +MAJORCOMP=ntos +MINORCOMP=hal + +TARGETNAME=halavant +TARGETPATH=$(BASEDIR)\public\sdk\lib + +ALPHA_WARNING_LEVEL=-W3 -WX +C_DEFINES=-DEV4 -DAPECS + +NT_UP=1 + +!IF $(ALPHA) + +TARGETTYPE=HAL + +!ELSE + +TARGETTYPE=DRIVER + +!ENDIF + +INCLUDES=..\..\inc;..\..\ke;..\..\io;..\..\fw\alpha;..\..\fastfat;..\halalpha + +SOURCES= + +ALPHA_SOURCES=hal.rc \ + bushnd.c \ + drivesup.c \ + alpha\allstart.c \ + alpha\alphaio.s \ + alpha\apecs.c \ + alpha\apecserr.c \ + alpha\apecsio.s \ + alpha\adjust.c \ + alpha\bios.c \ + alpha\cache.c \ + alpha\ebsgdma.c \ + alpha\eisasup.c \ + alpha\environ.c \ + alpha\ev4cache.c \ + alpha\ev4int.c \ + alpha\ev4ints.s \ + alpha\ev4mchk.c \ + alpha\ev4mem.s \ + alpha\ev4prof.c \ + alpha\fwreturn.c \ + alpha\haldebug.c \ + alpha\halpal.s \ + alpha\idle.s \ + alpha\info.c \ + alpha\inithal.c \ + alpha\intsup.s \ + alpha\ioproc.c \ + alpha\iousage.c \ + alpha\memory.c \ + alpha\pcisio.c \ + alpha\pcisup.c \ + alpha\pcrtc.c \ + alpha\pcserial.c \ + alpha\pcspeakr.c \ + alpha\perfcntr.c \ + alpha\vga.c \ + alpha\addrsup.c \ + alpha\busdata.c \ + alpha\ebinitnt.c \ + alpha\ebintsup.c \ + alpha\ebmapio.c \ + alpha\ebsysint.c \ + alpha\nvram.c \ + alpha\pcibus.c + +DLLDEF=obj\*\hal.def + +!IF $(ALPHA) + +NTTARGETFILES=$(TARGETPATH)\alpha\hal.lib \ + $(TARGETPATH)\alpha\hal.dll + +!ENDIF |