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| author | Adam <you@example.com> | 2020-05-17 05:51:50 +0200 |
|---|---|---|
| committer | Adam <you@example.com> | 2020-05-17 05:51:50 +0200 |
| commit | e611b132f9b8abe35b362e5870b74bce94a1e58e (patch) | |
| tree | a5781d2ec0e085eeca33cf350cf878f2efea6fe5 /private/ntos/nthals/hallx3/alpha | |
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Diffstat (limited to 'private/ntos/nthals/hallx3/alpha')
54 files changed, 4790 insertions, 0 deletions
diff --git a/private/ntos/nthals/hallx3/alpha/addrsup.c b/private/ntos/nthals/hallx3/alpha/addrsup.c new file mode 100644 index 000000000..5c6365c6e --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/addrsup.c @@ -0,0 +1,587 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + addrsup.c + +Abstract: + + This module contains the platform dependent code to create bus addreses + and QVAs for the Avanti system. + +Author: + + Joe Notarangelo 22-Oct-1993 + +Environment: + + Kernel mode + +Revision History: + + Eric Rehm (Digital) 03-Jan-1994 + Added PCIBus(0) and dense space support to all routines. + +--*/ + +#include "halp.h" +#include "eisa.h" +#include "lx3.h" + +typedef PVOID QUASI_VIRTUAL_ADDRESS; + +QUASI_VIRTUAL_ADDRESS +HalCreateQva( + IN PHYSICAL_ADDRESS PA, + IN PVOID VA + ); + + +BOOLEAN +HalpTranslateSystemBusAddress( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN PHYSICAL_ADDRESS BusAddress, + IN OUT PULONG AddressSpace, + OUT PPHYSICAL_ADDRESS TranslatedAddress + ) + + +/*++ + +Routine Description: + + This function returns the system physical address for a specified I/O bus + address. The return value is suitable for use in a subsequent call to + MmMapIoSpace. + +Arguments: + + BusHandler - Registered BUSHANDLER for the target configuration space + Supplies the bus handler (bus no, interface type). + + RootHandler - Registered BUSHANDLER for the orginating + HalTranslateBusAddress request. + + BusAddress - Supplies the bus relative address. + + AddressSpace - Supplies the address space number for the device: 0 for + memory and 1 for I/O space. If the desired access mode is user mode, + then bit 1 must be TRUE. + + TranslatedAddress - Supplies a pointer to return the translated address + + +Notes: + + This is a variation of what began in the MIPS code. The intel code often + assumes that if an address is in I/O space, the bottom 32 bits of the + physical address can be used "like" a virtual address, and are returned + to the user. This doesn't work on MIPs machines where physical + addresses can be larger than 32 bits. + + Since we are using superpage addresses for I/O on Alpha, we can do + almost what is done on intel. If AddressSpace is equal to 0 or 1, then + we assume the user is doing kernel I/O and we call + HalCreateQva to build a Quasi Virtual Address and return + that to the caller. We then set AddressSpace to a 1, so that the caller + will not call MmMapIoSpace. The Caller will use the low 32 bits of the + physical address we return as the VA. (Which we built a QVA in). + If the caller wants to access EISA I/O or Memory through user mode, then + the caller must set bit 1 in AddressSpace to a 1 (AddressSpace=2 or 3, + depending on whether EISA I/O or Memory), then the caller is returned the + 34 bit Physical address. The caller will then call MmMapIoSpace, or + ZwMapViewOfSection which in turn calls HalCreateQva to build a QVA out + of a VA mapped through the page tables. + + **** Note **** + + The QVA in user mode can only be used via the user-mode access macros. + + + +Return Value: + + A return value of TRUE indicates that a system physical address + corresponding to the supplied bus relative address and bus address + number has been returned in TranslatedAddress. + + A return value of FALSE occurs if the translation for the address was + not possible + +--*/ + +{ + INTERFACE_TYPE InterfaceType = BusHandler->InterfaceType; + ULONG BusNumber = BusHandler->BusNumber; + + PVOID va = 0; // note, this is used for a placeholder + + // + // The only buses available on Avanti are an ISA bus and a PCI bus. + // We support any translations for EISA devices as well, though + // if they are true EISA devices they won't even be able to plug into + // the connectors! + // + + if (InterfaceType != Isa && + InterfaceType != Eisa && + InterfaceType != PCIBus) { + + // + // Not on this system return nothing. + // + + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + } + + // + // Determine the address based on whether the bus address is in I/O space + // or bus memory space. + // + + switch ( (ADDRESS_SPACE_TYPE)(*AddressSpace) ) { + + case BusMemory: { + + // + // The address is in PCI memory space, kernel mode. + // + + switch( InterfaceType ) { + + case Isa: { + + // + // Can't go above 16MB (24 Bits) for Isa Buses + // + if( BusAddress.LowPart >= __16MB ){ + + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + + } + + break; + + } // case Isa + + case PCIBus: { + + if ( BusAddress.LowPart > PCI_MAX_DENSE_MEMORY_ADDRESS ) { + + // + // Unsupported dense PCI bus address. + // +#if HALDBG + DbgPrint ("Unsupported PCI address %x:%x\n", + BusAddress.HighPart, + BusAddress.LowPart); +#endif + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + } + else if( BusAddress.LowPart >= PCI_MIN_DENSE_MEMORY_ADDRESS && + BusAddress.LowPart <= PCI_MAX_DENSE_MEMORY_ADDRESS ) { + +#if HALDBG + DbgPrint ("Translating PCI kernel dense address %x:%x\n", + BusAddress.HighPart, + BusAddress.LowPart); +#endif + // + // Bus Address is in dense PCI memory space + // + + // + // QVA, as such, is simply the PCI bus address + // + + TranslatedAddress->LowPart = BusAddress.LowPart; + + // + // clear high longword for QVA + // + + TranslatedAddress->HighPart = 0; + + // + // dont let the user call MmMapIoSpace + // + + *AddressSpace = 1; + + return (TRUE); + + + } + + // + // Bus Address is in sparse PCI memory space + // + + +#if HALDBG + DbgPrint ("Translating PCI kernel sparse address %x:%x\n", + BusAddress.HighPart, + BusAddress.LowPart); +#endif + + break; + } // case PCIBus + + case Eisa: { + break; + } // case Eisa + + } // switch( InterfaceType ) + + // + // Start with the base physical address and add the + // bus address by converting it to the physical address. + // + + TranslatedAddress->QuadPart = APECS_PCI_MEMORY_BASE_PHYSICAL; + TranslatedAddress->QuadPart += ((ULONGLONG)BusAddress.LowPart << IO_BIT_SHIFT); + + // + // Now call HalCreateQva. This will create a QVA + // that we'll return to the caller. Then we will implicitly set + // AddressSpace to a 1. The caller then will not call MmMapIoSpace + // and will use the address we return as a VA. + // + + TranslatedAddress->LowPart = + (ULONG) HalCreateQva( *TranslatedAddress, va); + + // + // clear high longword for QVA + // + + TranslatedAddress->HighPart = 0; + + // + // don't let the user call MmMapIoSpace + // + + *AddressSpace = 1; + + return(TRUE); + + } // case BusMemory + + + case BusIo: { + + // + // The address is in PCI I/O space, kernel mode. + // + + switch( InterfaceType ) { + + case Isa: { + // + // Can't go above 64KB (16 Bits) for Isa Buses + // + if( BusAddress.LowPart >= __64K ){ + + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + + } + break; + } // case Isa + + case PCIBus: { + + // + // PCI IO space is always below 16MB (24 Bits) BusAddress + // If the address cannot be mapped, just return FALSE. + // + // IMPORTANT: For now we have set HAXR2 to 0(see ebinitnt.c) + // + if( BusAddress.LowPart >= __16MB ){ + + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + + } + // + // if the BusAddress.LowPart is > 64K then we use the HAXR2 + // register. + // + break; + } // case PCIBus + + case Eisa: { + break; + } // case Eisa + + } // switch( InterfaceType ) + + + // + // Start with the base physical address and add the + // bus address by converting it to the physical address. + // + + TranslatedAddress->QuadPart = APECS_PCI_IO_BASE_PHYSICAL; + TranslatedAddress->QuadPart += ((ULONGLONG)BusAddress.LowPart << IO_BIT_SHIFT); + + // + // Now call HalCreateQva. This will create a QVA + // that we'll return to the caller. Then we will implicitly set + // AddressSpace to a 1. The caller then will not call MmMapIoSpace + // and will use the address we return as a VA. + + TranslatedAddress->LowPart = (ULONG) HalCreateQva( *TranslatedAddress, + va); + + TranslatedAddress->HighPart = 0; // clear high longword for QVA + + *AddressSpace = 1; // Make sure user doesn't call + // MmMapIoSpace. + + return(TRUE); + + } // case BusIo + + case UserBusMemory: { + + // + // The address is in PCI memory space, user mode. + // + + // + // Start with the base physical address and add the + // bus address by converting it to the physical address. + // + + TranslatedAddress->QuadPart = APECS_PCI_MEMORY_BASE_PHYSICAL; + TranslatedAddress->QuadPart += ((ULONGLONG)BusAddress.LowPart << IO_BIT_SHIFT); + + *AddressSpace = 0; // Let the user call MmMapIoSpace + + return(TRUE); + + } + + case UserBusIo: { + + // + // The address is in PCI I/O space, user mode. + // + + // + // Start with the base physical address and add the + // bus address by converting it to the physical address. + // + + TranslatedAddress->QuadPart = APECS_PCI_IO_BASE_PHYSICAL; + TranslatedAddress->QuadPart += ((ULONGLONG)BusAddress.LowPart << IO_BIT_SHIFT); + + *AddressSpace = 0; // Make sure user can call + // MmMapIoSpace. + + return(TRUE); + + } + + + case KernelPciDenseMemory: + case UserPciDenseMemory: + { + + // + // The address is in PCI memory space, user mode. + // Note that ISA and EISA buses can also request this space + // + + // + // Start with the base physical address and add the + // bus address by converting it to the physical address. + // + + TranslatedAddress->QuadPart = APECS_PCI_DENSE_BASE_PHYSICAL; + TranslatedAddress->QuadPart += BusAddress.LowPart; + + *AddressSpace = 0; // Let the user call MmMapIoSpace + + return(TRUE); + + } + + default: { + + // + // Unsupported address space. + + *AddressSpace = 0; + TranslatedAddress->LowPart = 0; + return(FALSE); + + } + + + } +} + +PVOID +HalCreateQva( + IN PHYSICAL_ADDRESS PA, + IN PVOID VA + ) + +/*++ + +Routine Description: + + This function is called two ways. First, from HalTranslateBusAddress, + if the caller is going to run in kernel mode and use superpages. + The second way is if the user is going to access in user mode. + MmMapIoSpace or ZwViewMapOfSection will call this. + + If the input parameter VA is zero, then we assume super page and build + a QUASI virtual address that is only usable by calling the hal I/O + access routines. + + if the input parameter VA is non-zero, we assume the user has either + called MmMapIoSpace or ZwMapViewOfSection and will use the user mode + access macros. + + If the PA is not a sparse I/O space address (PCI I/O, PCI Memory), + then return the VA as the QVA. + +Arguments: + + PA - the physical address generated by HalTranslateBusAddress + + VA - the virtual address returned by MmMapIoSpace + +Return Value: + + The returned value is a quasi virtual address in that it can be + added to and subtracted from, but it cannot be used to access the + bus directly. The top bits are set so that we can trap invalid + accesses in the memory management subsystem. All access should be + done through the Hal Access Routines in *ioacc.s if it was a superpage + kernel mode access. If it is usermode, then the user mode access + macros must be used. + +--*/ +{ + + PVOID qva; + + if( (PA.QuadPart >= APECS_COMANCHE_BASE_PHYSICAL) + && (PA.QuadPart < APECS_PCI_DENSE_BASE_PHYSICAL) + ) + { + + // + // The physical address is within one of the sparse I/O spaces. + // + + if (VA == 0) { + + qva = (PVOID)(PA.QuadPart >> IO_BIT_SHIFT); + + } else { + + qva = (PVOID)((ULONG)VA >> IO_BIT_SHIFT); + } + + qva = (PVOID)((ULONG)qva | QVA_ENABLE); + + return(qva); + } + + // + // It is not a sparse I/O space address, return the VA as the QVA + // + + return(VA); + +} + +PVOID +HalDereferenceQva( + PVOID Qva, + INTERFACE_TYPE InterfaceType, + ULONG BusNumber + ) +/*++ + +Routine Description: + + This function performs the inverse of the HalCreateQva for I/O addresses + that are memory-mapped (i.e. the quasi-virtual address was created from + a virtual address rather than a physical address). + +Arguments: + + Qva - Supplies the quasi-virtual address to be converted back to a + virtual address. + + InterfaceType - Supplies the interface type of the bus to which the + Qva pertains. + + BusNumber - Supplies the bus number of the bus to which the Qva pertains. + +Return Value: + + The Virtual Address from which the quasi-address was originally created + is returned. + +--*/ +{ + + + // + // For Avanti we have only bus types: + // + // Isa + // PCIBus + // + // We will allow Eisa as an alias for Isa. All other values not named + // above will be considered bogus. + // + + switch (InterfaceType ){ + + case Isa: + case Eisa: + case PCIBus: + + // + // Support dense space: check to see if it's really + // a sparse space QVA. + // + + if ( ((ULONG) Qva & QVA_SELECTORS) == QVA_ENABLE ) + { + return( (PVOID)( (ULONG)Qva << IO_BIT_SHIFT ) ); + } + else + { + return (Qva); + } + break; + + + default: + + return NULL; + + } + + +} diff --git a/private/ntos/nthals/hallx3/alpha/adjust.c b/private/ntos/nthals/hallx3/alpha/adjust.c new file mode 100644 index 000000000..47c267fb8 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/adjust.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\adjust.c" + diff --git a/private/ntos/nthals/hallx3/alpha/allstart.c b/private/ntos/nthals/hallx3/alpha/allstart.c new file mode 100644 index 000000000..42f70b7ca --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/allstart.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\allstart.c" + diff --git a/private/ntos/nthals/hallx3/alpha/alphaio.s b/private/ntos/nthals/hallx3/alpha/alphaio.s new file mode 100644 index 000000000..d2fe61a53 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/alphaio.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\alphaio.s" + diff --git a/private/ntos/nthals/hallx3/alpha/am29f400.c b/private/ntos/nthals/hallx3/alpha/am29f400.c new file mode 100644 index 000000000..cc5152b17 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/am29f400.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\am29f400.c" + diff --git a/private/ntos/nthals/hallx3/alpha/apecs.c b/private/ntos/nthals/hallx3/alpha/apecs.c new file mode 100644 index 000000000..06eb91348 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/apecs.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\apecs.c" + diff --git a/private/ntos/nthals/hallx3/alpha/apecserr.c b/private/ntos/nthals/hallx3/alpha/apecserr.c new file mode 100644 index 000000000..441154cc9 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/apecserr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\apecserr.c" + diff --git a/private/ntos/nthals/hallx3/alpha/apecsio.s b/private/ntos/nthals/hallx3/alpha/apecsio.s new file mode 100644 index 000000000..27bb7caa7 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/apecsio.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\apecsio.s" + diff --git a/private/ntos/nthals/hallx3/alpha/bios.c b/private/ntos/nthals/hallx3/alpha/bios.c new file mode 100644 index 000000000..3a9d3aa50 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/bios.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\bios.c" + diff --git a/private/ntos/nthals/hallx3/alpha/busdata.c b/private/ntos/nthals/hallx3/alpha/busdata.c new file mode 100644 index 000000000..cc2a153c1 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/busdata.c @@ -0,0 +1,125 @@ +/*++ + + +Copyright (c) 1989 Microsoft Corporation +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + busdata.c + +Abstract: + + This module contains get/set bus data routines. + +Author: + + Darryl E. Havens (darrylh) 11-Apr-1990 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#include "halp.h" + +// +// External Function Prototypes +// + +ULONG +HalpNoBusData ( + IN PVOID BusHandler, + IN PVOID RootHandler, + IN ULONG SlotNumber, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length + ); + +#ifdef ALLOC_PRAGMA +#pragma alloc_text(INIT,HalpRegisterInternalBusHandlers) +#endif + + +VOID +HalpRegisterInternalBusHandlers ( + VOID + ) +/*++ + +Routine Description: + + This function registers the bushandlers for buses on the system + that will always be present on the system. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + PBUS_HANDLER Bus; + + // + // Initalize BusHandler data before registering any handlers + // + + HalpInitBusHandler (); + + // + // Build the processor internal bus 0 + // + + HaliRegisterBusHandler (ProcessorInternal, // Bus Type + -1, // No config space + 0, // Bus Number + -1, // No parent bus type + 0, // No parent bus number + 0, // No extension data + NULL, // No install handler + &Bus); // Bushandler return + + Bus->GetInterruptVector = HalpGetSystemInterruptVector; + + // + // Build internal-bus 0, or system level bus + // + + HaliRegisterBusHandler (Internal, // Bus Type + -1, // No config space + 0, // Bus Number + -1, // No parent bus type + 0, // No parent bus number + 0, // No extension data + NULL, // No install handler + &Bus); // Bushandler return + + Bus->GetInterruptVector = HalpGetSystemInterruptVector; + Bus->TranslateBusAddress = HalpTranslateSystemBusAddress; + + // + // Build Isa bus #0 + // + + HaliRegisterBusHandler (Isa, // Bus Type + -1, // No config space + 0, // Internal bus #0 + Internal, // Parent bus type + 0, // Parent bus number + 0, // No extension data + NULL, // No install handler + &Bus); // Bushandler return + + Bus->GetBusData = HalpNoBusData; + Bus->AdjustResourceList = HalpAdjustIsaResourceList; + +} diff --git a/private/ntos/nthals/hallx3/alpha/cache.c b/private/ntos/nthals/hallx3/alpha/cache.c new file mode 100644 index 000000000..561528477 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/cache.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\cache.c" + diff --git a/private/ntos/nthals/hallx3/alpha/chipset.h b/private/ntos/nthals/hallx3/alpha/chipset.h new file mode 100644 index 000000000..0a72ef8cb --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/chipset.h @@ -0,0 +1 @@ +#include "apecs.h" diff --git a/private/ntos/nthals/hallx3/alpha/eisasup.c b/private/ntos/nthals/hallx3/alpha/eisasup.c new file mode 100644 index 000000000..0d46ef3e4 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/eisasup.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\eisasup.c" + diff --git a/private/ntos/nthals/hallx3/alpha/environ.c b/private/ntos/nthals/hallx3/alpha/environ.c new file mode 100644 index 000000000..75015a0a0 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/environ.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\environ.c" + diff --git a/private/ntos/nthals/hallx3/alpha/ev4cache.c b/private/ntos/nthals/hallx3/alpha/ev4cache.c new file mode 100644 index 000000000..b0cf9e3be --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/ev4cache.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev4cache.c" + diff --git a/private/ntos/nthals/hallx3/alpha/ev4int.c b/private/ntos/nthals/hallx3/alpha/ev4int.c new file mode 100644 index 000000000..8a10705d7 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/ev4int.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev4int.c" + diff --git a/private/ntos/nthals/hallx3/alpha/ev4ints.s b/private/ntos/nthals/hallx3/alpha/ev4ints.s new file mode 100644 index 000000000..6df823ab6 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/ev4ints.s @@ -0,0 +1,6 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// +#include "..\halalpha\ev4ints.s" + diff --git a/private/ntos/nthals/hallx3/alpha/ev4mchk.c b/private/ntos/nthals/hallx3/alpha/ev4mchk.c new file mode 100644 index 000000000..697087c15 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/ev4mchk.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev4mchk.c" + diff --git a/private/ntos/nthals/hallx3/alpha/ev4mem.s b/private/ntos/nthals/hallx3/alpha/ev4mem.s new file mode 100644 index 000000000..f410d09a3 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/ev4mem.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev4mem.s" + diff --git a/private/ntos/nthals/hallx3/alpha/ev4prof.c b/private/ntos/nthals/hallx3/alpha/ev4prof.c new file mode 100644 index 000000000..7ecdfa8b7 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/ev4prof.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev4prof.c" + diff --git a/private/ntos/nthals/hallx3/alpha/flash8k.c b/private/ntos/nthals/hallx3/alpha/flash8k.c new file mode 100644 index 000000000..193b2b9fc --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/flash8k.c @@ -0,0 +1,518 @@ +/*++ + +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + flash8k.c + +Abstract: + + This module implements the flash-specific, device-independent routines + necessary to Read and Write the flash ROM containing the system environment + variables. The routines implemented here are: + + HalpReadNVRamBuffer() - copy data from Flash into memory + HalpWriteNVRamBuffer() - write memory data to Flash + HalpCopyNVRamBuffer() - stubbed for compatibility with NVRAM + +Author: + + Steve Brooks 5-Oct 93 + + +Revision History: + + Wim Colgate 1-May-1995 + + Added LX3 specfic code for Bankset 8 mumbo-jumbo for the LX3 specific + 'Flash Bus'. + + +--*/ + + +#include "halp.h" +#include "pflash.h" +#include "flash8k.h" + +#include "arccodes.h" + +// +// To access the flash bus, one needs to enable the bankset 8 in +// the APECS chipset. +// + +#define BANKSET8_CONFIGURATION_REGISTER HAL_MAKE_QVA( 0x180000B00 ) +#define BANKSET8_ENABLE 0x1 + +#define STALL_VALUE 16 + +// +// This variable tells us which bank of 8K 'nvram' are we using +// The LX3 nvram is actually two separate 8K sections of the FLASH ROM. +// One living at 0x4000, the other at 0x8000. +// +// This 'base' is not a QVA as in other platforms -- rather it is a base +// index off of the FLASH ROM device (0-512K). + +extern ULONG Am29F400NVRAMBase; + +// +// Variables: +// +// PFLASH_DRIVER HalpFlashDriver +// Pointer to the device-specific flash driver. +// + +PFLASH_DRIVER HalpFlashDriver = NULL; + +// +// Flash Drivers +// +// Each platform which uses this module must define FlashDriverList as an +// array of pointers to the initialize functions of any flash drivers for +// which the flash device might be used for the environment in the system. +// + +extern PFLASH_DRIVER (*FlashDriverList[])(ULONG); + +// +// Local function prototypes. +// + +ARC_STATUS +HalpReadNVRamBuffer ( + OUT PCHAR DataPtr, + IN PCHAR NvRamOffset, + IN ULONG Length + ); + +ARC_STATUS +HalpWriteNVRamBuffer ( + IN PCHAR NvRamOffset, + IN PCHAR DataPtr, + IN ULONG Length + ); + +ARC_STATUS +HalpCopyNVRamBuffer ( + IN PCHAR NvDestPtr, + IN PCHAR NvSrcPtr, + IN ULONG Length + ); + +PFLASH_DRIVER +HalpInitializeFlashDriver( + IN ULONG NvRamOffset + ); + +#ifdef AXP_FIRMWARE + +#pragma alloc_text(DISTEXT, HalpReadNVRamBuffer ) +#pragma alloc_text(DISTEXT, HalpWriteNVRamBuffer ) +#pragma alloc_text(DISTEXT, HalpCopyNVRamBuffer ) +#pragma alloc_text(DISTEXT, HalpInitializeFlashDriver ) + +#endif + +ARC_STATUS HalpReadNVRamBuffer ( + OUT PCHAR DataPtr, + IN PCHAR NvRamOffset, + IN ULONG Length ) + +/*++ + +Routine Description: + + This routine Reads data from the NVRam into main memory + +Arguments: + + DataPtr - Pointer to memory location to receive data + NvRamOffset- NVRam offset to read data from + Length - Number of bytes of data to transfer + +Return Value: + + ESUCCESS if the operation succeeds. + ENODEV if no flash driver is loaded + E2BIG if we attempt to read beyond the end of the NVRAM location + +--*/ +{ + ULONG CsrMask; + +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("HalpReadNVRamBuffer(%08x, %08x, %d)\r\n",(ULONG)DataPtr, + NvRamOffset, Length); +#endif + + // + // If there is no flash driver, return an error. + // + + if ((HalpFlashDriver == NULL) && + ((HalpFlashDriver = + HalpInitializeFlashDriver((ULONG)NvRamOffset)) == NULL)) { + + return ENODEV; + } + + // + // Check to see if we will read beyond the bounds... + // (normalize offset - base + length) + // + + if (NvRamOffset - Am29F400NVRAMBase + Length > (PUCHAR)NVRAM1_SECTOR_SIZE) { + return E2BIG; + } + + // + // Adjust the offset by the NVRAM Base -- The NVRAM Offset is going + // to be 0-8K. The Base is where in the FLASH ROM the NVRAM is located. + // Since these routines are going to call the lower FLASH ROM routines, + // (which spans 0-512K), we need to adjust the NVRAM offset appropriately. + // + + // + // Enable Bankset 8 + // + + CsrMask = READ_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER ); + WRITE_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER, + CsrMask | BANKSET8_ENABLE ); + + // + // Read from the flash. + // + + HalpFlash8kSetReadMode(NvRamOffset); + while(Length--) { + *DataPtr = HalpFlash8kReadByte(NvRamOffset); + DataPtr++; + NvRamOffset++; + } + + // + // Disable Bankset 8 (Restore original state) + // + + WRITE_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER, CsrMask ); + + return ESUCCESS; +} + +ARC_STATUS +HalpWriteNVRamBuffer ( + IN PCHAR NvRamOffset, + IN PCHAR DataPtr, + IN ULONG Length ) + +/*++ + +Routine Description: + + This routine Writes data from memory into the NVRam + +Arguments: + + NvRamOffset- NVRam Offset to write data into + DataPtr - Pointer to memory location of data to be written + Length - Number of bytes of data to transfer + +Return Value: + + ESUCCESS if the operation succeeds. + ENODEV if no flash driver is loaded + EIO if a device error was detected + E2BIG if we attempt to write beyond the end of the NVRAM location + +--*/ +{ + ARC_STATUS ReturnStatus = ESUCCESS; + UCHAR NeedToErase = FALSE; + UCHAR Byte; + ULONG Index; + ULONG Offset; + ULONG CsrMask; + PUCHAR FlashBuffer; + + ULONG SectorSize; + ULONG SectorBase; + +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("HalpWriteNVRamBuffer(%08x, %08x, %d)\r\n", NvRamOffset, + (ULONG)DataPtr, Length); +#endif + + // + // If there is no flash driver, return an error. + // + + if ((HalpFlashDriver == NULL) && + ((HalpFlashDriver = + HalpInitializeFlashDriver((ULONG)NvRamOffset)) == NULL)) { + + return ENODEV; + } + + // + // Check to see if we will write beyond the bounds... + // (normalize offset - base + length) + // + + if (NvRamOffset - Am29F400NVRAMBase + Length > (PUCHAR)NVRAM1_SECTOR_SIZE) { + return E2BIG; + } + + // + // Enable Bankset 8 + // + + CsrMask = READ_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER ); + WRITE_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER, + CsrMask | BANKSET8_ENABLE ); + + // + // Read the whole bloody Physical NVRAM into a temporary buffer for + // comparisons + // + + SectorBase = (ULONG)HalpFlash8kSectorAlign(NvRamOffset); + SectorSize = HalpFlash8kSectorSize(SectorBase); + + FlashBuffer = ExAllocatePool(NonPagedPool, SectorSize); + if (FlashBuffer == NULL) { +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("HalpWriteNVRamBuffer: Could not allocate shadow\r\n"); +#endif + return ENOMEM; + } + + ReturnStatus = HalpReadNVRamBuffer(FlashBuffer, + (PUCHAR)SectorBase, + SectorSize); + + // + // Check to see if we can write the data as is. Since we're dealing with + // a flash ROM device, we can only program 1-->1 and 1-->0, but not 0-->1. + // + + Offset = (ULONG)NvRamOffset; + for (Index = 0; (Index < Length) && !NeedToErase; Index++, Offset++) { + + Byte = FlashBuffer[Offset - SectorBase]; + + if (!HalpFlash8kOverwriteCheck(Byte, (UCHAR)DataPtr[Index])) { + NeedToErase = TRUE; + +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("Need to erase flash because byte at %08x (%02x) ", + Offset, Byte); + DbgPrint("Cannot be written with %02x\r\n", (UCHAR)DataPtr[Index]); +#endif + + } + + } + + // + // We can either program directly, or we must erase first. + // split this path here. + // + + if (!NeedToErase) { +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("Don't need to erase -- simple overwrite\n"); +#endif + Offset = (ULONG)NvRamOffset; + for (Index = 0; Index < Length; Index++, Offset++) { + + // + // if byte is the same - don't bother writing + // + + Byte = FlashBuffer[Offset - SectorBase]; + + if (Byte != (UCHAR)DataPtr[Index]) { +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("Writing %02x at %x\n", (UCHAR)DataPtr[Index], Offset); +#endif + HalpStallExecution(STALL_VALUE); + ReturnStatus = HalpFlash8kWriteByte(Offset,DataPtr[Index]); + if (ReturnStatus != ESUCCESS) { +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("Failed to write %02x (was %02x) at %x status %x (Retrying...)\n", + (UCHAR)DataPtr[Index], Byte, Offset, ReturnStatus); +#endif + // + // Retry + // + + Index--; Offset--; + } + } + } + } else { + + // + // We need to erase the flash block in order to write some of the + // requested data. + // + + + // + // Merge our data with the existing FLASH ROM data. + // + + for(Index = 0; Index < Length; Index++) { + FlashBuffer[(ULONG)NvRamOffset - SectorBase + Index] = + DataPtr[Index]; + } + +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("Erasing sector\n"); +#endif + + // + // Erase the sector + // + + ReturnStatus = HalpFlash8kEraseSector(SectorBase); + +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("Returned from erase: %x\n", ReturnStatus); + DbgPrint("Writing %x bytes to %x\n", SectorSize, SectorBase); +#endif + + for (Index = 0; Index < SectorSize; Index++, Offset++) { + + if (FlashBuffer[Index] != HalpFlashDriver->ErasedData) { + + HalpStallExecution(STALL_VALUE); + + ReturnStatus = HalpFlash8kWriteByte(SectorBase + Index, + FlashBuffer[Index]); + if (ReturnStatus != ESUCCESS) { +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("Failed to write %02x at %x status %x (Retrying...)\n", + (UCHAR)FlashBuffer[Index], SectorBase + Index, ReturnStatus); +#endif + // + // Retry + // + + Index--; Offset--; + } + } + } + +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("\nReturned from write: %x\n", ReturnStatus); + DbgPrint("Wrote %x bytes\n", Index); +#endif + + } + + // + // Disable Bankset 8 (Restore original state) + // + + WRITE_COMANCHE_REGISTER( BANKSET8_CONFIGURATION_REGISTER, CsrMask ); + + HalpFlash8kSetReadMode(NvRamOffset); + + ExFreePool(FlashBuffer); + + return ReturnStatus; +} + +// +// +// +ARC_STATUS HalpCopyNVRamBuffer ( + IN PCHAR NvDestPtr, + IN PCHAR NvSrcPtr, + IN ULONG Length ) +/*++ + +Routine Description: + + This routine is not supported. + +Arguments: + + NvDestPtr- NVRam Offset to write data into + NvSrcPtr - NVRam Offset of data to copy + Length - Number of bytes of data to transfer + +Return Value: + + ENODEV if no flash driver is loaded + EIO if a flash driver is loaded + +--*/ + +{ +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + DbgPrint("HalpCopyNVRamBuffer()\r\n"); +#endif + + // + // If there is no flash driver, return an error. + // + if (HalpFlashDriver == NULL) { + return ENODEV; + } + + return EIO; +} + +PFLASH_DRIVER +HalpInitializeFlashDriver( + IN ULONG NvRamOffset + ) +/*++ + +Routine Description: + + This routine attempts to recognize the flash device present in the + system by calling each known flash driver's Initialize() function + with the address passed in. The Initialize() functions will each + return NULL if they do not recognize the flash device at the specified + address and a pointer to a FLASH_DRIVER structure if the device is + recognized. This routine looks until it either recognizes a flash device + or runs out of known flash devices. + +Arguments: + + NvRamOffset - an Offset within the flash device + +Return Value: + + A pointer to the FLASH_DRIVER structure of the driver which corresponds + to the flash device in the system. NULL if no known flash device was + recognized. + +--*/ +{ + PFLASH_DRIVER FlashDriver = NULL; + ULONG DriverNumber; + + for(DriverNumber=0; FlashDriverList[DriverNumber] != NULL; DriverNumber++) { + FlashDriver = FlashDriverList[DriverNumber](NvRamOffset); + if (FlashDriver != NULL) { + break; + } + } + +#if defined(ALPHA_FW_KDHOOKS) || defined(HALDBG) + if (FlashDriver == NULL) { + DbgPrint("ERROR: No flash device found at %08x\r\n", NvRamOffset); + } +#endif + + return FlashDriver; +} + diff --git a/private/ntos/nthals/hallx3/alpha/flash8k.h b/private/ntos/nthals/hallx3/alpha/flash8k.h new file mode 100644 index 000000000..7d9131baa --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/flash8k.h @@ -0,0 +1,80 @@ +// flash8k.h + +#ifndef _FLASH8K_H_ +#define _FLASH8K_H_ + +#include "halp.h" +#include "arccodes.h" + +// +// The value of HalpCMOSRamBase must be set at initialization +// + +typedef enum _FLASH_OPERATIONS { + FlashByteWrite, + FlashEraseSector +} FLASH_OPERATIONS, *PFLASH_OPERATIONS; + +typedef struct _FLASH_DRIVER { + PCHAR DeviceName; + ARC_STATUS (*SetReadModeFunction)(PUCHAR Offset); + ARC_STATUS (*WriteByteFunction)(PUCHAR Offset, UCHAR data); + ARC_STATUS (*EraseSectorFunction)(PUCHAR Offset); + PUCHAR (*SectorAlignFunction)(PUCHAR Offset); + UCHAR (*ReadByteFunction)(PUCHAR Offset); + BOOLEAN (*OverwriteCheckFunction)(UCHAR olddata, UCHAR newdata); + ULONG (*SectorSizeFunction)(PUCHAR Offset); + ULONG DeviceSize; + UCHAR ErasedData; +} FLASH_DRIVER, *PFLASH_DRIVER; + +extern PFLASH_DRIVER HalpFlashDriver; + +// +// The following macros define the HalpFlash8k*() functions in terms +// of the FlashDriver variable. FlashDriver points to a structure +// containing information about the currently active flash driver. +// Information in the structure pointed to by FlashDriver includes +// functions within the driver to perform all device-dependent operations. +// + +#define HalpFlash8kSetReadMode(boffset) \ + HalpFlashDriver->SetReadModeFunction( \ + (PUCHAR)((ULONG)(HalpCMOSRamBase) | \ + (ULONG)(boffset))) + +#define HalpFlash8kReadByte(boffset) \ + HalpFlashDriver->ReadByteFunction( \ + (PUCHAR)((ULONG)(HalpCMOSRamBase) | \ + (ULONG)(boffset))) + +#define HalpFlash8kWriteByte(boffset, data) \ + HalpFlashDriver->WriteByteFunction( \ + (PUCHAR)((ULONG)(HalpCMOSRamBase) | \ + (ULONG)(boffset)), ((data) & 0xff)) + +#define HalpFlash8kOverwriteCheck(olddata, newdata) \ + HalpFlashDriver->OverwriteCheckFunction( \ + (olddata) & 0xff, (newdata) & 0xff) + +#define HalpFlash8kEraseSector(boffset) \ + HalpFlashDriver->EraseSectorFunction( \ + (PUCHAR)((ULONG)(HalpCMOSRamBase) | \ + (ULONG)(boffset))) + +#define HalpFlash8kSectorAlign(boffset) \ + HalpFlashDriver->SectorAlignFunction( \ + (PUCHAR)((ULONG)(HalpCMOSRamBase) | \ + (ULONG)(boffset))) + +#define HalpFlash8kSectorSize(boffset) \ + HalpFlashDriver->SectorSizeFunction( \ + (PUCHAR)((ULONG)(HalpCMOSRamBase) | \ + (ULONG)(boffset))) + +#define HalpFlash8kCheckStatus(boffset, operation) \ + HalpFlashDriver->CheckStatusFunction( \ + (PUCHAR)((ULONG)(HalpCMOSRamBase) | \ + (ULONG)(boffset)), (operation)) + +#endif // _FLASH8K_H_ diff --git a/private/ntos/nthals/hallx3/alpha/flashbus.h b/private/ntos/nthals/hallx3/alpha/flashbus.h new file mode 100644 index 000000000..2fceabad3 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/flashbus.h @@ -0,0 +1,9 @@ +// +// These are the defines that make up access to the FlashBus +// + +#define FLASH_ACCESS_ADDR HAL_MAKE_QVA( 0x100000000 ) +#define FLASH_ADDR_SHIFT 8 +#define FLASH_WRITE_FLAG (0x80000000) + +#define CONFIG_ACCESS_ADDR HAL_MAKE_QVA( 0x100100000 ) diff --git a/private/ntos/nthals/hallx3/alpha/flashdrv.c b/private/ntos/nthals/hallx3/alpha/flashdrv.c new file mode 100644 index 000000000..43638aa02 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/flashdrv.c @@ -0,0 +1,19 @@ +#include "flash8k.h" + +// +// Flash Drivers +// +// extern declarations of each known flash driver's Initialize() funcion +// are needed here for addition into the list of known drivers. +// +// FlashDriverList is an array of driver Initialize() functions used to +// identify the flash device present in the system. The last entry +// in FlashDriverList must be NULL. +// +extern PFLASH_DRIVER Am29F400_Initialize(PUCHAR); + +PFLASH_DRIVER (*FlashDriverList[])(PUCHAR) = { + Am29F400_Initialize, + NULL}; + + diff --git a/private/ntos/nthals/hallx3/alpha/fwreturn.c b/private/ntos/nthals/hallx3/alpha/fwreturn.c new file mode 100644 index 000000000..65ae88cb8 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/fwreturn.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\fwreturn.c" + diff --git a/private/ntos/nthals/hallx3/alpha/haldebug.c b/private/ntos/nthals/hallx3/alpha/haldebug.c new file mode 100644 index 000000000..ce91863ec --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/haldebug.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\haldebug.c" + diff --git a/private/ntos/nthals/hallx3/alpha/halpal.s b/private/ntos/nthals/hallx3/alpha/halpal.s new file mode 100644 index 000000000..fc89f8370 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/halpal.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\halpal.s" + diff --git a/private/ntos/nthals/hallx3/alpha/idle.s b/private/ntos/nthals/hallx3/alpha/idle.s new file mode 100644 index 000000000..22dc3c2ee --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/idle.s @@ -0,0 +1,187 @@ +// TITLE("Processor Idle Support") +//++ +// +// Copyright (c) 1992 Digital Equipment Corporation +// Copyright (c) 1993 Digital Equipment Corporation +// +// Module Name: +// +// idle.s +// +// Abstract: +// +// This module implements the HalProcessorIdle interface +// +// Author: +// +// John Vert (jvert) 11-May-1994 +// +// Environment: +// +// Revision History: +// +// Wim Colgate, 11-Nov-1995 +// +// Modified stub routine to idle the processor on LX3. +// +//-- +#include "halalpha.h" +#include "lx3.h" + + + SBTTL("Processor Idle") +//++ +// +// VOID +// HalProcessorIdle( +// VOID +// ) +// +// Routine Description: +// +// This function is called when the current processor is idle with +// interrupts disabled. There is no thread active and there are no +// DPCs to process. Therefore, power can be switched to a standby +// mode until the the next interrupt occurs on the current processor. +// +// N.B. This routine is entered with interrupts disabled. This routine +// must do any power management enabling necessary, enable interrupts, +// then either return or wait for an interrupt. +// +// Arguments: +// +// None. +// +// Return Value: +// +// None. +// +// Note: +// +// On LX3, the sequence of events should are: +// +// Write "idle" to processor +// Flush Dcache +// Enable Interrupts +// +// All of the above MUST be loaded into the Icache of the processor +// once we write "idle" to the processor +// +// Once the processor is idle, we cannot get to the backup cache, +// nor main memory. Once an interrupt occurs, the CPU reattaches via +// hardware magic. +// +//-- + + LEAF_ENTRY(HalProcessorIdle) + + // + // Enable, then disable interrups to force the PALcode + // enable_interrupt routine into the Icache -- by executing it, + // then back to interrupts disabled. + // + + ENABLE_INTERRUPTS + +#ifdef IDLE_PROCESSOR + + // + // set up temps here - instead of in critical Icache area + // temps are a0-a5, t0-t7 + // + + lda a0, HalpInterruptReceived + bis zero, 1, t3 + stl t3, 0(a0) + + // + // set up t5 for superpage mode base address + // + + ldiq t5, -0x4000 // 0xffff ffff ffff c000 + sll t5, 28, t5 // 0xffff fc00 0000 0000 + + // + // set t7 for interrupt register to poll on + // + + ldah t7, 0x1b(zero) // 0x0000 0000 1b00 0000 + sll t7, 4, t7 // 0x0000 0001 b000 0000 + + bis t5, t7, t7 // 0xffff fc01 b000 0000 + + // + // set t6 for a 32K constant for Dcache flushing + // + + ldil t6, 0x8000 // 0x0000 0000 0000 8000 + + // + // set a1 to be the 'bouncing' bit + // + + bis zero, 1, a1 + + mb + + DISABLE_INTERRUPTS + + // + // Flush Dcache -- start at superpage address 0 and read 32K worth of + // data + // + +flush: ldl t1, 0(t5) // read data + addl t5, 0x20, t5 // increment location by 8 longwords + and t5, t6, t4 // check for 32K limit + bne t4, setspin // loop finished + br zero, flush // branch back + + bne a1, touch1 // bounce ahead to touch1 + +continue: + + // + // clear a1 (aka the bouncing bit) so that we actually execite code + // now. + + bis zero, zero, a1 + + // + // Power down the processor to 'idle speed', which is not + // completelty off. Duh. + // + + ldil t0, CONFIG_REGISTER_SMALL // 0x0000 0000 0000 1001 + sll t0, 20, t0 // 0x0000 0001 0010 0000 + + bis t0, t5, t0 // 0xffff fc01 0010 0000 + + ldil t2, CONFIG_SELECT_IDLE // load idle setting + stl t2, 0(t0) // set processor to idle + + // + // Past this point, all instructions MUST be in the Icache + // + + // + // Enable Interrupts + // + +setspin: + ENABLE_INTERRUPTS + + // + // spin on the interrupt bit -- cleared by any interrupt routine + // + +spin: ldl t0, 0(a0) // load bit + bne t0, spin // spin on bit + +touch1: bne a1, continue // go all the way back + +#endif + +done: ret zero, (ra) + + .end HalProcessorIdle diff --git a/private/ntos/nthals/hallx3/alpha/info.c b/private/ntos/nthals/hallx3/alpha/info.c new file mode 100644 index 000000000..22aef63a3 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/info.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\info.c" + diff --git a/private/ntos/nthals/hallx3/alpha/inithal.c b/private/ntos/nthals/hallx3/alpha/inithal.c new file mode 100644 index 000000000..a99cb9a1a --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/inithal.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\inithal.c" + diff --git a/private/ntos/nthals/hallx3/alpha/intsup.s b/private/ntos/nthals/hallx3/alpha/intsup.s new file mode 100644 index 000000000..a7d9f8f4f --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/intsup.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// +#include "pcrtc.h" +#include "..\halalpha\intsup.s" + diff --git a/private/ntos/nthals/hallx3/alpha/ioproc.c b/private/ntos/nthals/hallx3/alpha/ioproc.c new file mode 100644 index 000000000..47c62196e --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/ioproc.c @@ -0,0 +1,102 @@ +/*++ + +Copyright (c) 1991 Microsoft Corporation + +Module Name: + + ioproc.c + +Abstract: + + Stub functions for UP hals. + +Author: + + Ken Reneris (kenr) 22-Jan-1991 + +Environment: + + Kernel mode only. + +Revision History: + + Added to Avanti Hals (Sameer Dekate) 04-May-1994 + +--*/ + +#include "halp.h" +#include "iousage.h" + +extern UCHAR HalRegisteredName[]; + +BOOLEAN +HalpInitMP ( + IN ULONG Phase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock + ); + +VOID HalpInitializePciBuses (VOID); +VOID HalpInitOtherBuses (VOID); + +#ifdef ALLOC_PRAGMA +#pragma alloc_text(INIT,HalpInitMP) +#pragma alloc_text(INIT,HalReportResourceUsage) +#pragma alloc_text(INIT,HalReportResourceUsage) +#pragma alloc_text(INIT,HalpInitOtherBuses) +#endif + + + +BOOLEAN +HalpInitMP ( + IN ULONG Phase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock + ) +{ + return TRUE; + // do nothing +} + + +VOID +HalpResetAllProcessors ( + VOID + ) +{ + // Just return, that will invoke the standard PC reboot code +} + + +VOID +HalReportResourceUsage ( + VOID + ) +{ + INTERFACE_TYPE interfacetype; + ANSI_STRING AHalName; + UNICODE_STRING UHalName; + + switch (HalpBusType) { + case MACHINE_TYPE_ISA: interfacetype = Isa; break; + case MACHINE_TYPE_EISA: interfacetype = Eisa; break; + default: interfacetype = Internal; break; + } + + RtlInitAnsiString (&AHalName, HalRegisteredName); + RtlAnsiStringToUnicodeString (&UHalName, &AHalName, TRUE); + HalpReportResourceUsage ( + &UHalName, // descriptive name + interfacetype // device space interface type + ); + + RtlFreeUnicodeString (&UHalName); +} + + +VOID +HalpInitOtherBuses ( + VOID + ) +{ + // no other internal buses supported +} diff --git a/private/ntos/nthals/hallx3/alpha/iousage.c b/private/ntos/nthals/hallx3/alpha/iousage.c new file mode 100644 index 000000000..c3f2bbe99 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/iousage.c @@ -0,0 +1,554 @@ +/*++ + +Copyright (c) 1991 Microsoft Corporation + +Module Name: + + iousage.c + +Abstract: + +Author: + + Ken Reneris (kenr) + +Environment: + + Kernel mode only. + +Revision History: + +--*/ + +#include "halp.h" +#include "iousage.h" + +// +// Define constants for system IDTs +// + +#define MAXIMUM_IDTVECTOR 0xff +#define MAXIMUM_PRIMARY_VECTOR 0xff +#define PRIMARY_VECTOR_BASE 0x30 // 0-2f are x86 trap vectors + +#define MAX_NAME_LENGTH 256 +UCHAR HalRegisteredName[MAX_NAME_LENGTH] = "Alpha Compatible PCI/ISA HAL"; + +// +// Array to remember hal's IDT usage +// + +KAFFINITY HalpActiveProcessors; + +// +// From usage.c +// + +ADDRESS_USAGE *HalpAddressUsageList; + +// +// IDT vector usage info +// + +IDTUsage HalpIDTUsage[MAXIMUM_IDTVECTOR]; + +VOID +HalpGetResourceSortValue ( + IN PCM_PARTIAL_RESOURCE_DESCRIPTOR pRCurLoc, + OUT PULONG sortscale, + OUT PLARGE_INTEGER sortvalue + ); + +#ifdef ALLOC_PRAGMA +#pragma alloc_text(INIT,HalpRegisterHalName) +#pragma alloc_text(INIT,HalpEnableInterruptHandler) +#pragma alloc_text(INIT,HalpRegisterVector) +#pragma alloc_text(INIT,HalpGetResourceSortValue) +#pragma alloc_text(INIT,HalpReportResourceUsage) +#endif + +VOID +HalpRegisterHalName( + IN PUCHAR NewHalName + ) +/*++ + +Routine Description: + + Allow the HAL to register a name string. + +Arguments: + + HalName - Supplies a pointer to the HAL name to register. + +Return Value: + + None. + +--*/ +{ + + strncpy( HalRegisteredName, NewHalName, MAX_NAME_LENGTH ); + return; +} + + + +VOID +HalpEnableInterruptHandler ( + IN UCHAR ReportFlags, + IN ULONG BusInterruptVector, + IN ULONG SystemInterruptVector, + IN KIRQL SystemIrql, + IN VOID (*HalInterruptServiceRoutine)(VOID), + IN KINTERRUPT_MODE InterruptMode + ) +/*++ + +Routine Description: + + This function connects & registers an IDT vectors usage by the HAL. + +Arguments: + +Return Value: + +--*/ +{ + // + // Remember which vector the hal is connecting so it can be reported + // later on + // + HalpRegisterVector (ReportFlags, BusInterruptVector, SystemInterruptVector, SystemIrql); + + + // + // Connect the IDT and enable the vector now + // + +#if 0 + KiSetHandlerAddressToIDT(SystemInterruptVector, HalInterruptServiceRoutine); +#endif //0 + HalEnableSystemInterrupt(SystemInterruptVector, SystemIrql, InterruptMode); +} + + +VOID +HalpRegisterVector ( + IN UCHAR ReportFlags, + IN ULONG BusInterruptVector, + IN ULONG SystemInterruptVector, + IN KIRQL SystemIrql + ) +/*++ + +Routine Description: + + This registers an IDT vectors usage by the HAL. + +Arguments: + +Return Value: + +--*/ +{ +#if DBG + // There are only 0ff IDT entries... + ASSERT (SystemInterruptVector <= MAXIMUM_IDTVECTOR && + BusInterruptVector <= MAXIMUM_IDTVECTOR); +#endif + + // + // Remember which vector the hal is connecting so it can be reported + // later on + // + + HalpIDTUsage[SystemInterruptVector].Flags = ReportFlags; + HalpIDTUsage[SystemInterruptVector].Irql = SystemIrql; + HalpIDTUsage[SystemInterruptVector].BusReleativeVector = (UCHAR) BusInterruptVector; +} + + +VOID +HalpGetResourceSortValue ( + IN PCM_PARTIAL_RESOURCE_DESCRIPTOR pRCurLoc, + OUT PULONG sortscale, + OUT PLARGE_INTEGER sortvalue + ) +/*++ + +Routine Description: + + Used by HalpReportResourceUsage in order to properly sort + partial_resource_descriptors. + +Arguments: + + pRCurLoc - resource descriptor + +Return Value: + + sortscale - scaling of resource descriptor for sorting + sortvalue - value to sort on + + +--*/ +{ + switch (pRCurLoc->Type) { + case CmResourceTypeInterrupt: + *sortscale = 0; + sortvalue->QuadPart = pRCurLoc->u.Interrupt.Level; + break; + + case CmResourceTypePort: + *sortscale = 1; + *sortvalue = pRCurLoc->u.Port.Start; + break; + + case CmResourceTypeMemory: + *sortscale = 2; + *sortvalue = pRCurLoc->u.Memory.Start; + break; + + default: + *sortscale = 4; + sortvalue->QuadPart = 0; + break; + } +} + + +VOID +HalpReportResourceUsage ( + IN PUNICODE_STRING HalName, + IN INTERFACE_TYPE DeviceInterfaceToUse + ) +/*++ + +Routine Description: + +Arguments: + +Return Value: + +--*/ +{ + PCM_RESOURCE_LIST RawResourceList, TranslatedResourceList; + PCM_FULL_RESOURCE_DESCRIPTOR pRFullDesc, pTFullDesc; + PCM_PARTIAL_RESOURCE_LIST pRPartList, pTPartList; + PCM_PARTIAL_RESOURCE_DESCRIPTOR pRCurLoc, pTCurLoc; + PCM_PARTIAL_RESOURCE_DESCRIPTOR pRSortLoc, pTSortLoc; + CM_PARTIAL_RESOURCE_DESCRIPTOR RPartialDesc, TPartialDesc; + ULONG i, j, k, ListSize, Count; + ULONG curscale, sortscale; + UCHAR pass, reporton; + INTERFACE_TYPE interfacetype; + ULONG CurrentIDT, CurrentElement; + ADDRESS_USAGE *CurrentAddress; + LARGE_INTEGER curvalue, sortvalue; + PHYSICAL_ADDRESS TempAddress; + + // + // Allocate some space to build the resource structure + // + + RawResourceList = (PCM_RESOURCE_LIST) ExAllocatePool (NonPagedPool, PAGE_SIZE*2); + TranslatedResourceList = (PCM_RESOURCE_LIST) ExAllocatePool (NonPagedPool, PAGE_SIZE*2); + + // This functions assumes unset fields are zero + RtlZeroMemory (RawResourceList, PAGE_SIZE*2); + RtlZeroMemory (TranslatedResourceList, PAGE_SIZE*2); + + // + // Initialize the lists + // + + RawResourceList->List[0].InterfaceType = (INTERFACE_TYPE) -1; + + pRFullDesc = RawResourceList->List; + pRCurLoc = (PCM_PARTIAL_RESOURCE_DESCRIPTOR) RawResourceList->List; + pTCurLoc = (PCM_PARTIAL_RESOURCE_DESCRIPTOR) TranslatedResourceList->List; + + // + // Make sure all vectors 00-2f are reserved + // 00-1E reserved by Intel + // 1F reserved by Intel for APIC (apc priority level) + // 20-2e reserved by Microsoft + // 2f reserved by Microsoft for APIC (dpc priority level) + // + + for(i=0; i < PRIMARY_VECTOR_BASE; i++) { + if (!(HalpIDTUsage[i].Flags & IDTOwned)) { + HalpIDTUsage[i].Flags = InternalUsage; + HalpIDTUsage[i].BusReleativeVector = (UCHAR) i; + } + } + + for(pass=0; pass < 3; pass++) { + + switch(pass) { + + case 0: { +#if DBG +DbgPrint("Device LIST...\n"); +#endif // DBG + // + // First pass - build resource lists for resources reported + // reported against device usage. + // + + reporton = DeviceUsage & ~IDTOwned; + interfacetype = DeviceInterfaceToUse; + break; + } + + case 1: { +#if DBG +DbgPrint("Internal LIST...\n"); +#endif // DBG + // + // Second pass = build reousce lists for resources reported + // as internal usage. + // + + reporton = InternalUsage & ~IDTOwned; + interfacetype = Internal; + break; + } + + case 2: { +#if DBG +DbgPrint("PCI LIST...\n"); +#endif // DBG + // + // Third pass = build reousce lists for resources reported + // as PCI usage. + // + + reporton = PCIUsage & ~IDTOwned; + interfacetype = PCIBus; + break; + } + } + + CurrentIDT = 0; + CurrentElement = 0; + CurrentAddress = HalpAddressUsageList; + + for (; ;) { + if (CurrentIDT <= MAXIMUM_IDTVECTOR) { + // + // Check to see if CurrentIDT needs to be reported + // + + if (!(HalpIDTUsage[CurrentIDT].Flags & reporton)) { + // Don't report on this one + CurrentIDT++; + continue; + } + + // + // Report CurrentIDT resource + // + + RPartialDesc.Type = CmResourceTypeInterrupt; + RPartialDesc.ShareDisposition = CmResourceShareDriverExclusive; + RPartialDesc.Flags = + HalpIDTUsage[CurrentIDT].Flags & InterruptLatched ? + CM_RESOURCE_INTERRUPT_LATCHED : + CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE; + RPartialDesc.u.Interrupt.Vector = HalpIDTUsage[CurrentIDT].BusReleativeVector; + RPartialDesc.u.Interrupt.Level = HalpIDTUsage[CurrentIDT].BusReleativeVector; + RPartialDesc.u.Interrupt.Affinity = HalpActiveProcessors; + + RtlCopyMemory (&TPartialDesc, &RPartialDesc, sizeof TPartialDesc); + TPartialDesc.u.Interrupt.Vector = CurrentIDT; + TPartialDesc.u.Interrupt.Level = HalpIDTUsage[CurrentIDT].Irql; + + CurrentIDT++; + + } else { + + // + // Check to see if CurrentAddress needs to be reported + // + + if (!CurrentAddress) { + break; // No addresses left + } + + if (!(CurrentAddress->Flags & reporton)) { + // Don't report on this list + CurrentElement = 0; + CurrentAddress = CurrentAddress->Next; + continue; + } + + if (!CurrentAddress->Element[CurrentElement].Length) { + // End of current list, go to next list + CurrentElement = 0; + CurrentAddress = CurrentAddress->Next; + continue; + } + + // + // Report CurrentAddress + // + + RPartialDesc.Type = (UCHAR) CurrentAddress->Type; + RPartialDesc.ShareDisposition = CmResourceShareDriverExclusive; + + if (RPartialDesc.Type == CmResourceTypePort) { + i = 1; // address space port + RPartialDesc.Flags = CM_RESOURCE_PORT_IO; + } else { + i = 0; // address space memory + RPartialDesc.Flags = CM_RESOURCE_MEMORY_READ_WRITE; + } + + // Notice: assuming u.Memory and u.Port have the same layout + RPartialDesc.u.Memory.Start.HighPart = 0; + RPartialDesc.u.Memory.Start.LowPart = + CurrentAddress->Element[CurrentElement].Start; + + RPartialDesc.u.Memory.Length = + CurrentAddress->Element[CurrentElement].Length; + +#if DBG +DbgPrint("Start=0x%x Lenght=0x%x\n", RPartialDesc.u.Memory.Start.LowPart, RPartialDesc.u.Memory.Length); +#endif // DBG + + // translated address = Raw address + RtlCopyMemory (&TPartialDesc, &RPartialDesc, sizeof TPartialDesc); + HalTranslateBusAddress ( + interfacetype, // device bus or internal + 0, // bus number + RPartialDesc.u.Memory.Start, // source address + &i, // address space + &TempAddress ); // aligned translated address + + TPartialDesc.u.Memory.Start = TempAddress; // TPartialDesc is pack(4) + +#if DBG +DbgPrint("TRANSLATED ADDRESS Start=0x%x Lenght=0x%x\n", TPartialDesc.u.Memory.Start.LowPart, TPartialDesc.u.Memory.Length); +#endif // DBG + + if (RPartialDesc.Type == CmResourceTypePort && i == 0) { + TPartialDesc.Flags = CM_RESOURCE_PORT_MEMORY; + } + + CurrentElement++; + } + + // + // Include the current resource in the HALs list + // + + if (pRFullDesc->InterfaceType != interfacetype) { + // + // Interface type changed, add another full section + // + + RawResourceList->Count++; + TranslatedResourceList->Count++; + + pRFullDesc = (PCM_FULL_RESOURCE_DESCRIPTOR) pRCurLoc; + pTFullDesc = (PCM_FULL_RESOURCE_DESCRIPTOR) pTCurLoc; + + pRFullDesc->InterfaceType = interfacetype; + pTFullDesc->InterfaceType = interfacetype; + + pRPartList = &pRFullDesc->PartialResourceList; + pTPartList = &pTFullDesc->PartialResourceList; + + // + // Bump current location pointers up + // + pRCurLoc = pRFullDesc->PartialResourceList.PartialDescriptors; + pTCurLoc = pTFullDesc->PartialResourceList.PartialDescriptors; + } + + + pRPartList->Count++; + pTPartList->Count++; + RtlCopyMemory (pRCurLoc, &RPartialDesc, sizeof RPartialDesc); + RtlCopyMemory (pTCurLoc, &TPartialDesc, sizeof TPartialDesc); + + pRCurLoc++; + pTCurLoc++; + } + } + + ListSize = (ULONG) ( ((PUCHAR) pRCurLoc) - ((PUCHAR) RawResourceList) ); + + // + // The HAL's resource usage structures have been built + // Sort the partial lists based on the Raw resource values + // + + pRFullDesc = RawResourceList->List; + pTFullDesc = TranslatedResourceList->List; + + for (i=0; i < RawResourceList->Count; i++) { + + pRCurLoc = pRFullDesc->PartialResourceList.PartialDescriptors; + pTCurLoc = pTFullDesc->PartialResourceList.PartialDescriptors; + Count = pRFullDesc->PartialResourceList.Count; + + for (j=0; j < Count; j++) { + HalpGetResourceSortValue (pRCurLoc, &curscale, &curvalue); + + pRSortLoc = pRCurLoc; + pTSortLoc = pTCurLoc; + + for (k=j; k < Count; k++) { + HalpGetResourceSortValue (pRSortLoc, &sortscale, &sortvalue); + + if (sortscale < curscale || + (sortscale == curscale && + (sortvalue.QuadPart < curvalue.QuadPart)) ) { + + // + // Swap the elements.. + // + + RtlCopyMemory (&RPartialDesc, pRCurLoc, sizeof RPartialDesc); + RtlCopyMemory (pRCurLoc, pRSortLoc, sizeof RPartialDesc); + RtlCopyMemory (pRSortLoc, &RPartialDesc, sizeof RPartialDesc); + + // swap translated descriptor as well + RtlCopyMemory (&TPartialDesc, pTCurLoc, sizeof TPartialDesc); + RtlCopyMemory (pTCurLoc, pTSortLoc, sizeof TPartialDesc); + RtlCopyMemory (pTSortLoc, &TPartialDesc, sizeof TPartialDesc); + + // get new curscale & curvalue + HalpGetResourceSortValue (pRCurLoc, &curscale, &curvalue); + } + + pRSortLoc++; + pTSortLoc++; + } + + pRCurLoc++; + pTCurLoc++; + } + + pRFullDesc = (PCM_FULL_RESOURCE_DESCRIPTOR) pRCurLoc; + pTFullDesc = (PCM_FULL_RESOURCE_DESCRIPTOR) pTCurLoc; + } + + + // + // Inform the IO system of our resources.. + // + + IoReportHalResourceUsage ( + HalName, + RawResourceList, + TranslatedResourceList, + ListSize + ); + + ExFreePool (RawResourceList); + ExFreePool (TranslatedResourceList); +} diff --git a/private/ntos/nthals/hallx3/alpha/iousage.h b/private/ntos/nthals/hallx3/alpha/iousage.h new file mode 100644 index 000000000..cefab9095 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/iousage.h @@ -0,0 +1,92 @@ +/*++ + +Copyright (c) 1991 Microsoft Corporation +Copyright (c) 1992,1993 Digital Equipment Corporation + +Module Name: + + iousage.h + +Abstract: + + This header file defines the iousage definitions + +Author: + + Sameer Dekate 5-3-1994 + + +Revision History: + + Most pieces have be stolen from Microsofts halp.h + +--*/ + +// +// External Function Prototypes +// + +VOID +HalpEnableInterruptHandler ( + IN UCHAR ReportFlags, + IN ULONG BusInterruptVector, + IN ULONG SystemInterruptVector, + IN KIRQL SystemIrql, + IN VOID (*HalInterruptServiceRoutine)(VOID), + IN KINTERRUPT_MODE InterruptMode + ); + +VOID +HalpRegisterVector ( + IN UCHAR ReportFlags, + IN ULONG BusInterruptVector, + IN ULONG SystemInterruptVector, + IN KIRQL SystemIrql + ); + +VOID +HalpReportResourceUsage ( + IN PUNICODE_STRING HalName, + IN INTERFACE_TYPE DeviceInterfaceToUse + ); + + +VOID +HalpRegisterHalName( + IN PUCHAR NewHalName + ); + +// +// Resource usage information +// + +#pragma pack(1) +typedef struct { + UCHAR Flags; + KIRQL Irql; + UCHAR BusReleativeVector; +} IDTUsage; + +typedef struct _HalAddressUsage{ + struct _HalAddressUsage *Next; + CM_RESOURCE_TYPE Type; // Port or Memory + UCHAR Flags; // same as IDTUsage.Flags + struct { + ULONG Start; + ULONG Length; + } Element[]; +} ADDRESS_USAGE; +#pragma pack() + +#define IDTOwned 0x01 // IDT is not available for others +#define InterruptLatched 0x02 // Level or Latched +#define InternalUsage 0x11 // Report usage on internal bus +#define DeviceUsage 0x21 // Report usage on device bus +#define PCIUsage 0x41 // Report usage on PCI bus + +extern IDTUsage HalpIDTUsage[]; +extern ADDRESS_USAGE *HalpAddressUsageList; + +#define HalpRegisterAddressUsage(a) \ + (a)->Next = HalpAddressUsageList, HalpAddressUsageList = (a); + diff --git a/private/ntos/nthals/hallx3/alpha/lx3.h b/private/ntos/nthals/hallx3/alpha/lx3.h new file mode 100644 index 000000000..157c89bd3 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/lx3.h @@ -0,0 +1,155 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + avantdef.h + +Abstract: + + This module specifies platform-specific definitions for the + Avanti modules. + +Author: + + Joe Notarangelo 25-Oct-1993 + +Revision History: + + +--*/ + +#ifndef _LX3DEF_ +#define _LX3DEF_ + +#include "alpharef.h" +#include "apecs.h" +#include "isaaddr.h" + +// +// Highest Virtual local PCI Slot is 14 == IDSEL PCI_AD[25] +// + +#define PCI_MAX_LOCAL_DEVICE 14 + +// +// Highest PCI interrupt vector is in ISA Vector Space +// + +#define PCI_MAX_INTERRUPT_VECTOR (MAXIMUM_ISA_VECTOR - ISA_VECTORS) + +// +// Define the per-processor data structures allocated in the PCR +// for each EV4 processor. +// + +#if !defined (_LANGUAGE_ASSEMBLY) && !defined (AXP_FIRMWARE) + +typedef struct _AVANTI_PCR{ + ULONGLONG HalpCycleCount; // 64-bit per-processor cycle count + EV4ProfileCount ProfileCount; // Profile counter state do not move + EV4IrqStatus IrqStatusTable[MaximumIrq];// Irq status table +} AVANTI_PCR, *PAVANTI_PCR; + +// +// Short form for PCR access +// + +#define HAL_PCR ( (PAVANTI_PCR)(&(PCR->HalReserved)) ) + +#endif //!_LANGUAGE_ASSEMBLY + +// +// define base of sparse I/O space +// +#define PCI_SPARSE_IO_BASE_QVA ((ULONG)(HAL_MAKE_QVA(APECS_PCI_IO_BASE_PHYSICAL))) + +// +// PCI-E/ISA Bridge chip configuration space base is at physical address +// 0x1.e000.0000. The equivalent QVA is: +// +// ((0x1.e000.0000 + cache line offset) >> IO_BIT_SHIFT) | QVA_ENABLE +// which equals 0xaf000000. +// +// NB: The PCI configuration space address is what we're really referring +// to, here; both symbols are useful. +// + +#define PCI_CONFIGURATION_BASE_QVA 0xaf000000 +#define PCI_BRIDGE_CONFIGURATION_BASE_QVA 0xaf000000 + +// +// ISA memory space base starts at 0x2.0000.0000. +// The equivalent QVA is: +// +// ((0x2.0000.0000 + cache line offset) >> IO_BIT_SHIFT) | QVA_ENABLE +// + +#define ISA_MEMORY_BASE_QVA 0xb0000000 + +// +// I/O space base starts at 0x3.0000.0000. +// The equivalent QVA is: +// +// ((0x3.0000.0000 + cache line offset) >> IO_BIT_SHIFT) | QVA_ENABLE +// + +#define IO_BASE_QVA 0xAE000000 + +// +// Define the PCI config cycle type +// + +#define PCI_CONFIG_CYCLE_TYPE_0 0x0 // Local PCI device +#define PCI_CONFIG_CYCLE_TYPE_1 0x1 // Nested PCI device + +#define PCI_REVISION (0x0100 >> IO_BIT_SHIFT) + +// +// Define the location of the PCI/ISA bridge IDSEL: AD[18] +// + +#define PCI_ISA_BRIDGE_HEADER_OFFSET (0x00070000 >> IO_BIT_SHIFT) + + +// +// Define primary (and only) CPU on an Avanti system +// + +#define HAL_PRIMARY_PROCESSOR ((ULONG)0x0) +#define HAL_MAXIMUM_PROCESSOR ((ULONG)0x0) + +// +// Define the default processor clock frequency used before the actual +// value can be determined. +// + +#define DEFAULT_PROCESSOR_FREQUENCY_MHZ (233) +#define DEFAULT_PROCESSOR_CYCLE_COUNT (1000000/233) + +// +// define configuration register +// (see page 5-3) of the LX3 spec. +// + +#define CONFIG_REGISTER_PHYS 0x100100000 +#define CONFIG_REGISTER_SMALL 0x1001 + +#define CONFIG_SELECT_DISABLE_AUDIO 0x0 +#define CONFIG_SELECT_ENABLE_AUDIO 0x1 +#define CONFIG_SELECT_SELECT_AUDIO1_530 0x10 +#define CONFIG_SELECT_SELECT_AUDIO1_E80 0x11 +#define CONFIG_SELECT_SELECT_AUDIO2_F40 0x20 +#define CONFIG_SELECT_SELECT_AUDIO2_604 0x21 +#define CONFIG_SELECT_ECP_DMA_0 0x30 +#define CONFIG_SELECT_ECP_DMA_1 0x31 +#define CONFIG_SELECT_DISABLE_87303 0x40 +#define CONFIG_SELECT_ENABLE_87303 0x41 +#define CONFIG_SELECT_LIGHT_LED 0x60 +#define CONFIG_SELECT_UNLIGHT_LED 0x61 +#define CONFIG_SELECT_RESET_SYSTEM 0x71 +#define CONFIG_SELECT_IDLE 0x80 + +#endif // _LX3DEF_ + diff --git a/private/ntos/nthals/hallx3/alpha/lxinitnt.c b/private/ntos/nthals/hallx3/alpha/lxinitnt.c new file mode 100644 index 000000000..8706dfb4a --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/lxinitnt.c @@ -0,0 +1,900 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation +Copyright (c) 1994 Digital Equipment Corporation + + +Module Name: + + lxinitnt.c + +Abstract: + + + This module implements the platform-specific initialization for + an Avanti system. + +Author: + + Joe Notarangelo 25-Oct-1993 + +Environment: + + Kernel mode only. + +Revision History: + + Wim Colgate November, 1995 + modified Joe's cruft for LX3 support. + +--*/ + +#include "halp.h" +#include "pcrtc.h" +#include "lx3.h" +#include "halpcsl.h" +#include "eisa.h" +#include "pci.h" +#include "pcip.h" +#include "iousage.h" +#include "stdio.h" + +#include "fwcallbk.h" + +#include <ntverp.h> // to get the product build number. + +// +// Include the header containing Error Frame Definitions(in halalpha). +// +#include "errframe.h" + +// +// Define extern global buffer for the Uncorrectable Error Frame. +// declared in halalpha\inithal.c +// + +extern PERROR_FRAME PUncorrectableError; + +#if DBG +VOID +DumpEpic( + VOID + ); +#endif // DBG + +// +// temporary +// + +PVOID HalpCMOSRamBase = 0; + +// +// Define the Product Naming data. +// + +PCHAR HalpProductName = "255"; +PCHAR HalpFamilyName = "AlphaStation"; +ULONG HalpProcessorNumber = 4; + + +// +// Define global data for builtin device interrupt enables. +// + +USHORT HalpBuiltinInterruptEnable; + + +// irql mask and tables +// +// irql 0 - passive +// irql 1 - sfw apc level +// irql 2 - sfw dispatch level +// irql 3 - device low +// irql 4 - device high +// irql 5 - clock +// irql 6 - real time, ipi, performance counters +// irql 7 - error, mchk, nmi, halt +// +// +// IDT mappings: +// For the built-ins, GetInterruptVector will need more info, +// or it will have to be built-in to the routines, since +// these don't match IRQL levels in any meaningful way. +// +// 0 passive 8 perf cntr 1 +// 1 apc 9 +// 2 dispatch 10 PIC +// 3 11 +// 4 12 errors +// 5 clock 13 +// 6 perf cntr 0 14 halt +// 7 nmi 15 +// +// This is assuming the following prioritization: +// nmi +// halt +// errors +// performance counters +// clock +// pic + +// +// The hardware interrupt pins are used as follows for Avanti +// +// IRQ_H[0] = EPIC Error +// IRQ_H[1] = unused +// IRQ_H[2] = PIC +// IRQ_H[3] = NMI +// IRQ_H[4] = Clock +// IRQ_H[5] = Halt + +// +// For information purposes: here is what the IDT division looks like: +// +// 000-015 Built-ins (we only use 8 entries; NT wants 10) +// 016-031 ISA +// 048-063 EISA +// 080-095 PCI +// 112-127 Turbo Channel +// 128-255 unused, as are all other holes +// + +// +// Define the bus type, this value allows us to distinguish between +// EISA and ISA systems. +// +ULONG HalpBusType = MACHINE_TYPE_ISA; + +// +// This is the PCI Memory space that cannot be used by anyone +// and therefore the HAL says it is reserved for itself +// + +ADDRESS_USAGE +AvantiPCIMemorySpace = { + NULL, CmResourceTypeMemory, PCIUsage, + { + __8MB, __32MB - __8MB, // Start=8MB; Length=24Mb (8 through 32) + 0,0 + } +}; + +// +// Define global data used to communicate new clock rates to the clock +// interrupt service routine. +// + +ULONG HalpCurrentTimeIncrement; +ULONG HalpNextRateSelect; +ULONG HalpNextTimeIncrement; +ULONG HalpNewTimeIncrement; + +VOID +HalpInitializeProcessorParameters( + VOID + ); + +VOID +HalpInitializeHAERegisters( + VOID + ); + +VOID +HalpClearInterrupts( + ); + +VOID +HalpParseLoaderBlock( + PLOADER_PARAMETER_BLOCK LoaderBlock + ); + + +BOOLEAN +HalpInitializeInterrupts ( + VOID + ) + +/*++ + +Routine Description: + + This function initializes interrupts for an Alpha system. + +Arguments: + + None. + +Return Value: + + A value of TRUE is returned if the initialization is successfully + completed. Otherwise a value of FALSE is returned. + +--*/ + +{ + + UCHAR DataByte; + ULONG DataLong; + ULONG Index; + ULONG Irq; + KIRQL Irql; + UCHAR Priority; + ULONG Vector; + + // + // Initialize HAL processor parameters based on estimated CPU speed. + // This must be done before HalpStallExecution is called. Compute integral + // megahertz first to avoid rounding errors due to imprecise cycle clock + // period values. + // + + HalpInitializeProcessorParameters(); + + // + // Connect the Stall interrupt vector to the clock. When the + // profile count is calculated, we then connect the normal + // clock. + + + PCR->InterruptRoutine[CLOCK2_LEVEL] = HalpStallInterrupt; + + // + // Clear all pending interrupts + // + + HalpClearInterrupts(); + + // + // Start the peridodic interrupt from the RTC + // + HalpProgramIntervalTimer(MAXIMUM_RATE_SELECT); + +//jnfix, wkc - init the Eisa interrupts after the chip, don't init the +// PIC here, fix halenablesysteminterrupt to init the pic +// interrrupt, as in sable + + // + // Initialize the PCI/ISA interrupt controller. + // + + HalpInitializePCIInterrupts(); + + // + // Initialize the 21064 interrupts. + // + + HalpInitialize21064Interrupts(); + + HalpEnable21064SoftwareInterrupt( Irql = APC_LEVEL ); + HalpEnable21064SoftwareInterrupt( Irql = DISPATCH_LEVEL ); + HalpEnable21064HardwareInterrupt( Irq = 4, + Irql = CLOCK_LEVEL, + Vector = CLOCK_VECTOR, + Priority = 0 ); + HalpEnable21064HardwareInterrupt( Irq = 3, + Irql = HIGH_LEVEL, + Vector = EISA_NMI_VECTOR, + Priority = 0 ); + HalpEnable21064HardwareInterrupt( Irq = 2, + Irql = DEVICE_LEVEL, + Vector = PIC_VECTOR, + Priority = 0 ); + + return TRUE; + +} + + +VOID +HalpClearInterrupts( + ) +/*++ + +Routine Description: + + This function no longer does anything. + +Arguments: + + None. + +Return Value: + + None. + +--*/ + +{ + return; +} + + +VOID +HalpSetTimeIncrement( + VOID + ) +/*++ + +Routine Description: + + This routine is responsible for setting the time increment for an EV4 + based machine via a call into the kernel. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + + // + // Set the time increment value. + // + + HalpCurrentTimeIncrement = MAXIMUM_INCREMENT; + HalpNextTimeIncrement = MAXIMUM_INCREMENT; + HalpNextRateSelect = 0; + KeSetTimeIncrement( MAXIMUM_INCREMENT, MINIMUM_INCREMENT ); + +} + +// +// Define global data used to calibrate and stall processor execution. +// + +ULONG HalpProfileCountRate; + +VOID +HalpInitializeClockInterrupts( + VOID + ) + +/*++ + +Routine Description: + + This function is called during phase 1 initialization to complete + the initialization of clock interrupts. For EV4, this function + connects the true clock interrupt handler and initializes the values + required to handle profile interrupts. + +Arguments: + + None. + +Return Value: + + None. + +--*/ + +{ + + // + // Compute the profile interrupt rate. + // + + HalpProfileCountRate = ((1000 * 1000 * 10) / KeQueryTimeIncrement()); + + // + // Set the time increment value and connect the real clock interrupt + // routine. + // + + PCR->InterruptRoutine[CLOCK2_LEVEL] = HalpClockInterrupt; + + return; +} + +VOID +HalpEstablishErrorHandler( + VOID + ) +/*++ + +Routine Description: + + This routine performs the initialization necessary for the HAL to + begin servicing machine checks. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + BOOLEAN ReportCorrectables; + + // + // Connect the machine check handler via the PCR. + // + + PCR->MachineCheckError = HalMachineCheck; + + // + // Initialize error handling for APECS. + // + + HalpInitializeMachineChecks( ReportCorrectables = FALSE ); + + return; +} + +VOID +HalpInitializeHalName( + VOID + ) + +/*++ + +Routine Description: + + Thsi routine intializes the visible HAL name. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + + UCHAR MsgBuffer[256]; + + sprintf(MsgBuffer, + "%s %s, %d Mhz, PCI/ISA HAL\n", + HalpFamilyName, + HalpProductName, + HalpClockMegaHertz ); + + // + // Register the name of the HAL. + // + + HalpRegisterHalName( MsgBuffer ); + +} + +VOID +HalpInitializeMachineDependent( + IN ULONG Phase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock + ) +/*++ + +Routine Description: + + This function performs any EV4-specific initialization based on + the current phase on initialization. + +Arguments: + + Phase - Supplies an indicator for phase of initialization, phase 0 or + phase 1. + + LoaderBlock - supplies a pointer to the loader block. + +Return Value: + + None. + +--*/ +{ + + UCHAR MsgBuffer[256]; + + if( Phase == 0 ){ + + // + // Phase 0 Initialization. + // + + // + // Parse the Loader Parameter block looking for PCI entry to determine + // if PCI parity should be disabled + // + + HalpParseLoaderBlock( LoaderBlock ); + + // + // Re-establish the error handler, to reflect the parity checking + // + + HalpEstablishErrorHandler(); + + // + // Set the HAE registers + // + + HalpInitializeHAERegisters(); + + } else { + + // + // Phase 1 Initialization. + // + + // + // Initialize the existing bus handlers. + // + + HalpRegisterInternalBusHandlers(); + + // + // Initialize PCI Bus. + // + + HalpInitializePCIBus( LoaderBlock ); + + // + // Initialize profiler. + // + + HalpInitializeProfiler(); + + + // + // Print out a cool-o message + // + + sprintf(MsgBuffer, + "Digital Equipment Corporation %s %s\n", + HalpFamilyName, + HalpProductName); + + HalDisplayString(MsgBuffer); + + // + // Initialize HAL name + // + + HalpInitializeHalName(); + + } + + return; + +} + + +VOID +HalpStallInterrupt ( + VOID + ) + +/*++ + +Routine Description: + + This function serves as the stall calibration interrupt service + routine. It is executed in response to system clock interrupts + during the initialization of the HAL layer. + +Arguments: + + None. + +Return Value: + + None. + +--*/ + +{ + + HalpAcknowledgeClockInterrupt(); + + return; +} + + +ULONG +HalSetTimeIncrement ( + IN ULONG DesiredIncrement + ) + +/*++ + +Routine Description: + + This function is called to set the clock interrupt rate to the frequency + required by the specified time increment value. + +Arguments: + + DesiredIncrement - Supplies desired number of 100ns units between clock + interrupts. + +Return Value: + + The actual time increment in 100ns units. + +--*/ + +{ + ULONG NewTimeIncrement; + ULONG NextRateSelect; + KIRQL OldIrql; + + // + // Raise IRQL to the highest level, set the new clock interrupt + // parameters, lower IRQl, and return the new time increment value. + // + KeRaiseIrql(HIGH_LEVEL, &OldIrql); + if (DesiredIncrement < MINIMUM_INCREMENT) { + DesiredIncrement = MINIMUM_INCREMENT; + } + if (DesiredIncrement > MAXIMUM_INCREMENT) { + DesiredIncrement = MAXIMUM_INCREMENT; + } + + // + // Find the allowed increment that is less than or equal to + // the desired increment. + // + if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS4) { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS4; + NextRateSelect = RTC_RATE_SELECT4; + } else if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS3) { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS3; + NextRateSelect = RTC_RATE_SELECT3; + } else if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS2) { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS2; + NextRateSelect = RTC_RATE_SELECT2; + } else { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS1; + NextRateSelect = RTC_RATE_SELECT1; + } + + HalpNextRateSelect = NextRateSelect; + HalpNewTimeIncrement = NewTimeIncrement; + + KeLowerIrql(OldIrql); + + return NewTimeIncrement; +} + + +VOID +HalpInitializeHAERegisters( + VOID + ) +/*++ + +Routine Description: + + This function initializes the HAE registers in the EPIC/APECS chipset. + It also register the holes in the PCI memory space if any. + +Arguments: + + none + +Return Value: + + none + +--*/ +{ + // + // We set HAXR1 to 0. This means no address extension + // + + WRITE_EPIC_REGISTER( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr1, 0); + + // + // We set HAXR2 to 0. Which means we have the following + // PCI IO addresses: + // 0 to 64KB VALID. HAXR2 Not used in address translation + // 64K to 16MB VALID. HAXR2 is used in the address translation + // + + WRITE_EPIC_REGISTER( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr2, 0); + + // + // Report that the apecs mapping to the Io subsystem + // + + HalpRegisterAddressUsage (&AvantiPCIMemorySpace); + +#if DBG + DumpEpic(); +#endif // DBG +} + + +VOID +HalpResetHAERegisters( + VOID + ) +/*++ + +Routine Description: + + This function resets the HAE registers in the EPIC/APECS chipset to 0. + This is routine called during a shutdown so that the prom + gets a predictable environment. + +Arguments: + + none + +Return Value: + + none + +--*/ +{ + WRITE_EPIC_REGISTER( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr1, 0 ); + WRITE_EPIC_REGISTER( &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr2, 0 ); +} + +VOID +HalpGetSystemInfo(SYSTEM_INFORMATION *SystemInfo) +/*++ + +Routine Description: + + This function fills in the System information. + + +Arguments: + + SystemInfo - Pointer to the SYSTEM_INFORMATION buffer that needs + to be filled in. + +Return Value: + + none + +--*/ +{ + EXTENDED_SYSTEM_INFORMATION FwExtSysInfo; + + + VenReturnExtendedSystemInformation(&FwExtSysInfo); + + RtlCopyMemory(SystemInfo->FirmwareRevisionId, + FwExtSysInfo.FirmwareVersion, + 16); + + RtlCopyMemory(SystemInfo->SystemSerialNumber, + FwExtSysInfo.SystemSerialNumber, + 16); + + SystemInfo->SystemRevision = PCR->SystemRevision; + SystemInfo->SystemVariant = PCR->SystemVariant; + + sprintf(SystemInfo->SystemType,"lx3"); + + SystemInfo->PalMajorVersion = PCR->PalMajorVersion; + SystemInfo->PalMinorVersion = PCR->PalMinorVersion; + + SystemInfo->OsRevisionId = VER_PRODUCTBUILD; + + // + // For now fill in dummy values. + // + SystemInfo->ModuleVariant = 1UL; + SystemInfo->ModuleRevision = 1UL; + SystemInfo->ModuleSerialNumber = 0; + + return; +} + +VOID +HalpGetMachineDependentErrorFrameSizes( + PULONG RawProcessorSize, + PULONG RawSystemInfoSize + ) +/*++ + +Routine Description: + + This function returns the size of the system specific structures. + + +Arguments: + + RawProcessorSize - Pointer to a buffer that will receive the + size of the processor specific error information buffer. + + RawSystemInfoSize - Pointer to a buffer that will receive the + size of the system specific error information buffer. + +Return Value: + + none + +--*/ +{ + *RawProcessorSize = sizeof(PROCESSOR_EV4_UNCORRECTABLE); + *RawSystemInfoSize = sizeof(APECS_UNCORRECTABLE_FRAME); + return; +} + + +VOID +HalpInitializeUncorrectableErrorFrame ( + VOID + ) +/*++ + +Routine Description: + + This function Allocates an Uncorrectable Error frame for this + system and initializes the frame with certain constant/global + values. + + This is routine called during machine dependent system + Initialization. + +Arguments: + + none + +Return Value: + + none + +--*/ +{ + PROCESSOR_EV4_UNCORRECTABLE processorFrame; + APECS_UNCORRECTABLE_FRAME AvantiUnCorrrectable; + + // + // If the Uncorrectable error buffer is not set then simply return + // + if(PUncorrectableError == NULL) + return; + + PUncorrectableError->Signature = ERROR_FRAME_SIGNATURE; + + PUncorrectableError->FrameType = UncorrectableFrame; + + // + // ERROR_FRAME_VERSION is define in errframe.h and will + // change as and when there is a change in the errframe.h. + // This Version number helps the service, that reads this + // information from the dumpfile, to check if it knows about + // this frmae version type to decode. If it doesn't know, it + // will dump the entire frame to the EventLog with a message + // "Error Frame Version Mismatch". + // + + PUncorrectableError->VersionNumber = ERROR_FRAME_VERSION; + + // + // The sequence number will always be 1 for Uncorrectable errors. + // + + PUncorrectableError->SequenceNumber = 1; + + // + // The PerformanceCounterValue field is not used for Uncorrectable + // errors. + // + + PUncorrectableError->PerformanceCounterValue = 0; + + // + // We will fill in the UncorrectableFrame.SystemInfo here. + // + + HalpGetSystemInfo(&PUncorrectableError->UncorrectableFrame.System); + + PUncorrectableError->UncorrectableFrame.Flags.SystemInformationValid = 1; + + return; +} diff --git a/private/ntos/nthals/hallx3/alpha/lxintsup.c b/private/ntos/nthals/hallx3/alpha/lxintsup.c new file mode 100644 index 000000000..f9a535832 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/lxintsup.c @@ -0,0 +1,396 @@ +/*++ + +Copyright (c) 1990 Microsoft Corporation +Copyright (c) 1992, 1993 Digital Equipment Corporation + +Module Name: + + lxintsup.c + +Abstract: + + The module provides the interrupt support for LX3 + +Author: + + Eric Rehm (DEC) 29-December-1993 + +Revision History: + + Rewritten from ebintsup.c to lx3intsup. + + +--*/ + + +#include "halp.h" +#include "eisa.h" +#include "ebsgdma.h" +#include "lx3.h" +#include "pcrtc.h" + + +extern BOOLEAN SioCStep; + +#ifdef IDLE_PROCESSOR +ULONG HalpInterruptReceived; +BOOLEAN +PreHalpSioDispatch( + VOID + ); +#endif + +// +// Declare the interrupt handler for the PCI and ISA bus. +// + +BOOLEAN +HalpSioDispatch( + VOID + ); + +// +// The following is the interrupt object used for DMA controller interrupts. +// DMA controller interrupts occur when a memory parity error occurs or a +// programming error occurs to the DMA controller. +// + +KINTERRUPT HalpEisaNmiInterrupt; + +// +// The following function initializes NMI handling. +// + +VOID +HalpInitializeNMI( + VOID + ); + +// +// The following function is called when an ISA NMI occurs. +// + +BOOLEAN +HalHandleNMI( + IN PKINTERRUPT Interrupt, + IN PVOID ServiceContext + ); + + +BOOLEAN +HalpInitializePCIInterrupts ( + VOID + ) + +/*++ + +Routine Description: + + This routine initializes the structures necessary for ISA & PCI operations + and connects the intermediate interrupt dispatcher. + +Arguments: + + None. + +Return Value: + + If the second level interrupt dispatcher is connected, then a value of + TRUE is returned. Otherwise, a value of FALSE is returned. + +--*/ + +{ + + KIRQL oldIrql; + + + // + // Initialize the EISA NMI interrupt. + // + + HalpInitializeNMI(); + + + // + // Directly connect the ISA interrupt dispatcher to the level for + // ISA bus interrupt. + // + // N.B. This vector is reserved for exclusive use by the HAL (see + // interrupt initialization. + // + +#ifdef IDLE_PROCESSOR + PCR->InterruptRoutine[PIC_VECTOR] = PreHalpSioDispatch; +#else + PCR->InterruptRoutine[PIC_VECTOR] = HalpSioDispatch; +#endif + HalEnableSystemInterrupt(PIC_VECTOR, ISA_DEVICE_LEVEL, LevelSensitive); + + + // + // Intitialize interrupt controller + // + + KeRaiseIrql(ISA_DEVICE_LEVEL, &oldIrql); + + + // + // Initialize the PCI-ISA bridge interrupt controller + // + + HalpInitializeSioInterrupts(); + + // + // Restore IRQL level. + // + + KeLowerIrql(oldIrql); + + // + // Initialize the DMA mode registers to a default value. + // Disable all of the DMA channels except channel 4 which is the + // cascade of channels 0-3. + // + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Dma1BasePort.AllMask, + 0x0F + ); + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Dma2BasePort.AllMask, + 0x0E + ); + + return(TRUE); +} + +VOID +HalpInitializeNMI( + VOID + ) +/*++ + +Routine Description: + + This function is called to intialize SIO NMI interrupts. + +Arguments: + + None. + +Return Value: + + None. +--*/ +{ + UCHAR DataByte; + + // + // Initialize the SIO NMI interrupt. + // + + KeInitializeInterrupt( &HalpEisaNmiInterrupt, + HalHandleNMI, + NULL, + NULL, + EISA_NMI_VECTOR, + EISA_NMI_LEVEL, + EISA_NMI_LEVEL, + LevelSensitive, + FALSE, + 0, + FALSE + ); + + // + // Don't fail if the interrupt cannot be connected. + // + + KeConnectInterrupt( &HalpEisaNmiInterrupt ); + + // + // Clear the Eisa NMI disable bit. This bit is the high order of the + // NMI enable register. + // + + DataByte = 0; + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable, + DataByte + ); + +} + +BOOLEAN +HalHandleNMI( + IN PKINTERRUPT Interrupt, + IN PVOID ServiceContext + ) +/*++ + +Routine Description: + + This function is called when an EISA NMI occurs. It print the appropriate + status information and bugchecks. + +Arguments: + + Interrupt - Supplies a pointer to the interrupt object + + ServiceContext - Bug number to call bugcheck with. + +Return Value: + + Returns TRUE. + +--*/ +{ + UCHAR StatusByte; + +#ifdef IDLE_PROCESSOR + // + // Clear interrupt flag + // + + HalpInterruptReceived = 0; +#endif + + StatusByte = + READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiStatus); + + if (StatusByte & 0x80) { + HalDisplayString ("NMI: Parity Check / Parity Error\n"); + } + + if (StatusByte & 0x40) { + HalDisplayString ("NMI: Channel Check / IOCHK\n"); + } + + // + // This is an Sio machine, no extnded nmi information, so just do it. + // + + + KeBugCheck(NMI_HARDWARE_FAILURE); + return(TRUE); +} + +UCHAR +HalpAcknowledgeEisaInterrupt( + PVOID ServiceContext + ) +/*++ + +Routine Description: + + Acknowledge the EISA interrupt from the programmable interrupt controller. + Return the vector number of the highest priority pending interrupt. + +Arguments: + + ServiceContext - Service context of the interrupt service supplies + a pointer to the EISA interrupt acknowledge register. + +Return Value: + + Return the value of the highest priority pending interrupt. + +--*/ +{ + UCHAR InterruptVector; + +#ifdef IDLE_PROCESSOR + // + // Clear interrupt flag + // + + HalpInterruptReceived = 0; +#endif + + // + // Read the interrupt vector from the PIC. + // + + InterruptVector = READ_PORT_UCHAR(ServiceContext); + + return( InterruptVector ); + +} + +VOID +HalpAcknowledgeClockInterrupt( + VOID + ) +/*++ + +Routine Description: + + Acknowledge the clock interrupt from the interval timer. The interval + timer for EB66 comes from the Dallas real-time clock. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + +#ifdef IDLE_PROCESSOR + // + // Clear interrupt flag + // + + HalpInterruptReceived = 0; +#endif + + // + // Acknowledge the clock interrupt by reading the control register C of + // the Real Time Clock. + // + + HalpReadClockRegister( RTC_CONTROL_REGISTERC ); + + return; +} + +#ifdef IDLE_PROCESSOR +BOOLEAN +PreHalpSioDispatch( + VOID + ) +/*++ + +Routine Description: + + Acknowledge the PCI interrupt by clearing the interrupt flag, then + dispatch to the real PCI/SIO interrupt handler + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + + // + // Clear interrupt flag + // + + HalpInterruptReceived = 0; + + return HalpSioDispatch(); + +} +#endif + diff --git a/private/ntos/nthals/hallx3/alpha/lxmapio.c b/private/ntos/nthals/hallx3/alpha/lxmapio.c new file mode 100644 index 000000000..4ecab50a2 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/lxmapio.c @@ -0,0 +1,160 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + lxmapio.c + +Abstract: + + This module contains the functions to map HAL-accessed I/O addresses + on the Avanti system. + +Author: + + Joe Notarangelo 25-Oct-1993 + +Environment: + + Kernel mode + +Revision History: + + Wim Colgate 27-April-1995 + + Renamed for LX3. + + +--*/ + +#include "halp.h" +#include "lx3.h" +#include "pflash.h" + + +// +// Define global data used to locate the EISA control space. +// +// The reason these names seem strange, is because they are legacy names. +// + +PVOID HalpEisaControlBase; +PVOID HalpEisaIntAckBase; +PVOID HalpCMOSRamBase; + + +BOOLEAN +HalpMapIoSpace ( + VOID + ) + +/*++ + +Routine Description: + + This routine maps the HAL I/O space for an Avanti + system using the Quasi VA. + +Arguments: + + None. + +Return Value: + + If the initialization is successfully completed, than a value of TRUE + is returned. Otherwise, a value of FALSE is returned. + +--*/ + +{ + PVOID PciIoSpaceBase; + + // + // Map base addresses in QVA space. + // + + PciIoSpaceBase = HAL_MAKE_QVA( APECS_PCI_IO_BASE_PHYSICAL ); + + HalpEisaControlBase = PciIoSpaceBase; + HalpEisaIntAckBase = HAL_MAKE_QVA( APECS_PCI_INTACK_BASE_PHYSICAL ); + + // + // Map the real-time clock registers. + // + + HalpRtcAddressPort = (PVOID)((ULONG)PciIoSpaceBase + RTC_ISA_ADDRESS_PORT); + HalpRtcDataPort = (PVOID)((ULONG)PciIoSpaceBase + RTC_ISA_DATA_PORT); + + // + // Set the base offset of the NVRAM location inside the FLASH ROM + // + + HalpCMOSRamBase = (PVOID)NVRAM1_BASE; + + return TRUE; + +} + +ULONG +HalpMapDebugPort( + IN ULONG ComPort, + OUT PULONG ReadQva, + OUT PULONG WriteQva + ) +/*++ + +Routine Description: + + This routine maps the debug com port so that the kernel debugger + may function - if called it is called very earlier in the boot sequence. + +Arguments: + + ComPort - Supplies the number of the com port to use as the debug port. + + ReadQva - Receives the QVA used to access the read registers of the debug + port. + + WriteQva - Receives the QVA used to access the write registers of the + debug port. + +Return Value: + + Returns the base bus address of the device used as the debug port. + +--*/ +{ + ULONG ComPortAddress; + ULONG PortQva; + + // + // Compute the port address, based on the desired com port. + // + + switch( ComPort ){ + + case 1: + + ComPortAddress = COM1_ISA_PORT_ADDRESS; + break; + + case 2: + default: + + ComPortAddress = COM2_ISA_PORT_ADDRESS; + + } + + // + // Return the QVAs for read and write access. + // + + PortQva = (ULONG)HAL_MAKE_QVA(APECS_PCI_IO_BASE_PHYSICAL) + ComPortAddress; + + *ReadQva = PortQva; + *WriteQva = PortQva; + + return ComPortAddress; + +} diff --git a/private/ntos/nthals/hallx3/alpha/lxsgdma.c b/private/ntos/nthals/hallx3/alpha/lxsgdma.c new file mode 100644 index 000000000..f2f033fad --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/lxsgdma.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ebsgdma.c" + diff --git a/private/ntos/nthals/hallx3/alpha/lxsysint.c b/private/ntos/nthals/hallx3/alpha/lxsysint.c new file mode 100644 index 000000000..48a092204 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/lxsysint.c @@ -0,0 +1,394 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + ebinitnt.c + +Abstract: + + This module implements the HAL enable/disable system interrupt, and + request interprocessor interrupt routines for the Avanti system. + +Author: + + Joe Notarangelo 25-Oct-1993 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#include "halp.h" +#include "lx3.h" +#include "axp21064.h" + +// +// Define reference to the builtin device interrupt enables. +// + +extern USHORT HalpBuiltinInterruptEnable; + +#ifdef ALLOC_PRAGMA +#pragma alloc_text(PAGE,HalpGetSystemInterruptVector) +#endif + + +VOID +HalDisableSystemInterrupt ( + IN ULONG Vector, + IN KIRQL Irql + ) + +/*++ + +Routine Description: + + This routine disables the specified system interrupt. + +Arguments: + + Vector - Supplies the vector of the system interrupt that is disabled. + + Irql - Supplies the IRQL of the interrupting source. + +Return Value: + + None. + +--*/ + +{ + + ULONG Irq; + KIRQL OldIrql; + + // + // Raise IRQL to the highest level. + // + + KeRaiseIrql(HIGH_LEVEL, &OldIrql); + + // + // If the vector number is within the range of the ISA interrupts, then + // disable the ISA interrrupt. + // + + if (Vector >= ISA_VECTORS && + Vector < MAXIMUM_ISA_VECTOR && + Irql == ISA_DEVICE_LEVEL) { + HalpDisableSioInterrupt(Vector); + } + + // + // If the vector is a performance counter vector or one of the internal + // device vectors then disable the interrupt for the 21064. + // + + switch (Vector) { + + // + // Performance counter 0 interrupt (internal to 21064) + // + + case PC0_VECTOR: + case PC0_SECONDARY_VECTOR: + + HalpDisable21064PerformanceInterrupt( PC0_VECTOR ); + break; + + // + // Performance counter 1 interrupt (internal to 21064) + // + + case PC1_VECTOR: + case PC1_SECONDARY_VECTOR: + + HalpDisable21064PerformanceInterrupt( PC1_VECTOR ); + break; + + } //end switch Vector + + // + // Lower IRQL to the previous level. + // + + KeLowerIrql(OldIrql); + return; +} + +BOOLEAN +HalEnableSystemInterrupt ( + IN ULONG Vector, + IN KIRQL Irql, + IN KINTERRUPT_MODE InterruptMode + ) + +/*++ + +Routine Description: + + This routine enables the specified system interrupt. + +Arguments: + + Vector - Supplies the vector of the system interrupt that is enabled. + + Irql - Supplies the IRQL of the interrupting source. + + InterruptMode - Supplies the mode of the interrupt; LevelSensitive or + Latched. + +Return Value: + + TRUE if the system interrupt was enabled + +--*/ + +{ + BOOLEAN Enabled = FALSE; + ULONG Irq; + KIRQL OldIrql; + + // + // Raise IRQL to the highest level. + // + + KeRaiseIrql(HIGH_LEVEL, &OldIrql); + + // + // If the vector number is within the range of the ISA interrupts, then + // enable the ISA interrrupt and set the Level/Edge register. + // + + if (Vector >= ISA_VECTORS && + Vector < MAXIMUM_ISA_VECTOR && + Irql == ISA_DEVICE_LEVEL) { + HalpEnableSioInterrupt( Vector, InterruptMode ); + Enabled = TRUE; + } + + // + // If the vector is a performance counter vector or one of the + // internal device vectors then perform 21064-specific enable. + // + + switch (Vector) { + + // + // Performance counter 0 (internal to 21064) + // + + case PC0_VECTOR: + case PC0_SECONDARY_VECTOR: + + HalpEnable21064PerformanceInterrupt( PC0_VECTOR, Irql ); + Enabled = TRUE; + break; + + // + // Performance counter 1 (internal to 21064) + // + + case PC1_VECTOR: + case PC1_SECONDARY_VECTOR: + + HalpEnable21064PerformanceInterrupt( PC1_VECTOR, Irql ); + Enabled = TRUE; + break; + + } //end switch Vector + + // + // Lower IRQL to the previous level. + // + + KeLowerIrql(OldIrql); + return Enabled; +} + +ULONG +HalpGetSystemInterruptVector( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN ULONG BusInterruptLevel, + IN ULONG BusInterruptVector, + OUT PKIRQL Irql, + OUT PKAFFINITY Affinity + ) + +/*++ + +Routine Description: + + This function returns the system interrupt vector and IRQL level + corresponding to the specified bus interrupt level and/or vector. The + system interrupt vector and IRQL are suitable for use in a subsequent call + to KeInitializeInterrupt. + + We only use InterfaceType, and BusInterruptLevel. BusInterruptVector + for ISA and ISA are the same as the InterruptLevel, so ignore. + +Arguments: + + BusHandler - Registered BUSHANDLER for the target configuration space + + RootHandler - Registered BUSHANDLER for the orginating HalGetBusData + request. + + BusInterruptLevel - Supplies the bus specific interrupt level. + + BusInterruptVector - Supplies the bus specific interrupt vector. + + Irql - Returns the system request priority. + + Affinity - Returns the affinity for the requested vector + +Return Value: + + Returns the system interrupt vector corresponding to the specified device. + +--*/ + +{ + INTERFACE_TYPE InterfaceType = BusHandler->InterfaceType; + ULONG BusNumber = BusHandler->BusNumber; + + ULONG Vector; + + *Affinity = 1; + + switch (InterfaceType) { + + case ProcessorInternal: + + // + // Handle the internal defined for the processor itself + // and used to control the performance counters in the 21064. + // + + if( (Vector = HalpGet21064PerformanceVector( BusInterruptLevel, + Irql)) != 0 ){ + + // + // Performance counter was successfully recognized. + // + + return Vector; + + } else { + + // + // Unrecognized processor interrupt. + // + + *Irql = 0; + *Affinity = 0; + return 0; + + } //end if Vector + + break; + + case Isa: + + // + // Assumes all ISA devices coming in on same pin + // + + *Irql = ISA_DEVICE_LEVEL; + + // + // The vector is equal to the specified bus level plus the ISA_VECTOR. + // This is assuming that the ISA levels not assigned Interrupt Levels + // in the Beta programming guide are unused in the LCA system. + // Otherwise, need a different encoding scheme. + // + // Not all interrupt levels are actually supported on Beta; + // Should we make some of them illegal here? + + return(BusInterruptLevel + ISA_VECTORS); + break; + + + case Eisa: + + // + // Assumes all EISA devices coming in on same pin + // + + *Irql = EISA_DEVICE_LEVEL; + + // + // The vector is equal to the specified bus level plus the EISA_VECTOR. + // + + return(BusInterruptLevel + EISA_VECTORS); + break; + + case PCIBus: + + // + // Assumes all PCI devices coming in on same pin + // + + *Irql = ISA_DEVICE_LEVEL; + + // + // The vector is equal to the specified bus level plus the ISA_VECTOR + // + + return((BusInterruptLevel) + ISA_VECTORS); + + break; + + + + default: + + // + // Not an interface supported on EB66/Mustang systems + // + + *Irql = 0; + *Affinity = 0; + return(0); + break; + + } //end switch(InterfaceType) + +} + +VOID +HalRequestIpi ( + IN ULONG Mask + ) + +/*++ + +Routine Description: + + This routine requests an interprocessor interrupt on a set of processors. + This routine performs no function on an Avanti because it is a + uni-processor system. + +Arguments: + + Mask - Supplies the set of processors that are sent an interprocessor + interrupt. + +Return Value: + + None. + +--*/ + +{ + + return; +} diff --git a/private/ntos/nthals/hallx3/alpha/machdep.h b/private/ntos/nthals/hallx3/alpha/machdep.h new file mode 100644 index 000000000..542953086 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/machdep.h @@ -0,0 +1,44 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + machdep.h + +Abstract: + + This file includes the platform-dependent include files used to + build the HAL. + +Author: + + Joe Notarangelo 01-Dec-1993 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#ifndef _MACHDEP_ +#define _MACHDEP_ + +// +// Include Avanti platform-specific definitions. +// + +#include "lx3.h" + +// +// Include scatter/gather definitions. +// + +#include "ebsgdma.h" + +extern ULONG Am29F400NVRAMBase; + +#endif //_MACHDEP_ diff --git a/private/ntos/nthals/hallx3/alpha/memory.c b/private/ntos/nthals/hallx3/alpha/memory.c new file mode 100644 index 000000000..76b1eb7df --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/memory.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\memory.c" + diff --git a/private/ntos/nthals/hallx3/alpha/nvenv.c b/private/ntos/nthals/hallx3/alpha/nvenv.c new file mode 100644 index 000000000..8a8dfdeb5 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/nvenv.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\nvenv.c" + diff --git a/private/ntos/nthals/hallx3/alpha/nvram.c b/private/ntos/nthals/hallx3/alpha/nvram.c new file mode 100644 index 000000000..6fd93ab46 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/nvram.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\nvram.c" + diff --git a/private/ntos/nthals/hallx3/alpha/pcibus.c b/private/ntos/nthals/hallx3/alpha/pcibus.c new file mode 100644 index 000000000..9b5c260ea --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/pcibus.c @@ -0,0 +1,108 @@ +/*++ + + +Copyright (c) 1993 Microsoft Corporationn, Digital Equipment Corporation + +Module Name: + + pcibus.c + +Abstract: + + Platform-specific PCI bus routines + +Author: + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#include "halp.h" +#include "pci.h" +#include "pcip.h" +#include "machdep.h" + +// +// This references a boolean variable that identifies the APECS revision. +// + +extern ULONG PCIMaxBus; + + + +PCI_CONFIGURATION_TYPES +HalpPCIConfigCycleType( + IN PBUS_HANDLER BusHandler + ) +{ + if (BusHandler->BusNumber == 0) { + return PciConfigType0; + } else { + return PciConfigType1; + } +} + + +VOID +HalpPCIConfigAddr ( + IN PBUS_HANDLER BusHandler, + IN PCI_SLOT_NUMBER Slot, + PPCI_CFG_CYCLE_BITS pPciAddr + ) +{ + PCI_CONFIGURATION_TYPES ConfigType; + + ConfigType = HalpPCIConfigCycleType(BusHandler); + + if (ConfigType == PciConfigType0) + { + // + // Initialize PciAddr for a type 0 configuration cycle + // + // Device number is mapped to address bits 11:24, which, in APECS + // pass 1, are wired to IDSEL pins. In pass 2, the format of a type + // 0 cycle is the same as the format of a type 1. Note that + // HalpValidPCISlot has already done bounds checking on DeviceNumber. + // + // PciAddr can be intialized for different bus numbers + // with distinct configuration spaces here. + // + + pPciAddr->u.AsULONG = (ULONG) APECS_PCI_CONFIG_BASE_QVA; + pPciAddr->u.AsULONG += ( (Slot.u.bits.DeviceNumber) << 11 ); + pPciAddr->u.bits0.FunctionNumber = Slot.u.bits.FunctionNumber; + pPciAddr->u.bits0.Reserved1 = PciConfigType0; + +#if HALDBG + DbgPrint("HalpPCIConfigAddr: Type 0 PCI Config Access @ %x\n", pPciAddr->u.AsULONG); +#endif // DBG + + } + else + { + // + // Initialize PciAddr for a type 1 configuration cycle + // + // + + pPciAddr->u.AsULONG = (ULONG) APECS_PCI_CONFIG_BASE_QVA; + pPciAddr->u.bits1.BusNumber = BusHandler->BusNumber; + pPciAddr->u.bits1.FunctionNumber = Slot.u.bits.FunctionNumber; + pPciAddr->u.bits1.DeviceNumber = Slot.u.bits.DeviceNumber; + pPciAddr->u.bits1.Reserved1 = PciConfigType1; + +#if HALDBG + DbgPrint("Type 1 PCI Config Access @ %x\n", pPciAddr->u.AsULONG); +#endif // DBG + + } + + return; +} + + diff --git a/private/ntos/nthals/hallx3/alpha/pcisio.c b/private/ntos/nthals/hallx3/alpha/pcisio.c new file mode 100644 index 000000000..cf5f0f462 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/pcisio.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcisio.c" + diff --git a/private/ntos/nthals/hallx3/alpha/pcisup.c b/private/ntos/nthals/hallx3/alpha/pcisup.c new file mode 100644 index 000000000..360919f42 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/pcisup.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcisup.c" + diff --git a/private/ntos/nthals/hallx3/alpha/pcrtc.c b/private/ntos/nthals/hallx3/alpha/pcrtc.c new file mode 100644 index 000000000..2e57b87d6 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/pcrtc.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcrtc.c" + diff --git a/private/ntos/nthals/hallx3/alpha/pcserial.c b/private/ntos/nthals/hallx3/alpha/pcserial.c new file mode 100644 index 000000000..a2f159c48 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/pcserial.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcserial.c" + diff --git a/private/ntos/nthals/hallx3/alpha/pcspeakr.c b/private/ntos/nthals/hallx3/alpha/pcspeakr.c new file mode 100644 index 000000000..807b6f324 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/pcspeakr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcspeakr.c" + diff --git a/private/ntos/nthals/hallx3/alpha/perfcntr.c b/private/ntos/nthals/hallx3/alpha/perfcntr.c new file mode 100644 index 000000000..6c0a8f892 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/perfcntr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\perfcntr.c" + diff --git a/private/ntos/nthals/hallx3/alpha/pflash.c b/private/ntos/nthals/hallx3/alpha/pflash.c new file mode 100644 index 000000000..870902f60 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/pflash.c @@ -0,0 +1,91 @@ +/*++ + +Copyright (c) 1995 Digital Equipment Corporation + +Module Name: + + pflash.c + +Abstract: + + This module contains the platform dependent code to access the AMD + flash ROM part + +Author: + + Wim Colgate, 5/23/95 + +Environment: + + Firmware/Kernel mode + +Revision History: + +--*/ + +#include "halp.h" +#include "arccodes.h" +#include <flash8k.h> +#include "flashbus.h" +#include "am29f400.h" + + +VOID pWriteFlashByte( + IN ULONG FlashOffset, + IN UCHAR Data + ) +/*++ + +Routine Description: + + This routine goes writes the flashbus using the hardware + specific access method. + +Arguments: + + FlashOffset - offset within the flash ROM. + Data - data to write + +Return Value: + + The value of the flash at the given location. + +--*/ +{ + + WRITE_EPIC_REGISTER(FLASH_ACCESS_ADDR, + (FlashOffset << FLASH_ADDR_SHIFT) | Data + | FLASH_WRITE_FLAG); +} + + +UCHAR pReadFlashByte( + IN ULONG FlashOffset + ) +/*++ + +Routine Description: + + This routine goes out and reads the flashbus using the hardware + specific access method. + +Arguments: + + FlashOffset - offset within the flash ROM. + +Return Value: + + The value of the flash at the given location. + +--*/ +{ + ULONG ReturnVal; + + + WRITE_EPIC_REGISTER(FLASH_ACCESS_ADDR, + (FlashOffset << FLASH_ADDR_SHIFT)); + + ReturnVal = READ_EPIC_REGISTER(FLASH_ACCESS_ADDR); + + return (UCHAR)ReturnVal; +} diff --git a/private/ntos/nthals/hallx3/alpha/pflash.h b/private/ntos/nthals/hallx3/alpha/pflash.h new file mode 100644 index 000000000..3704e27d7 --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/pflash.h @@ -0,0 +1,31 @@ +// +// The AMD is a full megabyte broken into the following sectors: +// +// 0x00000 .. 0x03fff -- > SROM (not writable) +// 0x04000 .. 0x05fff -- > First 8K 'nvram' +// 0x06000 .. 0x07fff -- > Second 8K 'nvram' +// 0x08000 .. 0x0ffff -- > DROM (not writable) +// 0x10000 .. 0x1ffff -- > First 64K of ARC firmware +// 0x20000 .. 0x2ffff -- > Second 64K of ARC firmware +// 0x30000 .. 0x3ffff -- > Third 64K of ARC firmware +// 0x40000 .. 0x4ffff -- > Fourth 64K of ARC firmware +// 0x50000 .. 0x5ffff -- > Fifth 64K of ARC firmware +// 0x60000 .. 0x6ffff -- > Sixth 64K of ARC firmware +// 0x70000 .. 0x7ffff -- > Seventh 64K of ARC firmware + +// +// Name the blocks +// + +#include "am29f400.h" + +#define SROM_BASE SECTOR_1_BASE +#define NVRAM1_BASE SECTOR_2_BASE +#define NVRAM2_BASE SECTOR_3_BASE +#define DROM_BASE SECTOR_4_BASE +#define ARC_BASE SECTOR_5_BASE + +#define SROM_SECTOR_SIZE (SECTOR_2_BASE - SECTOR_1_BASE) +#define NVRAM1_SECTOR_SIZE (SECTOR_3_BASE - SECTOR_2_BASE) +#define NVRAM2_SECTOR_SIZE (SECTOR_4_BASE - SECTOR_3_BASE) +#define DROM_SECTOR_SIZE (SECTOR_5_BASE - SECTOR_4_BASE) diff --git a/private/ntos/nthals/hallx3/alpha/vga.c b/private/ntos/nthals/hallx3/alpha/vga.c new file mode 100644 index 000000000..764c585af --- /dev/null +++ b/private/ntos/nthals/hallx3/alpha/vga.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\vga.c" + |