1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
|
/*++
Copyright (c) 1993 Digital Equipment Corporation
Module Name:
alphaio.s
Abstract:
The module contains the functions to turn quasi virtual
addresses into an Alpha superpage virtual address
and then read or write based on the request.
(We are using EV4 64-bit superpage mode.)
Author:
Joe Notarangelo 25-Oct-1993
Environment:
Executes in kernel mode.
Revision History:
12-Jul-1994 - Eric Rehm - Added dense space I/O
27-July-1994 - Sameer Dekate
Make a common file for all machines and optimize Read/Write
register buffer routines. Made a common routine with different
entry points for READ & WRITE_REGISTER_BUFFER routines
--*/
#include "halalpha.h"
#include "apoc.h"
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
.struct 0
.space 8 // filler for octaword alignment
IoRa: .space 8 // space for return address
IoS0: .space 8 // space for S0
IoS1: .space 8 // space for S1
IoS2: .space 8 // space for S2
IoIrql: .space 8 // space for local variable
IoFrameLength: //
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
#define EV4_IO(FastIoRoutine) \
ldq t0, HalpPciDenseBasePhysicalSuperPage; \
ldl t1, HalpIoArchitectureType; \
beq t1, FastIoRoutine; \
and a0, DTI_QVA_SELECTORS, t1; \
xor t1, DTI_QVA_ENABLE, t1; \
bne t1, FastIoRoutine; \
lda sp, -IoFrameLength(sp); \
stq ra, IoRa(sp); \
stq s0, IoS0(sp); \
stq s1, IoS1(sp); \
stq s2, IoS2(sp); \
or a0, a0, s0; \
or a1, a1, s1; \
or a2, a2, s2; \
or zero, HIGH_LEVEL, a0; \
addq sp, IoIrql, a1; \
bsr ra, KeRaiseIrql; \
or s0, s0, a0; \
bsr ra, HalpMiniTlbResolve; \
or v0, v0, a0; \
or s1, s1, a1; \
or s2, s2, a2; \
ldq t0, HalpPciDenseBasePhysicalSuperPage; \
bsr ra, FastIoRoutine; \
or v0, v0, s0; \
ldq a0, IoIrql(sp); \
and a0, 0xff, a0; \
bsr ra, KeLowerIrql; \
or s0, s0, v0; \
ldq s2, IoS2(sp); \
ldq s1, IoS1(sp); \
ldq s0, IoS0(sp); \
ldq ra, IoRa(sp); \
lda sp, IoFrameLength(sp); \
ret zero, (ra)
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
LEAF_ENTRY(READ_REGISTER_UCHAR)
ALTERNATE_ENTRY(READ_PORT_UCHAR)
EV4_IO(EV5_READ_PORT_UCHAR)
.end READ_REGISTER_UCHAR
LEAF_ENTRY(READ_REGISTER_USHORT)
ALTERNATE_ENTRY(READ_PORT_USHORT)
EV4_IO(EV5_READ_PORT_USHORT)
.end READ_REGISTER_USHORT
LEAF_ENTRY(READ_REGISTER_ULONG)
ALTERNATE_ENTRY(READ_PORT_ULONG)
EV4_IO(EV5_READ_PORT_ULONG)
.end READ_REGISTER_ULONG
LEAF_ENTRY(WRITE_REGISTER_UCHAR)
ALTERNATE_ENTRY(WRITE_PORT_UCHAR)
EV4_IO(EV5_WRITE_PORT_UCHAR)
.end WRITE_REGISTER_UCHAR
LEAF_ENTRY(WRITE_REGISTER_USHORT)
ALTERNATE_ENTRY(WRITE_PORT_USHORT)
EV4_IO(EV5_WRITE_PORT_USHORT)
.end WRITE_REGISTER_USHORT
LEAF_ENTRY(WRITE_REGISTER_ULONG)
ALTERNATE_ENTRY(WRITE_PORT_ULONG)
EV4_IO(EV5_WRITE_PORT_ULONG)
.end WRITE_REGISTER_ULONG
LEAF_ENTRY(READ_PORT_BUFFER_UCHAR)
EV4_IO(EV5_READ_PORT_BUFFER_UCHAR)
.end READ_PORT_BUFFER_UCHAR
LEAF_ENTRY(READ_PORT_BUFFER_USHORT)
EV4_IO(EV5_READ_PORT_BUFFER_USHORT)
.end READ_PORT_BUFFER_USHORT
LEAF_ENTRY(READ_PORT_BUFFER_ULONG)
EV4_IO(EV5_READ_PORT_BUFFER_ULONG)
.end READ_PORT_BUFFER_ULONG
LEAF_ENTRY(WRITE_PORT_BUFFER_UCHAR)
EV4_IO(EV5_WRITE_PORT_BUFFER_UCHAR)
.end WRITE_PORT_BUFFER_UCHAR
LEAF_ENTRY(WRITE_PORT_BUFFER_USHORT)
EV4_IO(EV5_WRITE_PORT_BUFFER_USHORT)
.end WRITE_PORT_BUFFER_USHORT
LEAF_ENTRY(WRITE_PORT_BUFFER_ULONG)
EV4_IO(EV5_WRITE_PORT_BUFFER_ULONG)
.end WRITE_PORT_BUFFER_ULONG
LEAF_ENTRY(READ_REGISTER_BUFFER_UCHAR)
EV4_IO(EV5_READ_REGISTER_BUFFER_UCHAR)
.end READ_REGISTER_BUFFER_UCHAR
LEAF_ENTRY(READ_REGISTER_BUFFER_USHORT)
EV4_IO(EV5_READ_REGISTER_BUFFER_USHORT)
.end READ_REGISTER_BUFFER_USHORT
LEAF_ENTRY(READ_REGISTER_BUFFER_ULONG)
EV4_IO(EV5_READ_REGISTER_BUFFER_ULONG)
.end READ_REGISTER_BUFFER_ULONG
LEAF_ENTRY(WRITE_REGISTER_BUFFER_UCHAR)
EV4_IO(EV5_WRITE_REGISTER_BUFFER_UCHAR)
.end WRITE_REGISTER_BUFFER_UCHAR
LEAF_ENTRY(WRITE_REGISTER_BUFFER_USHORT)
EV4_IO(EV5_WRITE_REGISTER_BUFFER_USHORT)
.end WRITE_REGISTER_BUFFER_USHORT
LEAF_ENTRY(WRITE_REGISTER_BUFFER_ULONG)
EV4_IO(EV5_WRITE_REGISTER_BUFFER_ULONG)
.end WRITE_REGISTER_BUFFER_ULONG
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
SBTTL( "Read I/O byte" )
//++
//
// UCHAR
// READ_REGISTER_UCHAR(
// IN PVOID RegisterQva
// )
//
// Routine Description:
//
// Reads a byte location in PCI bus memory or I/O space.
//
// Arguments:
//
// RegisterQva(a0) - Supplies the QVA of the I/O byte to read.
//
// Return Value:
//
// v0 - Returns the value read from I/O space.
//
//--
LEAF_ENTRY(EV5_READ_REGISTER_UCHAR)
ALTERNATE_ENTRY(EV5_READ_PORT_UCHAR)
and a0, DTI_QVA_SELECTORS, t1 // get qva selector bits
and a0, 3, t3 // get byte we need if eisa
xor t1, DTI_QVA_ENABLE, t1 // ok iff DTI_QVA_ENABLE set in selectors
bne t1, 2f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 // t0 contains VA<33:0>
ldiq t4, -0x3080 // 0xffff ffff ffff cf80
sll t4, 28, t4 // 0xffff fcf8 0000 0000
or t0, t4, t0 // superpage mode
mb
ldl v0, (t0) // get the longword
extbl v0, t3, v0 // get correct byte if eisa
ret zero, (ra) // return
//
// Dense space access: QVA is an offset into dense space
//
2:
and a0, 3, t3 // get byte we need
zap a0, 0xf0, a0 // clear <63:32>
bic a0, 3, a0 // clear <1:0> to get aligned longword
// ldiq t0, PCI_DENSE_BASE_PHYSICAL_SUPERPAGE
or a0, t0, a0 // superpage mode: add offset to base
ldl v0, (a0) // get the longword
extbl v0, t3, v0 // get correct byte
ret zero, (ra) // return
.end EV5_READ_REGISTER_UCHAR
SBTTL( "Read I/O word(16 bits)" )
//++
//
// USHORT
// READ_REGISTER_USHORT(
// IN PVOID RegisterQva
// )
//
// Routine Description:
//
// Reads a word location in PCI bus memory or I/O space.
//
// Arguments:
//
// RegisterQva(a0) - Supplies the QVA of the I/O word to read.
//
// Return Value:
//
// v0 - Returns the value read from I/O space.
//
//--
LEAF_ENTRY(EV5_READ_REGISTER_USHORT)
ALTERNATE_ENTRY(EV5_READ_PORT_USHORT)
and a0, DTI_QVA_SELECTORS, t1 // get qva selector bits
and a0, 3, t3 // get word
xor t1, DTI_QVA_ENABLE, t1 // ok iff DTI_QVA_ENABLE set in selectors
bne t1, 2f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 //
ldiq t4, -0x3080 //
sll t4, 28, t4 //
or t0, t4, t0 // superpage mode
or t0, IO_WORD_LEN, t0 // or in the byte enables
mb
ldl v0, (t0) // get the longword
extwl v0,t3,v0 // get the correct word
ret zero, (ra) // return
//
// Dense space access: QVA is an offset into dense space
//
2:
and a0, 3, t3 // get word we need
zap a0, 0xf0, a0 // clear <63:32>
bic a0, 3, a0 // clear <1:0> to get aligned longword
// ldiq t0, PCI_DENSE_BASE_PHYSICAL_SUPERPAGE
or a0,t0, a0 // superpage mode: add offset to base
ldl v0, (a0) // get the longword
extwl v0, t3, v0 // get correct word
ret zero, (ra) // return
.end EV5_READ_REGISTER_USHORT
SBTTL( "Read I/O longword(32 bits)" )
//++
//
// ULONG
// READ_REGISTER_ULONG(
// IN PVOID RegisterQva
// )
//
// Routine Description:
//
// Reads a longword location in PCI bus memory or I/O space.
//
// Arguments:
//
// RegisterQva(a0) - Supplies the QVA of the I/O longword to read.
//
// Return Value:
//
// v0 - Returns the value read from I/O space.
//
//--
LEAF_ENTRY(EV5_READ_REGISTER_ULONG)
ALTERNATE_ENTRY(EV5_READ_PORT_ULONG)
and a0, DTI_QVA_SELECTORS, t1 // get qva selector bits
xor t1, DTI_QVA_ENABLE, t1 // ok iff DTI_QVA_ENABLE set in selectors
bne t1, 2f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 //
ldiq t4, -0x3080 //
sll t4, 28, t4 //
or t0, t4, t0 // superpage mode
or t0, IO_LONG_LEN, t0 // or in the byte enables
mb
ldl v0, (t0) // read the longword
ret zero, (ra) // return
//
// Dense space access: QVA is an offset into dense space
//
2:
zap a0, 0xf0, a0 // clear <63:32>
// ldiq t0, PCI_DENSE_BASE_PHYSICAL_SUPERPAGE
or a0, t0, a0 // superpage mode: add offset to base
ldl v0, (a0) // get the longword
ret zero, (ra) // return
.end EV5_READ_REGISTER_ULONG
SBTTL( "Write I/O byte" )
//++
//
// VOID
// WRITE_REGISTER_UCHAR(
// IN PVOID RegisterQva,
// IN UCHAR Value
// )
//
// Routine Description:
//
// Writes a byte location in PCI bus memory or I/O space.
//
// Arguments:
//
// RegisterQva(a0) - Supplies the QVA of the I/O byte to write.
//
// Value(a1) - Supplies the value written to I/O space.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_WRITE_REGISTER_UCHAR)
ALTERNATE_ENTRY(EV5_WRITE_PORT_UCHAR)
and a0, DTI_QVA_SELECTORS, t1 // get qva selector bits
and a0, 3, t3 // get byte we need if eisa
xor t1, DTI_QVA_ENABLE, t1 // ok iff DTI_QVA_ENABLE set in selectors
bne t1, 2f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 // t0 contains VA<33:0>
ldiq t4, -0x3080 //
sll t4, 28, t4 //
or t0, t4, t0 // superpage mode
insbl a1,t3,t4 // put the byte in the correct position
stl t4, (t0) // write the byte
mb // order the write
ret zero, (ra) // return
//
// Dense space access: QVA is an offset into dense space
//
2:
and a0, 3, t3 // get byte we need if eisa
zap a0, 0xf0, a0 // clear <63:32>
bic a0, 3, a0 // clear <1:0> to get aligned longword
// ldiq t0, PCI_DENSE_BASE_PHYSICAL_SUPERPAGE
or a0, t0, a0 // superpage mode: add offset to base
ldl t1, (a0) // get the long
mskbl t1, t3, t1 // mask the proper byte
insbl a1, t3, t2 // put byte into position
bis t1, t2, t1 // merge byte in result
stl t1, (a0) // store the result
mb // order the write
ret zero, (ra) // return
.end EV5_WRITE_REGISTER_UCHAR
SBTTL( "Write I/O word (16 bits)" )
//++
//
// VOID
// WRITE_REGISTER_USHORT(
// IN PVOID RegisterQva,
// IN USHORT Value
// )
//
// Routine Description:
//
// Writes a word location in PCI bus memory or I/O space.
//
// Arguments:
//
// RegisterQva(a0) - Supplies the QVA of the I/O word to write.
//
// Value(a1) - Supplies the value written to I/O space.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_WRITE_REGISTER_USHORT)
ALTERNATE_ENTRY(EV5_WRITE_PORT_USHORT)
and a0, DTI_QVA_SELECTORS, t1 // get qva selector bits
and a0, 3, t3 // get word
xor t1, DTI_QVA_ENABLE, t1 // ok iff DTI_QVA_ENABLE set in selectors
bne t1, 2f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 //
ldiq t4, -0x3080 //
sll t4, 28, t4 //
or t0, t4, t0 // superpage mode
or t0, IO_WORD_LEN, t0 // or in the byte enables
inswl a1,t3,t2 // put the word in the correct place
stl t2, (t0) // write the word
mb // order the write
ret zero, (ra) // return
//
// Dense space access: QVA is an offset into dense space
//
2:
and a0, 3, t3 // get byte we need if eisa
zap a0, 0xf0, a0 // clear <63:32>
bic a0, 3, a0 // clear <1:0> to get aligned longword
// ldiq t0, PCI_DENSE_BASE_PHYSICAL_SUPERPAGE
or a0, t0, a0 // superpage mode: add offset to base
ldl t1, (a0) // get the long
mskwl t1, t3, t1 // mask the proper word
inswl a1, t3, t2 // put word into position
bis t1, t2, t1 // merge in result
stl t1, (a0) // store the result
mb // order the write
ret zero, (ra) // return
.end EV5_WRITE_REGISTER_USHORT
SBTTL( "Write I/O longword (32 bits)" )
//++
//
// VOID
// WRITE_REGISTER_ULONG(
// IN PVOID RegisterQva,
// IN ULONG Value
// )
//
// Routine Description:
//
// Writes a longword location in PCI bus memory or I/O space.
//
// Arguments:
//
// RegisterQva(a0) - Supplies the QVA of the I/O longword to write.
//
// Value(a1) - Supplies the value written to I/O space.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_WRITE_REGISTER_ULONG)
ALTERNATE_ENTRY(EV5_WRITE_PORT_ULONG)
and a0, DTI_QVA_SELECTORS, t1 // get qva selector bits
xor t1, DTI_QVA_ENABLE, t1 // ok iff DTI_QVA_ENABLE set in selectors
bne t1, 2f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 //
ldiq t4, -0x3080 //
sll t4, 28, t4 //
or t0, t4, t0 // superpage mode
or t0, IO_LONG_LEN, t0 // or in the byte enables
stl a1, (t0) // write the longword
mb // order the write
ret zero, (ra) // return
//
// Dense space access: QVA is an offset into dense space
//
2:
zap a0, 0xf0, a0 // clear <63:32>
// ldiq t0, PCI_DENSE_BASE_PHYSICAL_SUPERPAGE
or a0, t0, a0 // superpage mode: add offset to base
stl a1, (a0) // store the longword
mb // order the write
ret zero, (ra) // return
.end EV5_WRITE_REGISTER_ULONG
//++
//
// VOID
// READ_PORT_BUFFER_UCHAR(
// IN PVOID PortQva,
// IN PUCHAR Buffer,
// IN ULONG Count
// )
//
// Routine Description:
//
// Read multiple bytes from the specified port address into the
// destination buffer.
//
// Arguments:
//
// PortQva(a0) - Supplies the QVA of the port to read.
//
// Buffer(a1) - Supplies a pointer to the buffer to fill with
// the data read from the port.
//
// Count(a2) - Supplies the number of bytes to read.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_READ_PORT_BUFFER_UCHAR)
and a0, 3, t3 // get byte we need if eisa
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 // t0 contains VA<33:0>
ldiq t4, -0x3080 // t4=ffff ffff ffff c000
sll t4, 28, t4 // t4=ffff fc00 0000 0000
or t0, t4, t0 // superpage mode
beq a2, 3f // if count==0 return
2:
ldl v0, (t0) // get the longword
subl a2, 1, a2 // decrement count
extbl v0,t3,v0 // get the correct byte
stb v0,(a1) // cheat and let the assembler do it
addl a1, 1, a1 // next byte in buffer
bne a2, 2b // while count != 0
3:
ret zero, (ra) // return
.end EV5_READ_PORT_BUFFER_UCHAR
SBTTL( "Read Buffer from Port Space in Ushorts")
//++
//
// VOID
// READ_PORT_BUFFER_USHORT(
// IN PVOID PortQva,
// IN PUSHORT Buffer,
// IN ULONG Count
// )
//
// Routine Description:
//
// Read multiple words from the specified port address into the
// destination buffer.
//
// Arguments:
//
// PortQva(a0) - Supplies the QVA of the port to read.
//
// Buffer(a1) - Supplies a pointer to the buffer to fill with
// the data read from the port.
//
// Count(a2) - Supplies the number of words to read.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_READ_PORT_BUFFER_USHORT)
and a0, 3, t3 // get word we need
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 // t0 contains VA<33:0>
ldiq t4, -0x3080 // t4=ffff ffff ffff c000
sll t4, 28, t4 // t4=ffff fc00 0000 0000
or t0, t4, t0 // superpage mode
or t0, IO_WORD_LEN, t0 // or in the byte enables
beq a2, 3f // if count==0 return
2:
ldl v0, (t0) // get the longword
subl a2, 1, a2 // decrement count
extwl v0,t3,v0 // get the correct word
stw v0,(a1) // cheat and let the assembler do it
addl a1, 2, a1 // next word in buffer
bne a2, 2b // while count != 0
3:
ret zero, (ra) // return
.end EV5_READ_PORT_BUFFER_USHORT
SBTTL( "Read Buffer from Port Space in Ulongs")
//++
//
// VOID
// READ_PORT_BUFFER_ULONG(
// IN PVOID PortQva,
// IN PULONG Buffer,
// IN ULONG Count
// )
//
// Routine Description:
//
// Read multiple longwords from the specified port address into the
// destination buffer.
//
// Arguments:
//
// PortQva(a0) - Supplies the QVA of the port to read.
//
// Buffer(a1) - Supplies a pointer to the buffer to fill with
// the data read from the port.
//
// Count(a2) - Supplies the number of longwords to read.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_READ_PORT_BUFFER_ULONG)
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 // t0 contains VA<33:0>
ldiq t4, -0x3080 // t4=ffff ffff ffff c000
sll t4, 28, t4 // t4=ffff fc00 0000 0000
or t0, t4, t0 // superpage mode
or t0, IO_LONG_LEN, t0 // or in the byte enables
beq a2, 3f // if count==0 return
2:
ldl v0, (t0) // get the longword
subl a2, 1, a2 // decrement count
stl v0,(a1) // cheat and let the assembler do it
addl a1, 4, a1 // next word in buffer
bne a2, 2b // while count != 0
3:
ret zero, (ra) // return
.end EV5_READ_PORT_BUFFER_ULONG
SBTTL( "Write Buffer to Port Space in Uchars")
//++
//
// VOID
// WRITE_PORT_BUFFER_UCHAR(
// IN PVOID PortQva,
// IN PUCHAR Buffer,
// IN ULONG Count
// )
//
// Routine Description:
//
// Write multiple bytes from the source buffer to the specified port
// address.
//
// Arguments:
//
// PortQva(a0) - Supplies the QVA of the port to write.
//
// Buffer(a1) - Supplies a pointer to the buffer containing the data
// to write to the port.
//
// Count(a2) - Supplies the number of bytes to write.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_WRITE_PORT_BUFFER_UCHAR)
and a0, 3, t3 // get byte we need if eisa
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 // t0 contains VA<33:0>
ldiq t4, -0x3080 // t4=ffff ffff ffff c000
sll t4, 28, t4 // t4=ffff fc00 0000 0000
or t0, t4, t0 // superpage mode
beq a2, 3f // if count==0 return
2:
ldq_u t1, 0(a1) // get quad surrounding byte
subl a2, 1, a2 // decrement count
extbl t1, a1, t1 // extract appropriate byte
addl a1, 1, a1 // increment buffer pointer
insbl t1, t3, t1 // put byte to appropriate lane
stl t1, 0(t0) // store to port
mb // push writes off chip
bne a2, 2b // while count != 0
3:
ret zero, (ra) // return
.end EV5_WRITE_PORT_BUFFER_UCHAR
SBTTL( "Write Buffer to Port Space in Ushorts")
//++
//
// VOID
// WRITE_PORT_BUFFER_USHORT(
// IN PVOID PortQva,
// IN PSHORT Buffer,
// IN ULONG Count
// )
//
// Routine Description:
//
// Write multiple words from the source buffer to the specified port
// address.
//
// Arguments:
//
// PortQva(a0) - Supplies the QVA of the port to write.
//
// Buffer(a1) - Supplies a pointer to the buffer containing the data
// to write to the port.
//
// Count(a2) - Supplies the number of words to write.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_WRITE_PORT_BUFFER_USHORT)
and a0, 3, t3 // get word we need
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 // t0 contains VA<33:0>
ldiq t4, -0x3080 // t4=ffff ffff ffff c000
sll t4, 28, t4 // t4=ffff fc00 0000 0000
or t0, t4, t0 // superpage mode
or t0, IO_WORD_LEN, t0 // or in the byte enables
beq a2, 3f // if count==0 return
2:
ldq_u t1, 0(a1) // get quad surrounding word
subl a2, 1, a2 // decrement count
extwl t1, a1, t1 // extract appropriate word
addl a1, 2, a1 // increment buffer pointer
inswl t1, t3, t1 // put word in appropriate lane
stl t1, 0(t0) // store to port
mb // push writes off chip
bne a2, 2b // while count != 0
3:
ret zero, (ra) // return
.end EV5_WRITE_PORT_BUFFER_USHORT
SBTTL( "Write Buffer to Port Space in Ulongs")
//++
//
// VOID
// WRITE_PORT_BUFFER_ULONG(
// IN PVOID PortQva,
// IN PULONG Buffer,
// IN ULONG Count
// )
//
// Routine Description:
//
// Write multiple longwords from the source buffer to the specified port
// address.
//
// Arguments:
//
// PortQva(a0) - Supplies the QVA of the port to write.
//
// Buffer(a1) - Supplies a pointer to the buffer containing the data
// to write to the port.
//
// Count(a2) - Supplies the number of longwords to write.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_WRITE_PORT_BUFFER_ULONG)
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 // t0 contains VA<33:0>
ldiq t4, -0x3080 // t4=ffff ffff ffff c000
sll t4, 28, t4 // t4=ffff fc00 0000 0000
or t0, t4, t0 // superpage mode
or t0, IO_LONG_LEN, t0 // or in the byte enables
beq a2, 3f // if count==0 return
2:
ldl t1, 0(a1) // a1 must be longword aligned
subl a2, 1, a2 // decrement count
stl t1, 0(t0) // store to port
mb // push writes off chip
addl a1, 4, a1 // increment buffer
bne a2, 2b // while count != 0
3:
ret zero, (ra) // return
.end EV5_WRITE_PORT_BUFFER_ULONG
SBTTL( "Read Buffer from PCI Memory Space in Uchars")
//++
//
// VOID
// READ_REGISTER_BUFFER_UXXXXX(
// IN PVOID RegisterQva,
// IN PUCHAR Buffer,
// IN ULONG Count
// )
//
// Routine Description:
//
// Copies a buffer from PCI Memory Space to an in-memory buffer.
//
// Arguments:
//
// RegisterQva(a0) - Supplies the starting QVA of the memory space buffer.
//
// Buffer(a1) - Supplies a pointer to the in-memory buffer to receive
// the copied data.
//
// Count(a2) - Supplies the number of bytes, words or longwords to write.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_READ_REGISTER_BUFFER_ULONG)
sll a2, 1, a2 // convert number of longs to words
ALTERNATE_ENTRY(EV5_READ_REGISTER_BUFFER_USHORT)
sll a2, 1, a2 // convert number of words to chars
ALTERNATE_ENTRY(EV5_READ_REGISTER_BUFFER_UCHAR)
and a0, DTI_QVA_SELECTORS, t1 // get qva selector bits
xor t1, DTI_QVA_ENABLE, t1 // ok iff DTI_QVA_ENABLE set in selectors
beq t1, 1f // if (eq) go do sparse space
//
// Dense space access: QVA is an offset into dense space
// Set IO address in t0
//
zap a0, 0xf0, a0 // clear <63:32>
// ldiq t0, PCI_DENSE_BASE_PHYSICAL_SUPERPAGE
or a0, t0, t0 // superpage mode: add offset to base
ldil a3, 1 // Offset to next byte
ldil a4, 4 // Offset to next long
ldil a5, 0 // LONG LEN ENABLE
br zero 2f // go do the actual transfer
//
// Sparse memory
// Set IO address in t0
//
1:
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 // t0 contains VA<33:0>
ldiq t4, -0x3080 // 0xffff ffff ffff c000
sll t4, 28, t4 // 0xffff fc00 0000 0000
or t0, t4, t0 // superpage mode
ldil a3, IO_BYTE_OFFSET // Offset to next byte
ldil a4, IO_LONG_OFFSET // Offset to next long
ldil a5, IO_LONG_LEN // LONG LEN ENABLE
//
// Do the ACTUAL TRANSFER
// a2 = count in characters
//
2:
beq a2, 60f // if count == 0 goto 60f (return)
//
// Check alignment of src and destn
//
and a0, 3, t3 // source alignment = t3
and a1, 3, t2 // destination alignment = t2
xor t2, t3, t4 // t4 = t2 xor t3
bne t4, 70f // if (t4!=0) do unaligned copy
// else do byte copies till alignment
beq t3, 20f // if t3==0 go do long word copies
// else do byte copies till alignment
//
// Src and Destn are not longword aligned but have same alignment
// (sympathetically aligned) copy till alignment
//
10:
beq a2, 60f // if count == 0 goto 60f (return)
ldl v0, 0(t0) // get the longword
subl a2, 1, a2 // decrement count
extbl v0, t3,v0 // get the correct byte
stb v0, (a1) // cheat and let the assembler do it
addq t0, a3, t0 // next I/O address
addl a1, 1, a1 // next byte in buffer
addl t3, 1, t3 // next byte in lane
and t3, 3, t3 // longword lanes
bne t3, 10b // while unaligned
//
// Src and Destn have same alignment and are longword aligned
//
20:
srl a2, 2, t3 // t3= #longwords to move
beq t3, 40f // if #longwords == 0 goto 40f
or t0, a5, t0 // We will now do LONG READS
30:
ldl v0, 0(t0) // get the longword
subl t3, 1, t3 // decrement long word count
stl v0, (a1) // store the longword at destn
addq t0, a4, t0 // next I/O address
addl a1, 4, a1 // next longword in buffer
bne t3, 30b // while #longwords > 0
//
// Do byte copies of remaining data uncopied
//
bic t0, a5, t0 // We will now do BYTE READS
40:
and a2, 3, a2 // remaining Bytes to copy
beq a2, 60f // if count == 0 goto 60f
50:
ldl v0, 0(t0) // get the longword
subl a2, 1, a2 // decrement count
extbl v0, t3,v0 // get the correct byte
stb v0, (a1) // cheat and let the assembler do it
addl a1, 1, a1 // next byte in buffer
addq t0, a3, t0 // next I/O address
addl t3, 1, t3 // next byte in lane
and t3, 3, t3 // longword lanes
bne a2, 50b // while count > 0
60:
ret zero, (ra) // return
//
// source IO alignment != destination memory alignment
// move enough bytes to longword align the IO source
// then move 32bit (longwords) storing unaligned into memory
// then move residual bytes
//
// Align src IO addresses; unaligned destn memory
//
70:
beq t3, 90f // branch if source is long aligned
//
// Move bytes until IO src is at a longword boundary or bytes exhausted
//
80:
beq a2, 130f // if count == 0 goto 130f (return)
ldl v0, 0(t0) // get the longword
subl a2, 1, a2 // decrement count
extbl v0, t3,v0 // get the correct byte
stb v0, (a1) // cheat and let the assembler do it
addl a1, 1, a1 // next byte in buffer
addq t0, a3, t0 // next I/O address
addl t3, 1, t3 // next byte in lane
and t3, 3, t3 // longword lanes
bne t3, 80b // while unaligned
//
// aligned IO source, unaligned memory destination
//
90:
srl a2, 3, t3 // quadwords to move
beq t3, 110f // if no quads finish with bytes copies
or t0, a5, t0 // We will now do LONG READS
100:
//
// Decoding for Comment:
// S= sign, X= overwritten byte, V= Valid byte,assume destn align a1= 2
//
ldl t1, 0(t0) // load LW 0 from IO src SSSS 4321
ldq_u t4, 0(a1) // load destn merge XXVV VVVV
ldq_u t5, 7(a1) // load destn next merge VVXX XXXX
subl t3, 1, t3 // decrement quadwords to move
addq t0, a4, t0 // add LONG OFFSET to t0
ldl t2, 0(t0) // load LW 1 from IO src SSSS 8765
mskql t4, a1, t4 // mask low LW for merge 00VV VVVV
mskqh t5, a1, t5 // mask high LW for merge VV00 0000
zap t1, 0xf0, t1 // clear high LW for long 0 0000 4321
sll t2, 32, t2 // get long 1 to high longword 8765 0000
bis t1, t2, t1 // merge read quadword together8765 4321
addq t0, a4, t0 // increment to next long
insql t1, a1, t6 // position low QW for merge 2100 0000
insqh t1, a1, t7 // position high QW for merge 0087 6543
bis t4, t6, t4 // merge new data, low QW 21VV VVVV
bis t5, t7, t5 // merge new data, high QW VV87 6543
stq_u t5, 7(a1) // write high quadword
stq_u t4, 0(a1) // write low quadword
lda a1, 8(a1) // increment memory pointer
bne t3, 100b // while quadwords to move
//
// Do byte copies of the remaining data not yet copied
//
bic t0, a5, t0 // We will now do BYTE READS
110:
and a2, 7, a2 // remaining bytes to copy
beq a2, 130f // if count == 0 goto 130f (return)
120:
ldl v0, 0(t0) // get the longword
subl a2, 1, a2 // decrement count
extbl v0, t3,v0 // get the correct byte
stb v0, (a1) // cheat and let the assembler do it
addl a1, 1, a1 // next byte in buffer
addq t0, a3, t0 // next I/O address
addl t3, 1, t3 // next byte in lane
and t3, 3, t3 // longword lanes
bne a2, 120b // while count != 0
130:
ret zero, (ra) // return
.end EV5_READ_REGISTER_BUFFER_ULONG // end for UCHAR & USHORT
SBTTL( "Write Buffer to PCI Memory Space in Uchars")
//++
//
// VOID
// WRITE_REGISTER_BUFFER_UXXXXX(
// IN PVOID RegisterQva,
// IN PUCHAR Buffer,
// IN ULONG Count
// )
//
// Routine Description:
//
// Copies an in-memory buffer to a PCI Memory Space buffer.
//
// Arguments:
//
// RegisterQva(a0) - Supplies the starting QVA of the memory space buffer.
//
// Buffer(a1) - Supplies a pointer to the in-memory source buffer.
//
// Count(a2) - Supplies the number of bytes, words to longwords to write.
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(EV5_WRITE_REGISTER_BUFFER_ULONG)
sll a2, 1, a2 // convert number of longs to words
ALTERNATE_ENTRY(EV5_WRITE_REGISTER_BUFFER_USHORT)
sll a2, 1, a2 // convert number of words to chars
ALTERNATE_ENTRY(EV5_WRITE_REGISTER_BUFFER_UCHAR)
and a0, DTI_QVA_SELECTORS, t1 // get qva selector bits
xor t1, DTI_QVA_ENABLE, t1 // ok iff DTI_QVA_ENABLE set in selectors
beq t1, 1f // if (eq) go do sparse space
//
// Dense space access: QVA is an offset into dense space
// Set IO address in t0
//
zap a0, 0xf0, a0 // clear <63:32>
// ldiq t0, PCI_DENSE_BASE_PHYSICAL_SUPERPAGE
or a0, t0, t0 // superpage mode: add offset to base
ldil a3, 1 // Offset to next byte
ldil a4, 4 // Offset to next long
ldil a5, 0 // LONG LEN ENABLE
br zero, 2f // go do the actual transfer
//
// Sparse Space
// Set IO address in t0
//
1:
zap a0, 0xf0, a0 // clear <63:32>
bic a0, DTI_QVA_ENABLE,a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0 // t0 contains VA<33:0>
ldiq t4, -0x3080 // 0xffff ffff ffff c000
sll t4, 28, t4 // 0xffff fc00 0000 0000
or t0, t4, t0 // superpage mode
ldil a3, IO_BYTE_OFFSET // Offset to next byte
ldil a4, IO_LONG_OFFSET // Offset to next long
ldil a5, IO_LONG_LEN // LONG LEN ENABLE
//
// Do the ACTUAL TRANSFER
// a2 = count in characters
//
2:
beq a2, 60f // if count == 0 goto 60f (return)
//
// Check alignment of src and destn
//
and a0, 3, t3 // destn alignment = t3
and a1, 3, t2 // src alignment = t2
xor t2, t3, t4 // t4 = t2 xor t3
bne t4, 70f // if (t4!=0) do unaligned copy
// else do byte copies till alignment
beq t3, 20f // if t3==0 go do longword copies
// else do byte copies till alignment
//
// Src and Destn are not longword aligned but have same alignment
// (sympathetically aligned) copy till alignment
//
10:
beq a2, 60f // if count == 0 goto 60f (return)
ldq_u t1, 0(a1) // get quad surrounding byte
subl a2, 1, a2 // decrement count
extbl t1, a1, t1 // extract appropriate byte
addl a1, 1, a1 // increment buffer pointer
insbl t1, t3, t1 // get proper lane
stl t1, 0(t0) // store byte to buffer (BYTE ENABLED)
addq t0, a3, t0 // increment I/O buffer
addl t3, 1, t3 // increment bytelane
and t3, 3, t3 // longwords only
bne t3, 10b // loop while not long aligned
//
// Src and Destn have same alignment and are longword aligned
//
20:
srl a2, 2, t3 // t3= #longwords to move
beq t3, 40f // if #longwords == 0 goto 40f
or t0, a5, t0 // We will now do LONG WRITE
30:
ldl t1, 0(a1) // get the longword
addl a1, 4, a1 // increment buffer pointer
subl t3, 1, t3 // decrement #longwords by 1
stl t1, 0(t0) // store long to buffer
addq t0, a4, t0 // increment I/O buffer
bne t3, 30b // while #longwords > 0
//
// Do byte copies of remaining data uncopied
//
bic t0, a5, t0 // Stop doing LONG WRITE
40:
and a2, 3, a2 // remaining Bytes to copy
beq a2, 60f // if count == 0 goto 60f (return)
50:
ldq_u t1, 0(a1) // get quad surrounding byte
subl a2, 1, a2 // decrement count
extbl t1, a1, t1 // extract appropriate byte
addl a1, 1, a1 // increment buffer pointer
insbl t1, t3, t1 // get proper lane
stl t1, 0(t0) // store to buffer
addq t0, a3, t0 // increment I/O buffer
addl t3, 1, t3 // increment bytelane
and t3, 3, t3 // longwords only
bne a2, 50b // while count != 0
60:
mb // push writes off chip
ret zero, (ra) // return
//
// destn IO alignment != Src memory alignment
// move enough bytes to longword align the IO destn
// then move 32bit (longwords) reading unaligned data from memory
// then move residual bytes
//
70:
beq t3, 90f // branch if destn is long aligned
//
// Move bytes until IO destn is at a longword boundary or bytes exhausted
//
80:
beq a2, 130f // if count == 0 goto 130f (return)
ldq_u t1, 0(a1) // get quad surrounding byte
extbl t1, a1, t1 // extract appropriate byte
insbl t1, t3, t1 // get proper lane
stl t1, 0(t0) // store byte to buffer (BYTE ENABLED)
subl a2, 1, a2 // decrement count
addl a1, 1, a1 // increment buffer pointer
addq t0, a3, t0 // increment I/O buffer
addl t3, 1, t3 // increment bytelane
and t3, 3, t3 // longwords only
bne t3, 80b // loop if not long aligned
//
// aligned IO destn, unaligned memory src
//
90:
srl a2, 3, t3 // t3 = quadwords to move
beq t3, 110f // if no quads finish with bytes copies
or t0, a5, t0 // We will now do LONG WRITES
100:
ldq_u t1, 0(a1) // load low source quadword
ldq_u t2, 7(a1) // load high source quadword
extql t1, a1, t1 // extract low portion of quadword
extqh t2, a1, t2 // extract high portion of quadword
or t1, t2, t1 // merge to get the source quadword
stl t1, 0(t0) // store the long word (LONG ENABLED)
lda a1, 8(a1) // next source quadword
srl t1, 32, t1 // get high longword into position
subl t3, 1, t3 // decrement number of quadwords to move
addq t0, a4, t0 // add LONG OFFSET to t0
stl t1, (t0) // store the second long word
addq t0, a4, t0 // increment to next dest. long
bne t3, 100b // while quadwords to move
//
// Do byte copies of the remaining data not yet copied
//
bic t0, a5, t0 // We will now do BYTE WRITES
110:
and a2, 7, a2 // remaining Bytes to copy
beq a2, 130f // if count == 0 goto 130f (return)
120:
ldq_u t1, 0(a1) // get quad surrounding byte
subl a2, 1, a2 // decrement count
extbl t1, a1, t1 // extract appropriate byte
addl a1, 1, a1 // increment buffer pointer
insbl t1, t3, t1 // get proper lane
stl t1, 0(t0) // store byte to buffer (BYTE ENABLED)
addq t0, a3, t0 // increment I/O buffer
addl t3, 1, t3 // increment bytelane
and t3, 3, t3 // longwords only
bne a2, 120b // while count != 0
130:
mb // push writes off chip
ret zero, (ra) // return
.end EV5_WRITE_REGISTER_BUFFER_ULONG // end for UCHAR & USHORT
//++
//
// VOID
// HalpWriteAbsoluteUlong(
// IN ULONG HighPart,
// IN ULONG LowPart,
// IN ULONG Value
// )
//
// Routine Description:
//
// Writes Value to the processor address given in HighPart and LowPart.
//
// Arguments:
//
// HighPart(a0) - Upper 32 bits of address
//
// LowPart(a1) - Lower 32 bits of address
//
// Value(a2) - Value to write
//
// Return Value:
//
// None.
//
//--
LEAF_ENTRY(HalpWriteAbsoluteUlong)
sll a0, 32, t0 // Shift Upper 32 bits of address into position
zap t0, 0x0f, t0 // Clear lower 32 bits of shifted address
zap a1, 0xf0, a1 // Clear upper 32 of lower part of address
or a1, t0, t0 // Build 64 bit address
stl a2, 0x0(t0) // Write value to address
mb // Memory Barrier
ret zero, (ra) // return
.end HalpWriteAbsoluteUlong
//++
//
// ULONG
// HalpReadAbsoluteUlong(
// IN ULONG HighPart,
// IN ULONG LowPart
// )
//
// Routine Description:
//
// Reads a value from the processor address given in HighPart and LowPart.
//
// Arguments:
//
// HighPart(a0) - Upper 32 bits of address
//
// LowPart(a1) - Lower 32 bits of address
//
// Return Value:
//
// 32 bit value read from the processor address.
//
//--
LEAF_ENTRY(HalpReadAbsoluteUlong)
sll a0, 32, t0 // Shift Upper 32 bits of address into position
zap t0, 0x0f, t0 // Clear lower 32 bits of shifted address
zap a1, 0xf0, a1 // Clear upper 32 of lower part of address
or a1, t0, t0 // Build 64 bit address
mb // Memory Barrier
ldl v0, 0x0(t0) // Read value from address
ret zero, (ra) // return
.end HalpReadAbsoluteUlong
|