1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
|
/*++
Copyright (c) 1993 Digital Equipment Corporation
Module Name:
sableio.s
Abstract:
This contains assembler code routines for the Sable system.
The module contains the functions to turn quasi virtual
addresses into an Alpha superpage virtual address
and then read or write based on the request.
(We are using EV4 64-bit superpage mode.)
Author:
Joe Notarangelo 25-Oct-1993
Environment:
Executes in kernel mode.
Revision History:
--*/
#include "sable.h"
#include "halalpha.h"
.set noreorder
LEAF_ENTRY(WRITE_T2_REGISTER)
ALTERNATE_ENTRY(WRITE_CPU_REGISTER)
ALTERNATE_ENTRY(WRITE_MEM_REGISTER)
/*++
Routine Description:
Writes a T2, Memory Module or a CPU CSR.
Arguments:
a0 QVA of register to be written.
a1 Longword to be written.
Return Value:
None.
--*/
and a0, QVA_SELECTORS, t1 // get qva selector bits
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
bne t1, 2f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0
ldiq t4, -0x4000
sll t4, 28, t4
or t0, t4, t0 // superpage mode
stq a1, (t0) // write the quadword
mb // order the write
mb
ret zero, (ra)
2:
BREAK_DEBUG_STOP // Bad Qva
ret zero, (ra)
.end WRITE_T2_REGISTER
LEAF_ENTRY(READ_T2_REGISTER)
ALTERNATE_ENTRY(READ_CPU_REGISTER)
ALTERNATE_ENTRY(READ_MEM_REGISTER)
/*++
Routine Description:
Read a T2, Memory Module or CPU CSR.
Arguments:
a0 QVA of register to be read.
Return Value:
The quadword read from the register.
--*/
and a0, QVA_SELECTORS, t1 // get qva selector bits
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
bne t1, 2f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
sll a0, IO_BIT_SHIFT, t0
ldiq t4, -0x4000
sll t4, 28, t4
or t0, t4, t0 // superpage mode
ldq v0, (t0) // read the register
mb // synchronize
mb //
ret zero, (ra)
2:
BREAK_DEBUG_STOP // Bad Qva
ret zero, (ra)
.end READ_T2_REGISTER
//
// Values and structures used to access configuration space.
//
//
// Define the QVA for the Configuration Cycle Type register within the
// IOC.
//
// PASS 1 SABLE SUPPORT
#define T2_HAE0_2_QVA (0xbc700008)
#define T2_HAE02_CYCLETYPE_SHIFT 30
#define T2_HAE02_CYCLETYPE_MASK 0xc0000000
// PASS 2 SABLE SUPPORT
#define T2_HAE0_3_QVA (0xbc700012)
#define T2_HAE03_CYCLETYPE_SHIFT 30
#define T2_HAE03_CYCLETYPE_MASK 0xc0000000
#define T2_CONFIG_ADDR_QVA (0xbc800000)
// T4 SUPPORT
#define T4_HAE0_3_QVA (0xbc780012)
#define T4_CONFIG_ADDR_QVA (0xbcc00000)
#define T2_OR_T4 (0x00400000)
//
// Define the configuration routines stack frame.
//
.struct 0
CfgRa: .space 8 // return address
CfgA0: .space 8 // saved ConfigurationAddress
CfgA1: .space 8 // saved ConfigurationData
CfgA2: .space 8 // padding for 16 byte alignment
CfgFrameLength:
//++
//
// ULONG
// READ_CONFIG_UCHAR(
// ULONG ConfigurationAddress,
// ULONG ConfigurationCycleType
// )
//
// Routine Description:
//
// Read an unsigned byte from PCI configuration space.
//
// Arguments:
//
// ConfigurationAddress(a0) - Supplies the QVA of configuration to be read.
//
// ConfigurationCycleType(a1) - Supplies the type of the configuration cycle.
//
// Return Value:
//
// (v0) Returns the value of configuration space at the specified location.
//
// N.B. - This routine follows a protocol for reading from PCI configuration
// space that allows the HAL or firmware to fixup and continue
// execution if no device exists at the configuration target address.
// The protocol requires 2 rules:
// (1) The configuration space load must use a destination register
// of v0
// (2) The instruction immediately following the configuration space
// load must use v0 as an operand (it must consume the value
// returned by the load)
//
//--
NESTED_ENTRY( READ_CONFIG_UCHAR, CfgFrameLength, zero )
lda sp, -CfgFrameLength(sp) // allocate stack frame
stq ra, CfgRa(sp) // save return address
PROLOGUE_END // end prologue
//
// Depending on whether it's a pass 1 or pass 2 sable the configuration
// cycle type is in different registers
//
ldl t0, T2VersionNumber // load version number
beq t0, 1f // if 0 then pass 1 sable
//
// PASS 2 sable or Xio access:
// Cycle type are the only bits in HAE0_3 register
//
stq a0, CfgA0(sp) // save config space address
//
// See if this was a request on the T4 or the T2 by looking at the
// Config address passed in.
//
ldil t1, T2_HAE0_3_QVA // address of T2's HAE0_3
ldil t2, T4_HAE0_3_QVA // address of T4's HAE0_3
ldil t0, T2_OR_T4 // Load mask to tell if T2 or T4
and a0, t0, t3 // mask out other bits
cmoveq t3, t1, a0 // if t3 == 0 then t1 -> a0
cmovne t3, t2, a0 // if t3 != 0 then t2 -> a0
sll a1, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type in position
bsr ra, WRITE_T2_REGISTER // write updated HAE
br zero, 2f // go do actual read
//
// PASS 1 sable
// Merge the configuration cycle type into the HAE0_2 register within
// the T2.
//
1:
stq a0, CfgA0(sp) // save config space address
stq a1, CfgA1(sp) // save config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, READ_T2_REGISTER // read current value
ldq a1, CfgA1(sp) // restore config cycle type
ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
bic v0, t0, t0 // clear config cycle type field
sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1// put cycle type in position
bis a1, t0, a1 // merge config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, WRITE_T2_REGISTER // write updated HAE
//
// Perform the read from configuration space after restoring the
// configuration space address.
//
2:
ldq a0, CfgA0(sp) // restore config space address
and a0, QVA_SELECTORS, t1 // get qva selector bits
and a0, 0x3, t3 // capture byte lane
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set
bne t1, 3f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, QVA_ENABLE, a0 // clear QVA fields
sll a0, IO_BIT_SHIFT, t0 //
ldiq t4, -0x4000 //
sll t4, 28, t4 //
bis t0, t4, t0 // superpage mode
bis t0, IO_BYTE_LEN, t0 // or in the byte enables
ldl v0, (t0) // read the longword
extbl v0, t3, v0 // return byte from requested lane
// also, consume loaded value
// to cause a pipeline stall
mb // Sable requires MBs or the
mb // machine check may happen
// much later
3: //
ldq ra, CfgRa(sp) // restore return address
lda sp, CfgFrameLength(sp) // deallocate stack frame
ret zero, (ra) // return
.end READ_CONFIG_UCHAR
//++
//
// VOID
// WRITE_CONFIG_UCHAR(
// ULONG ConfigurationAddress,
// UCHAR ConfigurationData,
// ULONG ConfigurationCycleType
// )
//
// Routine Description:
//
// Read an unsigned byte from PCI configuration space.
//
// Arguments:
//
// ConfigurationAddress(a0) - Supplies the QVA to write.
//
// ConfigurationData(a1) - Supplies the data to be written.
//
// ConfigurationCycleType(a2) - Supplies the type of the configuration cycle.
//
// Return Value:
//
// None.
//
// N.B. - The configuration address must exist within the address space
// allocated to an existing PCI device. Otherwise, the access
// below will initiate an unrecoverable machine check.
//
//--
NESTED_ENTRY( WRITE_CONFIG_UCHAR, CfgFrameLength, zero )
lda sp, -CfgFrameLength(sp) // allocate stack frame
stq ra, CfgRa(sp) // save return address
PROLOGUE_END // end prologue
//
// Depending on whether it's a pass 1 or pass 2 sable the configuration
// cycle type is in different registers
//
ldl t0, T2VersionNumber // load version number
beq t0, 1f // if 0 then pass 1 sable
//
// PASS 2 sable
// Merge the configuration cycle type into the HAE0_3 register within
// the T2.
//
stq a0, CfgA0(sp) // save config space address
stq a1, CfgA1(sp) // save config data
//
// See if this was a request on the T4 or the T2 by looking at the
// Config address passed in.
//
ldil t1, T2_HAE0_3_QVA // address of T2's HAE0_3
ldil t2, T4_HAE0_3_QVA // address of T4's HAE0_3
ldil t0, T2_OR_T4 // Load mask to tell if T2 or T4
and a0, t0, t3 // mask out other bits
cmoveq t3, t1, a0 // if t3 == 0 then t1 -> a0
cmovne t3, t2, a0 // if t3 != 0 then t2 -> a0
sll a2, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type into position
bsr ra, WRITE_T2_REGISTER // write updated HAE
br zero, 2f
//
// Merge the configuration cycle type into the HAE0_3 register within
// the T2.
//
1:
stq a0, CfgA0(sp) // save config space address
stq a1, CfgA1(sp) // save config data
stq a2, CfgA2(sp) // save config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, READ_T2_REGISTER // read current value
ldq a1, CfgA2(sp) // restore config cycle type
ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
bic v0, t0, t0 // clear config cycle type field
sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1 // put cycle type into position
bis a1, t0, a1 // merge config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, WRITE_T2_REGISTER // write updated HAE
//
// Perform the read from configuration space after restoring the
// configuration space address and data.
//
2:
ldq a0, CfgA0(sp) // restore config space address
ldq a1, CfgA1(sp) // restore config data
and a0, QVA_SELECTORS, t1 // get qva selector bits
and a0, 0x3, t3 // capture byte lane
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE
bne t1, 3f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, QVA_ENABLE, a0 // clear QVA fields
sll a0, IO_BIT_SHIFT, t0 //
ldiq t4, -0x4000 //
sll t4, 28, t4 //
bis t0, t4, t0 // superpage mode
bis t0, IO_BYTE_LEN, t0 // or in the byte length indicator
insbl a1, t3, t4 // put byte in the appropriate lane
stl t4, (t0) // write the configuration byte
mb // synchronize
mb // synchronize
3:
ldq ra, CfgRa(sp) // restore return address
lda sp, CfgFrameLength(sp) // deallocate stack frame
ret zero, (ra) // return
.end WRITE_CONFIG_UCHAR
//++
//
// ULONG
// READ_CONFIG_USHORT(
// ULONG ConfigurationAddress,
// ULONG ConfigurationCycleType
// )
//
// Routine Description:
//
// Read a longword from PCI configuration space.
//
// Arguments:
//
// ConfigurationAddress(a0) - Supplies the QVA of quadword to be read.
//
// ConfigurationCycleType(a1) - Supplies the type of the configuration cycle.
//
// Return Value:
//
// (v0) Returns the value of configuration space at the specified location.
//
// N.B. - This routine follows a protocol for reading from PCI configuration
// space that allows the HAL or firmware to fixup and continue
// execution if no device exists at the configuration target address.
// The protocol requires 2 rules:
// (1) The configuration space load must use a destination register
// of v0
// (2) The instruction immediately following the configuration space
// load must use v0 as an operand (it must consume the value
// returned by the load)
//--
NESTED_ENTRY( READ_CONFIG_USHORT, CfgFrameLength, zero )
lda sp, -CfgFrameLength(sp) // allocate stack frame
stq ra, CfgRa(sp) // save return address
PROLOGUE_END // end prologue
//
// Depending on whether it's a pass 1 or pass 2 sable the configuration
// cycle type is in different registers
//
ldl t0, T2VersionNumber // load version number
beq t0, 1f // if 0 then pass 1 sable
//
// Pass 2 Sable
// Merge the configuration cycle type into the HAE0_2 register within
// the T2.
//
stq a0, CfgA0(sp) // save config space address
//
// See if this was a request on the T4 or the T2 by looking at the
// Config address passed in.
//
ldil t1, T2_HAE0_3_QVA // address of T2's HAE0_3
ldil t2, T4_HAE0_3_QVA // address of T4's HAE0_3
ldil t0, T2_OR_T4 // Load mask to tell if T2 or T4
and a0, t0, t3 // mask out other bits
cmoveq t3, t1, a0 // if t3 == 0 then t1 -> a0
cmovne t3, t2, a0 // if t3 != 0 then t2 -> a0
sll a1, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type into position
bsr ra, WRITE_T2_REGISTER // write updated HAE
br zero, 2f // go do actual io
//
// Pass 1 Sable
// Merge the configuration cycle type into the HAE0_2 register within
// the T2.
//
1:
stq a0, CfgA0(sp) // save config space address
stq a1, CfgA1(sp) // save config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, READ_T2_REGISTER // read current value
ldq a1, CfgA1(sp) // restore configuration cycle type
ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
bic v0, t0, t0 // clear config cycle type field
sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1 // put cycle type into position
bis a1, t0, a1 // merge config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, WRITE_T2_REGISTER // write updated HAE
//
// Perform the read from configuration space after restoring the
// configuration space address.
//
2:
ldq a0, CfgA0(sp) // restore config space address
and a0, QVA_SELECTORS, t1 // get qva selector bits
and a0, 0x3, t3 // capture word offset
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set
bne t1, 3f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, QVA_ENABLE, a0 // clear QVA fields
sll a0, IO_BIT_SHIFT, t0 //
ldiq t4, -0x4000 //
sll t4, 28, t4 //
bis t0, t4, t0 // superpage mode
bis t0, IO_WORD_LEN, t0 // or in the byte enables
ldl v0, (t0) // read the longword
extwl v0, t3, v0 // return word from requested lanes
// also, consume loaded value
// to cause a pipeline stall
mb // Sable requires MBs or the
mb // machine check may happen
// much later
3:
ldq ra, CfgRa(sp) // restore return address
lda sp, CfgFrameLength(sp) // deallocate stack frame
ret zero, (ra) // return
.end READ_CONFIG_USHORT
//++
//
// VOID
// WRITE_CONFIG_USHORT(
// ULONG ConfigurationAddress,
// USHORT ConfigurationData,
// ULONG ConfigurationCycleType
// )
//
// Routine Description:
//
// Read a longword from PCI configuration space.
//
// Arguments:
//
// ConfigurationAddress(a0) - Supplies the QVA to write.
//
// ConfigurationData(a1) - Supplies the data to be written.
//
// ConfigurationCycleType(a2) - Supplies the type of the configuration cycle.
//
// Return Value:
//
// (v0) Returns the value of configuration space at the specified location.
//
// N.B. - The configuration address must exist within the address space
// allocated to an existing PCI device. Otherwise, the access
// below will initiate an unrecoverable machine check.
//
//--
NESTED_ENTRY( WRITE_CONFIG_USHORT, CfgFrameLength, zero )
lda sp, -CfgFrameLength(sp) // allocate stack frame
stq ra, CfgRa(sp) // save return address
PROLOGUE_END // end prologue
//
// Depending on whether it's a pass 1 or pass 2 sable the configuration
// cycle type is in different registers
//
ldl t0, T2VersionNumber // load version number
beq t0, 1f // if 0 then pass 1 sable
//
// Pass 2 sable
// Merge the configuration cycle type into the HAE0_2 register within
// the T2.
//
stq a0, CfgA0(sp) // save config space address
stq a1, CfgA1(sp) // save config data
//
// See if this was a request on the T4 or the T2 by looking at the
// Config address passed in.
//
ldil t1, T2_HAE0_3_QVA // address of T2's HAE0_3
ldil t2, T4_HAE0_3_QVA // address of T4's HAE0_3
ldil t0, T2_OR_T4 // Load mask to tell if T2 or T4
and a0, t0, t3 // mask out other bits
cmoveq t3, t1, a0 // if t3 == 0 then t1 -> a0
cmovne t3, t2, a0 // if t3 != 0 then t2 -> a0
sll a2, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type into position
bsr ra, WRITE_T2_REGISTER // write updated HAE
br zero, 2f // go do actual transfer
//
// Pass 1 sable
// Merge the configuration cycle type into the HAE0_2 register within
// the T2.
//
1:
stq a0, CfgA0(sp) // save config space address
stq a1, CfgA1(sp) // save config data
stq a2, CfgA2(sp) // save config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, READ_T2_REGISTER // read current value
ldq a1, CfgA2(sp) // restore configuration cycle type
ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
bic v0, t0, t0 // clear config cycle type field
sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1 // put cycle type into position
bis a1, t0, a1 // merge config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, WRITE_T2_REGISTER // write updated HAE
//
// Perform the read from configuration space after restoring the
// configuration space address and data.
//
2:
ldq a0, CfgA0(sp) // restore config space address
ldq a1, CfgA1(sp) // restore config data
and a0, QVA_SELECTORS, t1 // get qva selector bits
and a0, 0x3, t3 // capture word offset
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set
bne t1, 3f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, QVA_ENABLE, a0 // clear QVA fields
sll a0, IO_BIT_SHIFT, t0 //
ldiq t4, -0x4000 //
sll t4, 28, t4 //
bis t0, t4, t0 // superpage mode
bis t0, IO_WORD_LEN, t0 // or in the byte enables
inswl a1, t3, t4 // put data to appropriate lane
stl t4, (t0) // read the longword
mb // synchronize
mb // synchronize
3:
ldq ra, CfgRa(sp) // restore return address
lda sp, CfgFrameLength(sp) // deallocate stack frame
ret zero, (ra) // return
.end WRITE_CONFIG_USHORT
//++
//
// ULONG
// READ_CONFIG_ULONG(
// ULONG ConfigurationAddress,
// ULONG ConfigurationCycleType
// )
//
// Routine Description:
//
// Read a longword from PCI configuration space.
//
// Arguments:
//
// ConfigurationAddress(a0) - Supplies the QVA of quadword to be read.
//
// ConfigurationCycleType(a1) - Supplies the type of the configuration cycle.
//
// Return Value:
//
// (v0) Returns the value of configuration space at the specified location.
//
// N.B. - This routine follows a protocol for reading from PCI configuration
// space that allows the HAL or firmware to fixup and continue
// execution if no device exists at the configuration target address.
// The protocol requires 2 rules:
// (1) The configuration space load must use a destination register
// of v0
// (2) The instruction immediately following the configuration space
// load must use v0 as an operand (it must consume the value
// returned by the load)
//--
NESTED_ENTRY( READ_CONFIG_ULONG, CfgFrameLength, zero )
lda sp, -CfgFrameLength(sp) // allocate stack frame
stq ra, CfgRa(sp) // save return address
PROLOGUE_END // end prologue
//
// Depending on whether it's a pass 1 or pass 2 sable the configuration
// cycle type is in different registers
//
ldl t0, T2VersionNumber // load version number
beq t0, 1f // if 0 then pass 1 sable
//
// PASS 2 sable:
// Cycle type are the only bits in HAE0_3 register
//
stq a0, CfgA0(sp) // save config space address
//
// See if this was a request on the T4 or the T2 by looking at the
// Config address passed in.
//
ldil t1, T2_HAE0_3_QVA // address of T2's HAE0_3
ldil t2, T4_HAE0_3_QVA // address of T4's HAE0_3
ldil t0, T2_OR_T4 // Load mask to tell if T2 or T4
and a0, t0, t3 // mask out other bits
cmoveq t3, t1, a0 // if t3 == 0 then t1 -> a0
cmovne t3, t2, a0 // if t3 != 0 then t2 -> a0
sll a1, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type in position
bsr ra, WRITE_T2_REGISTER // write updated HAE
br zero, 2f // go do actual read
//
// PASS 1 sable
// Merge the configuration cycle type into the HAE0_2 register within
// the T2.
//
1:
stq a0, CfgA0(sp) // save config space address
stq a1, CfgA1(sp) // save config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, READ_T2_REGISTER // read current value
ldq a1, CfgA1(sp) // restore config cycle type
ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
bic v0, t0, t0 // clear config cycle type field
sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1// put cycle type in position
bis a1, t0, a1 // merge config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, WRITE_T2_REGISTER // write updated HAE
//
// Perform the read from configuration space after restoring the
// configuration space address.
//
2:
ldq a0, CfgA0(sp) // restore config space address
and a0, QVA_SELECTORS, t1 // get qva selector bits
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set
bne t1, 3f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, QVA_ENABLE,a0 // clear QVA fields
sll a0, IO_BIT_SHIFT, t0 //
ldiq t4, -0x4000 //
sll t4, 28, t4 //
or t0, t4, t0 // superpage mode
or t0, IO_LONG_LEN, t0 // or in the byte enables
ldl v0, (t0) // read the longword
bis v0, zero, t1 // consume loaded value to cause
// a pipeline stall
mb // Sable requires MBs or the
mb // machine check may happen
// much later
3:
ldq ra, CfgRa(sp) // restore return address
lda sp, CfgFrameLength(sp) // deallocate stack frame
ret zero, (ra) // return
.end READ_CONFIG_ULONG
//++
//
// VOID
// WRITE_CONFIG_ULONG(
// ULONG ConfigurationAddress,
// ULONG ConfigurationData,
// ULONG ConfigurationCycleType
// )
//
// Routine Description:
//
// Read a longword from PCI configuration space.
//
// Arguments:
//
// ConfigurationAddress(a0) - Supplies the QVA to write.
//
// ConfigurationData(a1) - Supplies the data to be written.
//
// ConfigurationCycleType(a2) - Supplies the type of the configuration cycle.
//
// Return Value:
//
// (v0) Returns the value of configuration space at the specified location.
//
// N.B. - The configuration address must exist within the address space
// allocated to an existing PCI device. Otherwise, the access
// below will initiate an unrecoverable machine check.
//
//--
NESTED_ENTRY( WRITE_CONFIG_ULONG, CfgFrameLength, zero )
lda sp, -CfgFrameLength(sp) // allocate stack frame
stq ra, CfgRa(sp) // save return address
PROLOGUE_END // end prologue
//
// Depending on whether it's a pass 1 or pass 2 sable the configuration
// cycle type is in different registers
//
ldl t0, T2VersionNumber // load version number
beq t0, 1f // if 0 then pass 1 sable
//
// Pass 2 sable
// Merge the configuration cycle type into the HAE0_2 register within
// the T2.
//
stq a0, CfgA0(sp) // save config space address
stq a1, CfgA1(sp) // save config data
//
// See if this was a request on the T4 or the T2 by looking at the
// Config address passed in.
//
ldil t1, T2_HAE0_3_QVA // address of T2's HAE0_3
ldil t2, T4_HAE0_3_QVA // address of T4's HAE0_3
ldil t0, T2_OR_T4 // Load mask to tell if T2 or T4
and a0, t0, t3 // mask out other bits
cmoveq t3, t1, a0 // if t3 == 0 then t1 -> a0
cmovne t3, t2, a0 // if t3 != 0 then t2 -> a0
sll a2, T2_HAE03_CYCLETYPE_SHIFT, a1 // put cycle type into position
bsr ra, WRITE_T2_REGISTER // write updated HAE
br zero, 2f // go do actual transfer
//
// Pass 1 sable
// Merge the configuration cycle type into the HAE0_2 register within
// the T2.
//
1:
stq a0, CfgA0(sp) // save config space address
stq a1, CfgA1(sp) // save config data
stq a2, CfgA2(sp) // save config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, READ_T2_REGISTER // read current value
ldq a1, CfgA2(sp) // restore configuration cycle type
ldil t0, T2_HAE02_CYCLETYPE_MASK // get cycle type field mask
bic v0, t0, t0 // clear config cycle type field
sll a1, T2_HAE02_CYCLETYPE_SHIFT, a1 // put cycle type into position
bis a1, t0, a1 // merge config cycle type
ldil a0, T2_HAE0_2_QVA // address of HAE0_2
bsr ra, WRITE_T2_REGISTER // write updated HAE
//
// Perform the read from configuration space after restoring the
// configuration space address and data.
//
2:
ldq a0, CfgA0(sp) // restore config space address
ldq a1, CfgA1(sp) // restore config data
and a0, QVA_SELECTORS, t1 // get qva selector bits
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set
bne t1, 3f // if ne, iff failed
zap a0, 0xf0, a0 // clear <63:32>
bic a0, QVA_ENABLE, a0 // clear QVA fields
sll a0, IO_BIT_SHIFT, t0 //
ldiq t4, -0x4000 //
sll t4, 28, t4 //
bis t0, t4, t0 // superpage mode
bis t0, IO_LONG_LEN, t0 // or in the byte enables
stl a1, (t0) // write the longword
mb // synchronize
mb // synchronize
3: //
ldq ra, CfgRa(sp) // restore return address
lda sp, CfgFrameLength(sp) // deallocate stack frame
ret zero, (ra) // return
.end WRITE_CONFIG_ULONG
|
