blob: f902b150688f7e51aaaf4c87eebfa3b83860b098 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
|
/*++
Copyright (c) 1993 Digital Equipment Corporation
Module Name:
ebmapio.c
Abstract:
This module contains the functions to map HAL-accessed I/O addresses
on the Sable system.
Author:
Joe Notarangelo 25-Oct-1993
Environment:
Kernel mode
Revision History:
--*/
#include "halp.h"
#include "isaaddr.h"
//
// Define global data used to locate the EISA control space.
//
PVOID HalpEisaControlBase;
PVOID HalpEisaIntAckBase;
PVOID HalpCMOSRamBase;
//
// Define the array that maps logical processor numbers to the corresponding
// QVA for that processor's CPU CSRs.
//
PSABLE_CPU_CSRS HalpSableCpuCsrs[HAL_MAXIMUM_PROCESSOR+1];
BOOLEAN
HalpMapIoSpace (
VOID
)
/*++
Routine Description:
This routine maps the HAL I/O space for a Sable
system using the Quasi VA.
Arguments:
None.
Return Value:
If the initialization is successfully completed, then a value of TRUE
is returned. Otherwise, a value of FALSE is returned.
--*/
{
PVOID PciIoSpaceBase;
#if !defined(AXP_FIRMWARE)
PKPRCB Prcb;
extern HalpLogicalToPhysicalProcessor[HAL_MAXIMUM_PROCESSOR+1];
Prcb = PCR->Prcb;
//
// Assign CPU specific CSR address
//
switch( HalpLogicalToPhysicalProcessor[Prcb->Number] ) {
case SABLE_CPU0:
HAL_PCR->IpirSva = SABLE_CPU0_IPIR_PHYSICAL | SUPERPAGE_ENABLE;
HAL_PCR->CpuCsrsQva = SABLE_CPU0_CSRS_QVA;
HalpSableCpuCsrs[Prcb->Number] = SABLE_CPU0_CSRS_QVA;
break;
case SABLE_CPU1:
HAL_PCR->IpirSva = SABLE_CPU1_IPIR_PHYSICAL | SUPERPAGE_ENABLE;
HAL_PCR->CpuCsrsQva = SABLE_CPU1_CSRS_QVA;
HalpSableCpuCsrs[Prcb->Number] = SABLE_CPU1_CSRS_QVA;
break;
case SABLE_CPU2:
HAL_PCR->IpirSva = SABLE_CPU2_IPIR_PHYSICAL | SUPERPAGE_ENABLE;
HAL_PCR->CpuCsrsQva = SABLE_CPU2_CSRS_QVA;
HalpSableCpuCsrs[Prcb->Number] = SABLE_CPU2_CSRS_QVA;
break;
case SABLE_CPU3:
HAL_PCR->IpirSva = SABLE_CPU3_IPIR_PHYSICAL | SUPERPAGE_ENABLE;
HAL_PCR->CpuCsrsQva = SABLE_CPU3_CSRS_QVA;
HalpSableCpuCsrs[Prcb->Number] = SABLE_CPU3_CSRS_QVA;
break;
default:
#ifdef HALDBG
DbgPrint("HalpMapIoSpace: Invalid Cpu number %d\n", Prcb->Number);
DbgBreakPoint();
#else
;
#endif // HALDBG
}
#endif // AXP_FIRMWARE
//
// Map EISA control space.
//
PciIoSpaceBase = HAL_MAKE_QVA( SABLE_PCI0_SPARSE_IO_PHYSICAL );
HalpEisaControlBase = PciIoSpaceBase;
HalpCMOSRamBase = (PVOID)
( (ULONG)HAL_MAKE_QVA( SABLE_PCI0_SPARSE_IO_PHYSICAL ) +
CMOS_ISA_PORT_ADDRESS );
//
// Map the real-time clock registers.
//
HalpRtcAddressPort = (PVOID)((ULONG)PciIoSpaceBase + RTC_ISA_ADDRESS_PORT);
HalpRtcDataPort = (PVOID)((ULONG)PciIoSpaceBase + RTC_ISA_DATA_PORT);
return TRUE;
}
ULONG
HalpMapDebugPort(
IN ULONG ComPort,
OUT PULONG ReadQva,
OUT PULONG WriteQva
)
/*++
Routine Description:
This routine maps the debug com port so that the kernel debugger
may function - if called it is called very earlier in the boot sequence.
Arguments:
ComPort - Supplies the number of the com port to use as the debug port.
ReadQva - Receives the QVA used to access the read registers of the debug
port.
WriteQva - Receives the QVA used to access the write registers of the
debug port.
Return Value:
Returns the base bus address of the device used as the debug port.
--*/
{
ULONG ComPortAddress;
ULONG PortQva;
//
// Compute the port address, based on the desired com port.
//
switch( ComPort ){
case 1:
ComPortAddress = COM1_ISA_PORT_ADDRESS;
break;
case 2:
default:
ComPortAddress = COM2_ISA_PORT_ADDRESS;
}
//
// Return the QVAs for read and write access.
//
PortQva = (ULONG)HAL_MAKE_QVA(SABLE_PCI0_SPARSE_IO_PHYSICAL) +
ComPortAddress;
*ReadQva = PortQva;
*WriteQva = PortQva;
return ComPortAddress;
}
|
