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authorMathew Maidment <mathew1800@gmail.com>2016-04-06 19:01:32 +0200
committerMathew Maidment <mathew1800@gmail.com>2016-04-06 19:01:32 +0200
commit0408f1191a4787ab6c47743d963b0692f7329f6e (patch)
tree67e837d30e2a84e725f6492155148163028e0026
parentMerge pull request #1435 from mailwl/frd_u (diff)
parentFix thumb ADR instruction alignment (diff)
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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 9ed61947e..a6faf42b9 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3955,9 +3955,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
add_inst* const inst_cream = (add_inst*)inst_base->component;
- u32 rn_val = RN;
- if (inst_cream->Rn == 15)
- rn_val += 2 * cpu->GetInstructionSize();
+ u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn);
bool carry;
bool overflow;
@@ -6167,9 +6165,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
sub_inst* const inst_cream = (sub_inst*)inst_base->component;
- u32 rn_val = RN;
- if (inst_cream->Rn == 15)
- rn_val += 2 * cpu->GetInstructionSize();
+ u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn);
bool carry;
bool overflow;