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authorbunnei <bunneidev@gmail.com>2022-03-29 00:45:52 +0200
committerGitHub <noreply@github.com>2022-03-29 00:45:52 +0200
commit642913b0d1e27e4a81ee454903a65b5ce5ddee72 (patch)
treea77c2c60258ff98c475556fffe784074f4c93287
parentMerge pull request #8095 from bylaws/master (diff)
parentarm_dynarmic_64: Invalidate on all cores (diff)
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m---------externals/dynarmic0
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp6
2 files changed, 4 insertions, 2 deletions
diff --git a/externals/dynarmic b/externals/dynarmic
-Subproject e1a266b9299be81cc0318c7e25b00388c342704
+Subproject af2d50288fc537201014c4230bb55ab9018a743
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index d96226c41..24107f9f6 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -93,17 +93,19 @@ public:
static constexpr u64 ICACHE_LINE_SIZE = 64;
const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
- parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
+ parent.system.InvalidateCpuInstructionCacheRange(cache_line_start, ICACHE_LINE_SIZE);
break;
}
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
- parent.ClearInstructionCache();
+ parent.system.InvalidateCpuInstructionCaches();
break;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default:
LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
break;
}
+
+ parent.jit->HaltExecution();
}
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {