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| author | Lioncash <mathew1800@gmail.com> | 2015-02-26 15:26:51 +0100 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2015-02-26 15:28:31 +0100 |
| commit | 8812d2fbdb64ebeed7868bb73f470e30e50d27e0 (patch) | |
| tree | 68f847d3df6dbccdfcbdd91d8c4d1b2f54b42819 | |
| parent | Merge pull request #612 from yuriks/fix-A4 (diff) | |
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| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 3b508f617..d8a708b9e 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -4709,9 +4709,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { DEBUG_MSG; } else { if (inst_cream->cp_num == 15) { - if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) { - CP15_REG(CP15_MAIN_ID) = RD; - } else if(CRn == 1 && CRm == 0 && OPCODE_2 == 0) { + if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) { CP15_REG(CP15_CONTROL) = RD; } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) { CP15_REG(CP15_AUXILIARY_CONTROL) = RD; |