2 files changed, 39 insertions, 1 deletions

diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 96b745db8..dc98bdc3d 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -242,6 +242,8 @@ enum class TextureType : u64 {
     TextureCube = 3,
 };
 
+enum class IpaMode : u64 { Pass = 0, None = 1, Constant = 2, Sc = 3 };
+
 union Instruction {
     Instruction& operator=(const Instruction& instr) {
         value = instr.value;
@@ -325,6 +327,10 @@ union Instruction {
     } alu;
 
     union {
+        BitField<54, 3, IpaMode> mode;
+    } ipa;
+
+    union {
         BitField<48, 1, u64> negate_b;
     } fmul;
 
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 7e5ebfe24..7b6eb25a4 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -2100,7 +2100,39 @@ private:
             }
             case OpCode::Id::IPA: {
                 const auto& attribute = instr.attribute.fmt28;
-                regs.SetRegisterToInputAttibute(instr.gpr0, attribute.element, attribute.index);
+                const auto& reg = instr.gpr0;
+                switch (instr.ipa.mode) {
+                case Tegra::Shader::IpaMode::Pass:
+                    if (stage == Maxwell3D::Regs::ShaderStage::Fragment &&
+                        attribute.index == Attribute::Index::Position) {
+                        switch (attribute.element) {
+                        case 0:
+                            shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.x;");
+                            break;
+                        case 1:
+                            shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.y;");
+                            break;
+                        case 2:
+                            shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.z;");
+                            break;
+                        case 3:
+                            shader.AddLine(regs.GetRegisterAsFloat(reg) + " = 1.0;");
+                            break;
+                        }
+                    } else {
+                        regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
+                    }
+                    break;
+                case Tegra::Shader::IpaMode::None:
+                    regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
+                    break;
+                default:
+                    LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}",
+                                 static_cast<u32>(instr.ipa.mode.Value()));
+                    UNREACHABLE();
+                    regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
+                }
+
                 break;
             }
             case OpCode::Id::SSY: {