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| author | Normmatt <normmatt234@gmail.com> | 2014-12-17 08:54:24 +0100 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2014-12-17 09:17:44 +0100 |
| commit | b5dbd6f2a27cc85a7262920942dd1c78fff21bb5 (patch) | |
| tree | 25c9e49781d45aace8ce19c1559c834b21b61fc3 /src/core/arm/interpreter/armemu.cpp | |
| parent | armemu: Fix SXTAH (diff) | |
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Diffstat (limited to 'src/core/arm/interpreter/armemu.cpp')
| -rw-r--r-- | src/core/arm/interpreter/armemu.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index 843323293..cffbae7e7 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp @@ -6044,7 +6044,7 @@ L_stm_s_takeabort: break; } - Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF); + Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF; if (Rm & 0x80) Rm |= 0xffffff00; @@ -6053,7 +6053,7 @@ L_stm_s_takeabort: state->Reg[BITS(12, 15)] = Rm; else /* SXTAB */ - state->Reg[BITS(12, 15)] += Rm; + state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm; return 1; } |