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authorLioncash <mathew1800@gmail.com>2015-04-06 21:58:45 +0200
committerLioncash <mathew1800@gmail.com>2015-04-06 22:09:28 +0200
commitf9cc6d648469dbf454997ff7f61ae457ff11a4bb (patch)
tree7a9d99be1e6c71c0caa929353d7ae90ab70085ad /src/core/arm/skyeye_common/armdefs.h
parentMerge pull request #685 from lioncash/cpregs (diff)
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Diffstat (limited to 'src/core/arm/skyeye_common/armdefs.h')
-rw-r--r--src/core/arm/skyeye_common/armdefs.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
index 12fa533f7..743e935f0 100644
--- a/src/core/arm/skyeye_common/armdefs.h
+++ b/src/core/arm/skyeye_common/armdefs.h
@@ -92,13 +92,15 @@ struct ARMul_State
ARMword exclusive_state;
ARMword exclusive_result;
ARMword CP15[CP15_REGISTER_COUNT];
- ARMword VFP[3]; // FPSID, FPSCR, and FPEXC
+
+ // FPSID, FPSCR, and FPEXC
+ ARMword VFP[VFP_SYSTEM_REGISTER_COUNT];
// VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
// VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
// and only 32 singleword registers are accessible (S0-S31).
ARMword ExtReg[VFP_REG_NUM];
/* ---- End of the ordered registers ---- */
-
+
ARMword RegBank[7][16]; // all the registers
ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed