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| author | Lioncash <mathew1800@gmail.com> | 2015-07-29 18:21:04 +0200 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2015-07-29 18:21:16 +0200 |
| commit | 46663d657fd7cde82e3600d08b5e3bfd17b366d5 (patch) | |
| tree | ee7978d22c1b60597e8148a55f872aea367678f8 /src/core/arm | |
| parent | Merge pull request #1009 from lioncash/table (diff) | |
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Diffstat (limited to 'src/core/arm')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 0c20c2bc3..bb0cbb4dc 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -3886,7 +3886,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { #endif arm_inst* inst_base; unsigned int addr; - unsigned int phys_addr; unsigned int num_instrs = 0; int ptr; @@ -3905,8 +3904,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { else cpu->Reg[15] &= 0xfffffffc; - phys_addr = cpu->Reg[15]; - // Find the cached instruction cream, otherwise translate it... auto itr = cpu->instruction_cache.find(cpu->Reg[15]); if (itr != cpu->instruction_cache.end()) { |