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| author | Lioncash <mathew1800@gmail.com> | 2015-01-07 22:38:52 +0100 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2015-01-07 22:41:08 +0100 |
| commit | df5e0f9f288d1ddb5e0563caf5071df6028fa57d (patch) | |
| tree | 3123d9ced84b294884e7c9d3b6e7ebfc09476b46 /src/core/arm | |
| parent | Merge pull request #438 from lioncash/swp (diff) | |
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Diffstat (limited to 'src/core/arm')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 426fc6474..7c710ccde 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -5891,16 +5891,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) { SMULW_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - smlad_inst *inst_cream = (smlad_inst *)inst_base->component; - int64_t rm = RM; - int64_t rn = RN; - if (inst_cream->m) - rm = BITS(rm, 16, 31); - else - rm = BITS(rm, 0, 15); - int64_t rst = rm * rn; - RD = BITS(rst, 16, 47); + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + + s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF); + + s64 result = (s64)rm * (s64)(s32)RN; + RD = BITS(result, 16, 47); } cpu->Reg[15] += GET_INST_SIZE(cpu); INC_PC(sizeof(smlad_inst)); |