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authorSubv <subv2112@gmail.com>2015-03-12 19:11:57 +0100
committerSubv <subv2112@gmail.com>2015-03-16 23:54:06 +0100
commit23b401c3ac6ac1ab9e9cf9ffa9d9a03daa20dfb7 (patch)
tree4cda494f5705d6fb19216b11e4a95e5b99325d38 /src/core/hw/gpu.h
parentGPU: Fixed the bit 25 in the display transfer flags. (diff)
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Diffstat (limited to 'src/core/hw/gpu.h')
-rw-r--r--src/core/hw/gpu.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h
index 3158738f0..d07490db0 100644
--- a/src/core/hw/gpu.h
+++ b/src/core/hw/gpu.h
@@ -188,6 +188,12 @@ struct Regs {
BitField<16, 16, u32> input_height;
};
+ enum ScalingMode : u32 {
+ NoScale = 0, // Doesn't scale the image
+ ScaleX = 1, // Downscales the image in half in the X axis and applies a box filter
+ ScaleXY = 2, // Downscales the image in half in both the X and Y axes and applies a box filter
+ };
+
union {
u32 flags;
@@ -197,8 +203,7 @@ struct Regs {
BitField< 8, 3, PixelFormat> input_format;
BitField<12, 3, PixelFormat> output_format;
- BitField<24, 1, u32> scale_x; // Shrinks the image in half horizontally, blending the extra pixels
- BitField<25, 1, u32> scale_xy; // Shrinks the image horizontally and vertically, blending the extra pixels
+ BitField<24, 2, ScalingMode> scaling; // Determines the scaling mode of the transfer
};
INSERT_PADDING_WORDS(0x1);