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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-05-25 07:46:51 +0200
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:33 +0200
commit75fd0079db9ac2f3bc6bcf182ed080a58538ed06 (patch)
tree3ab3e313bf4d97eea7cde4a31fe18b6bf6698929 /src/shader_recompiler/backend/glasm/reg_alloc.cpp
parentglasm: Throw when there are register leaks (diff)
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Diffstat (limited to 'src/shader_recompiler/backend/glasm/reg_alloc.cpp')
-rw-r--r--src/shader_recompiler/backend/glasm/reg_alloc.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/shader_recompiler/backend/glasm/reg_alloc.cpp b/src/shader_recompiler/backend/glasm/reg_alloc.cpp
index c55a833c6..4c046db6e 100644
--- a/src/shader_recompiler/backend/glasm/reg_alloc.cpp
+++ b/src/shader_recompiler/backend/glasm/reg_alloc.cpp
@@ -78,16 +78,16 @@ Value RegAlloc::MakeImm(const IR::Value& value) {
ret.imm_u32 = value.U32();
break;
case IR::Type::F32:
- ret.type = Type::F32;
- ret.imm_f32 = value.F32();
+ ret.type = Type::U32;
+ ret.imm_u32 = Common::BitCast<u32>(value.F32());
break;
case IR::Type::U64:
ret.type = Type::U64;
ret.imm_u64 = value.U64();
break;
case IR::Type::F64:
- ret.type = Type::F64;
- ret.imm_f64 = value.F64();
+ ret.type = Type::U64;
+ ret.imm_u64 = Common::BitCast<u64>(value.F64());
break;
default:
throw NotImplementedException("Immediate type {}", value.Type());