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| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2021-04-12 00:16:47 +0200 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-23 03:51:27 +0200 |
| commit | 2ed80f6b1e85823d7a13dfbb119545a0a0ec7427 (patch) | |
| tree | 5025ced89b185ae325f0c490699889a2b8dad415 /src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | |
| parent | shader: Implement SR_THREAD_KILL (diff) | |
| download | yuzu-2ed80f6b1e85823d7a13dfbb119545a0a0ec7427.tar yuzu-2ed80f6b1e85823d7a13dfbb119545a0a0ec7427.tar.gz yuzu-2ed80f6b1e85823d7a13dfbb119545a0a0ec7427.tar.bz2 yuzu-2ed80f6b1e85823d7a13dfbb119545a0a0ec7427.tar.lz yuzu-2ed80f6b1e85823d7a13dfbb119545a0a0ec7427.tar.xz yuzu-2ed80f6b1e85823d7a13dfbb119545a0a0ec7427.tar.zst yuzu-2ed80f6b1e85823d7a13dfbb119545a0a0ec7427.zip | |
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp index 8bf43b91d..944f1e429 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp @@ -111,16 +111,25 @@ Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift) { return ctx.OpShiftRightArithmetic(ctx.U64, base, shift); } -Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) { - return ctx.OpBitwiseAnd(ctx.U32[1], a, b); +Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { + const Id result{ctx.OpBitwiseAnd(ctx.U32[1], a, b)}; + SetZeroFlag(ctx, inst, result); + SetSignFlag(ctx, inst, result); + return result; } -Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b) { - return ctx.OpBitwiseOr(ctx.U32[1], a, b); +Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { + const Id result{ctx.OpBitwiseOr(ctx.U32[1], a, b)}; + SetZeroFlag(ctx, inst, result); + SetSignFlag(ctx, inst, result); + return result; } -Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b) { - return ctx.OpBitwiseXor(ctx.U32[1], a, b); +Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { + const Id result{ctx.OpBitwiseXor(ctx.U32[1], a, b)}; + SetZeroFlag(ctx, inst, result); + SetSignFlag(ctx, inst, result); + return result; } Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count) { |