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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-02-15 00:15:42 +0100
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:22 +0200
commitcbfb7d182a4e90e4e263696d1fca35e47d3eabb4 (patch)
treea8d384aa0daefdfafd9b61330e06b1cf7ac40ea6 /src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
parentshader: Misc fixes (diff)
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Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 3ef4f3d78..e811a63ab 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -73,8 +73,8 @@ Id EmitSPIRV::EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id coun
return ctx.OpBitFieldUExtract(ctx.u32[1], base, offset, count);
}
-void EmitSPIRV::EmitSLessThan(EmitContext&) {
- throw NotImplementedException("SPIR-V Instruction");
+Id EmitSPIRV::EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
+ return ctx.OpSLessThan(ctx.u1, lhs, rhs);
}
void EmitSPIRV::EmitULessThan(EmitContext&) {
@@ -93,8 +93,8 @@ void EmitSPIRV::EmitULessThanEqual(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
}
-void EmitSPIRV::EmitSGreaterThan(EmitContext&) {
- throw NotImplementedException("SPIR-V Instruction");
+Id EmitSPIRV::EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
+ return ctx.OpSGreaterThan(ctx.u1, lhs, rhs);
}
void EmitSPIRV::EmitUGreaterThan(EmitContext&) {