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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-04-21 05:27:55 +0200
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:28 +0200
commit420982864634a5e52cea42c43f8623f75483fbcc (patch)
tree5433936232c2819713e69581641ce271c4e0e68f /src/shader_recompiler/frontend/ir/basic_block.h
parentshader: Inline common Opcode and Inst functions (diff)
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Diffstat (limited to 'src/shader_recompiler/frontend/ir/basic_block.h')
-rw-r--r--src/shader_recompiler/frontend/ir/basic_block.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/ir/basic_block.h b/src/shader_recompiler/frontend/ir/basic_block.h
index 6a1d615d9..3a4230755 100644
--- a/src/shader_recompiler/frontend/ir/basic_block.h
+++ b/src/shader_recompiler/frontend/ir/basic_block.h
@@ -101,6 +101,13 @@ public:
return branch_false;
}
+ void SetSsaRegValue(IR::Reg reg, const Value& value) noexcept {
+ ssa_reg_values[RegIndex(reg)] = value;
+ }
+ const Value& SsaRegValue(IR::Reg reg) const noexcept {
+ return ssa_reg_values[RegIndex(reg)];
+ }
+
[[nodiscard]] bool empty() const {
return instructions.empty();
}
@@ -182,6 +189,9 @@ private:
/// Block immediate predecessors
std::vector<Block*> imm_predecessors;
+ /// Intrusively store the value of a register in the block.
+ std::array<Value, NUM_REGS> ssa_reg_values;
+
/// Intrusively stored host definition of this block.
u32 definition{};
};