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| author | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-02-25 06:46:40 +0100 |
|---|---|---|
| committer | ameerj <52414509+ameerj@users.noreply.github.com> | 2021-07-23 03:51:22 +0200 |
| commit | cc55d289494c991e7e0e456e428a110569708c2e (patch) | |
| tree | 36e869098e87528ab7b7f668e232d7e909a2258a /src/shader_recompiler/frontend/ir | |
| parent | shader: Implement SEL (diff) | |
| download | yuzu-cc55d289494c991e7e0e456e428a110569708c2e.tar yuzu-cc55d289494c991e7e0e456e428a110569708c2e.tar.gz yuzu-cc55d289494c991e7e0e456e428a110569708c2e.tar.bz2 yuzu-cc55d289494c991e7e0e456e428a110569708c2e.tar.lz yuzu-cc55d289494c991e7e0e456e428a110569708c2e.tar.xz yuzu-cc55d289494c991e7e0e456e428a110569708c2e.tar.zst yuzu-cc55d289494c991e7e0e456e428a110569708c2e.zip | |
Diffstat (limited to 'src/shader_recompiler/frontend/ir')
| -rw-r--r-- | src/shader_recompiler/frontend/ir/ir_emitter.cpp | 4 | ||||
| -rw-r--r-- | src/shader_recompiler/frontend/ir/ir_emitter.h | 1 | ||||
| -rw-r--r-- | src/shader_recompiler/frontend/ir/opcodes.inc | 1 |
3 files changed, 6 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp index 0209d5540..7c3908398 100644 --- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp +++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp @@ -804,6 +804,10 @@ U32 IREmitter::BitFieldExtract(const U32& base, const U32& offset, const U32& co count); } +U32 IREmitter::BitReverse(const U32& value) { + return Inst<U32>(Opcode::BitReverse32, value); +} + U1 IREmitter::ILessThan(const U32& lhs, const U32& rhs, bool is_signed) { return Inst<U1>(is_signed ? Opcode::SLessThan : Opcode::ULessThan, lhs, rhs); } diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h index 2c923716a..f7998e156 100644 --- a/src/shader_recompiler/frontend/ir/ir_emitter.h +++ b/src/shader_recompiler/frontend/ir/ir_emitter.h @@ -159,6 +159,7 @@ public: const U32& count); [[nodiscard]] U32 BitFieldExtract(const U32& base, const U32& offset, const U32& count, bool is_signed); + [[nodiscard]] U32 BitReverse(const U32& value); [[nodiscard]] U1 ILessThan(const U32& lhs, const U32& rhs, bool is_signed); [[nodiscard]] U1 IEqual(const U32& lhs, const U32& rhs); diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc index 289e76f32..f420f1161 100644 --- a/src/shader_recompiler/frontend/ir/opcodes.inc +++ b/src/shader_recompiler/frontend/ir/opcodes.inc @@ -231,6 +231,7 @@ OPCODE(BitwiseXor32, U32, U32, OPCODE(BitFieldInsert, U32, U32, U32, U32, U32, ) OPCODE(BitFieldSExtract, U32, U32, U32, U32, ) OPCODE(BitFieldUExtract, U32, U32, U32, U32, ) +OPCODE(BitReverse32, U32, U32, ) OPCODE(SLessThan, U1, U32, U32, ) OPCODE(ULessThan, U1, U32, U32, ) |