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authorliamwhite <liamwhite@users.noreply.github.com>2022-11-11 14:03:40 +0100
committerGitHub <noreply@github.com>2022-11-11 14:03:40 +0100
commitc973029374a731e13f2de240820c818fa2899c2b (patch)
treeab20b418b3c6465e4e9b9503d8d3744f3560ad4b /src/shader_recompiler/frontend/maxwell
parentMerge pull request #9223 from goldenx86/threadcount (diff)
parentvideo_core: Fix few issues in Tess stage (diff)
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Diffstat (limited to 'src/shader_recompiler/frontend/maxwell')
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
index 52be12f9c..753c62098 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
@@ -117,8 +117,7 @@ enum class SpecialRegister : u64 {
case SpecialRegister::SR_THREAD_KILL:
return IR::U32{ir.Select(ir.IsHelperInvocation(), ir.Imm32(-1), ir.Imm32(0))};
case SpecialRegister::SR_INVOCATION_INFO:
- LOG_WARNING(Shader, "(STUBBED) SR_INVOCATION_INFO");
- return ir.Imm32(0x00ff'0000);
+ return ir.InvocationInfo();
case SpecialRegister::SR_TID: {
const IR::Value tid{ir.LocalInvocationId()};
return ir.BitFieldInsert(ir.BitFieldInsert(IR::U32{ir.CompositeExtract(tid, 0)},