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| author | Subv <subv2112@gmail.com> | 2018-04-20 16:04:54 +0200 |
|---|---|---|
| committer | Subv <subv2112@gmail.com> | 2018-04-20 21:57:40 +0200 |
| commit | d03fc774756306aa8fd89abd5522c928b46336c7 (patch) | |
| tree | 89b74e72ec1dafe6889a34826e383e45c1f80def /src/video_core/engines/shader_bytecode.h | |
| parent | ShaderGen: Ignore the 'sched' instruction when generating shaders. (diff) | |
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Diffstat (limited to 'src/video_core/engines/shader_bytecode.h')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 7cd125f05..b0da805db 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -13,6 +13,9 @@ namespace Tegra { namespace Shader { struct Register { + // Register 255 is special cased to always be 0 + static constexpr size_t ZeroIndex = 255; + constexpr Register() = default; constexpr Register(u64 value) : value(value) {} |