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author | Subv <subv2112@gmail.com> | 2018-02-12 03:34:20 +0100 |
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committer | Subv <subv2112@gmail.com> | 2018-02-12 04:42:48 +0100 |
commit | e01a8f218707b6f3ed0f111c432440b07ea5b6ff (patch) | |
tree | f5a95dc16a129a5c1a8a4d1309dfbbc3e4ccdb3f /src/video_core/engines | |
parent | nvdrv: Make the GPU memory manager available to nvhost-gpu. (diff) | |
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Diffstat (limited to 'src/video_core/engines')
-rw-r--r-- | src/video_core/engines/fermi_2d.cpp | 15 | ||||
-rw-r--r-- | src/video_core/engines/fermi_2d.h | 18 | ||||
-rw-r--r-- | src/video_core/engines/maxwell_3d.cpp | 15 | ||||
-rw-r--r-- | src/video_core/engines/maxwell_3d.h | 18 | ||||
-rw-r--r-- | src/video_core/engines/maxwell_compute.cpp | 15 | ||||
-rw-r--r-- | src/video_core/engines/maxwell_compute.h | 18 |
6 files changed, 99 insertions, 0 deletions
diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp new file mode 100644 index 000000000..3d62c321f --- /dev/null +++ b/src/video_core/engines/fermi_2d.cpp @@ -0,0 +1,15 @@ +// Copyright 2018 yuzu Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#include "video_core/engines/fermi_2d.h" + +namespace Tegra { +namespace Engines { +namespace Fermi2D { + +void WriteReg(u32 method, u32 value) {} + +} // namespace Fermi2D +} // namespace Engines +} // namespace Tegra diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h new file mode 100644 index 000000000..6f3f5dfbc --- /dev/null +++ b/src/video_core/engines/fermi_2d.h @@ -0,0 +1,18 @@ +// Copyright 2018 yuzu Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#pragma once + +#include "common/common_types.h" + +namespace Tegra { +namespace Engines { +namespace Fermi2D { + +void WriteReg(u32 method, u32 value); + +} // namespace Fermi2D + +} // namespace Engines +} // namespace Tegra diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp new file mode 100644 index 000000000..c2697c960 --- /dev/null +++ b/src/video_core/engines/maxwell_3d.cpp @@ -0,0 +1,15 @@ +// Copyright 2018 yuzu Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#include "video_core/engines/maxwell_3d.h" + +namespace Tegra { +namespace Engines { +namespace Maxwell3D { + +void WriteReg(u32 method, u32 value) {} + +} // namespace Maxwell3D +} // namespace Engines +} // namespace Tegra diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h new file mode 100644 index 000000000..6957fb721 --- /dev/null +++ b/src/video_core/engines/maxwell_3d.h @@ -0,0 +1,18 @@ +// Copyright 2018 yuzu Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#pragma once + +#include "common/common_types.h" + +namespace Tegra { +namespace Engines { +namespace Maxwell3D { + +void WriteReg(u32 method, u32 value); + +} // namespace Maxwell3D + +} // namespace Engines +} // namespace Tegra diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp new file mode 100644 index 000000000..c2134d63b --- /dev/null +++ b/src/video_core/engines/maxwell_compute.cpp @@ -0,0 +1,15 @@ +// Copyright 2018 yuzu Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#include "video_core/engines/maxwell_compute.h" + +namespace Tegra { +namespace Engines { +namespace MaxwellCompute { + +void WriteReg(u32 method, u32 value) {} + +} // namespace MaxwellCompute +} // namespace Engines +} // namespace Tegra diff --git a/src/video_core/engines/maxwell_compute.h b/src/video_core/engines/maxwell_compute.h new file mode 100644 index 000000000..dc9a13593 --- /dev/null +++ b/src/video_core/engines/maxwell_compute.h @@ -0,0 +1,18 @@ +// Copyright 2018 yuzu Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#pragma once + +#include "common/common_types.h" + +namespace Tegra { +namespace Engines { +namespace MaxwellCompute { + +void WriteReg(u32 method, u32 value); + +} // namespace MaxwellCompute + +} // namespace Engines +} // namespace Tegra |