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authorDavid Marcec <dmarcecguzman@gmail.com>2018-09-01 08:34:27 +0200
committerDavid Marcec <dmarcecguzman@gmail.com>2018-09-01 08:34:27 +0200
commitad3dca7e62373fe9d7df50414178fe65322e6a06 (patch)
tree640c076e8a3d49960f07d8ce6a53449e0a9523df /src/video_core/renderer_opengl
parentMerge pull request #1196 from FearlessTobi/ccache-consistency (diff)
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Diffstat (limited to 'src/video_core/renderer_opengl')
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 391c92d47..e3a82b0c9 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -2110,8 +2110,12 @@ private:
case OpCode::Id::IPA: {
const auto& attribute = instr.attribute.fmt28;
const auto& reg = instr.gpr0;
- switch (instr.ipa.mode) {
- case Tegra::Shader::IpaMode::Pass:
+ ASSERT_MSG(instr.ipa.sample_mode == Tegra::Shader::IpaSampleMode::Default,
+ "Unhandled IPA sample mode: {}",
+ static_cast<u32>(instr.ipa.sample_mode.Value()));
+ ASSERT_MSG(instr.ipa.saturate == 0, "IPA saturate not implemented");
+ switch (instr.ipa.interp_mode) {
+ case Tegra::Shader::IpaInterpMode::Linear:
if (stage == Maxwell3D::Regs::ShaderStage::Fragment &&
attribute.index == Attribute::Index::Position) {
switch (attribute.element) {
@@ -2132,12 +2136,12 @@ private:
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
}
break;
- case Tegra::Shader::IpaMode::None:
+ case Tegra::Shader::IpaInterpMode::Perspective:
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
break;
default:
LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}",
- static_cast<u32>(instr.ipa.mode.Value()));
+ static_cast<u32>(instr.ipa.interp_mode.Value()));
UNREACHABLE();
regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
}