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authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-21 03:57:09 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:50 +0100
commit06cb910c6d9b0be664db4305f90974198f84ae98 (patch)
treeb1e194f9b560bdbb97d2334363ddf63dfd336e49 /src/video_core/shader
parentshader_decode: Implement FMNMX_C, FMNMX_R and FMNMX_IMM (diff)
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Diffstat (limited to 'src/video_core/shader')
-rw-r--r--src/video_core/shader/decode/arithmetic.cpp9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic.cpp b/src/video_core/shader/decode/arithmetic.cpp
index 0b6654397..9f8c27b3e 100644
--- a/src/video_core/shader/decode/arithmetic.cpp
+++ b/src/video_core/shader/decode/arithmetic.cpp
@@ -140,6 +140,15 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
Operation(OperationCode::Select, NO_PRECISE, condition, min, max));
break;
}
+ case OpCode::Id::RRO_C:
+ case OpCode::Id::RRO_R:
+ case OpCode::Id::RRO_IMM: {
+ // Currently RRO is only implemented as a register move.
+ op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b);
+ SetRegister(bb, instr.gpr0, op_b);
+ LOG_WARNING(HW_GPU, "RRO instruction is incomplete");
+ break;
+ }
default:
UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName());
}