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author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2018-12-21 04:11:33 +0100 |
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committer | ReinUsesLisp <reinuseslisp@airmail.cc> | 2019-01-15 21:54:50 +0100 |
commit | 8215ae942c72ec20c2ebebbf8fc5784e3f21bb3c (patch) | |
tree | 4e5932333ba21201504a9570472804e120e77653 /src/video_core/shader | |
parent | shader_decode: Implement IPA (diff) | |
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Diffstat (limited to 'src/video_core/shader')
-rw-r--r-- | src/video_core/shader/decode/other.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index ffdc77d90..3f058324c 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -11,6 +11,7 @@ namespace VideoCommon::Shader { using Tegra::Shader::Instruction; using Tegra::Shader::OpCode; +using Tegra::Shader::ConditionCode; u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { const Instruction instr = {program_code[pc]}; @@ -45,6 +46,17 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { } break; } + case OpCode::Id::BRA: { + UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0, + "BRA with constant buffers are not implemented"); + + const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; + UNIMPLEMENTED_IF(cc != Tegra::Shader::ConditionCode::T); + + const u32 target = pc + instr.bra.GetBranchTarget(); + bb.push_back(Operation(OperationCode::Bra, Immediate(target))); + break; + } case OpCode::Id::IPA: { const auto& attribute = instr.attribute.fmt28; const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(), |