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author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2018-12-18 02:18:46 +0100 |
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committer | ReinUsesLisp <reinuseslisp@airmail.cc> | 2019-01-15 21:54:52 +0100 |
commit | 376a8375118937c577063c5d92ad33cfdc33439b (patch) | |
tree | ff8ad6be514928e0c6774fe2b37eb99e03665c70 /src/video_core | |
parent | shader_decode: Implement IMNMX (diff) | |
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Diffstat (limited to 'src/video_core')
-rw-r--r-- | src/video_core/shader/decode/other.cpp | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 5b3f9aa30..9200b5da9 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp @@ -46,6 +46,33 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { } break; } + case OpCode::Id::KIL: { + UNIMPLEMENTED_IF(instr.flow.cond != Tegra::Shader::FlowCondition::Always); + + const Tegra::Shader::ConditionCode cc = instr.flow_condition_code; + UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "KIL condition code used: {}", + static_cast<u32>(cc)); + + bb.push_back(Operation(OperationCode::Kil)); + break; + } + case OpCode::Id::MOV_SYS: { + switch (instr.sys20) { + case Tegra::Shader::SystemVariable::InvocationInfo: { + LOG_WARNING(HW_GPU, "MOV_SYS instruction with InvocationInfo is incomplete"); + SetRegister(bb, instr.gpr0, Immediate(0u)); + break; + } + case Tegra::Shader::SystemVariable::Ydirection: { + // Config pack's third value is Y_NEGATE's state. + SetRegister(bb, instr.gpr0, Operation(OperationCode::YNegate)); + break; + } + default: + UNIMPLEMENTED_MSG("Unhandled system move: {}", static_cast<u32>(instr.sys20.Value())); + } + break; + } case OpCode::Id::BRA: { UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0, "BRA with constant buffers are not implemented"); |