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authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-21 03:59:01 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:50 +0100
commitea358bd4bf70b6b93b4022ede7a8bcd111f10f9e (patch)
treeadac0a6f611770f77d6d8dd147e340b5b7d482ce /src/video_core
parentshader_decode: Implement FMUL32_IMM (diff)
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Diffstat (limited to 'src/video_core')
-rw-r--r--src/video_core/shader/decode/arithmetic_immediate.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic_immediate.cpp b/src/video_core/shader/decode/arithmetic_immediate.cpp
index 0e4cbccab..996b2537a 100644
--- a/src/video_core/shader/decode/arithmetic_immediate.cpp
+++ b/src/video_core/shader/decode/arithmetic_immediate.cpp
@@ -31,6 +31,18 @@ u32 ShaderIR::DecodeArithmeticImmediate(BasicBlock& bb, u32 pc) {
SetRegister(bb, instr.gpr0, value);
break;
}
+ case OpCode::Id::FADD32I: {
+ UNIMPLEMENTED_IF_MSG(instr.op_32.generates_cc,
+ "Condition codes generation in FADD32I is not implemented");
+ const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fadd32i.abs_a,
+ instr.fadd32i.negate_a);
+ const Node op_b = GetOperandAbsNegFloat(GetImmediate32(instr), instr.fadd32i.abs_b,
+ instr.fadd32i.negate_b);
+
+ const Node value = Operation(OperationCode::FAdd, PRECISE, op_a, op_b);
+ SetRegister(bb, instr.gpr0, value);
+ break;
+ }
default:
UNIMPLEMENTED_MSG("Unhandled arithmetic immediate instruction: {}",
opcode->get().GetName());