summaryrefslogtreecommitdiffstats
path: root/src
diff options
context:
space:
mode:
authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-23 21:07:49 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:52 +0100
commit7e13e8bfcb4d3bb3c9d7eafb81e790e244cdfdd7 (patch)
tree2474cbdb79a13858ab0c64a86c00353a947ecf9b /src
parentshader_decode: Implement HFMA2 (diff)
downloadyuzu-7e13e8bfcb4d3bb3c9d7eafb81e790e244cdfdd7.tar
yuzu-7e13e8bfcb4d3bb3c9d7eafb81e790e244cdfdd7.tar.gz
yuzu-7e13e8bfcb4d3bb3c9d7eafb81e790e244cdfdd7.tar.bz2
yuzu-7e13e8bfcb4d3bb3c9d7eafb81e790e244cdfdd7.tar.lz
yuzu-7e13e8bfcb4d3bb3c9d7eafb81e790e244cdfdd7.tar.xz
yuzu-7e13e8bfcb4d3bb3c9d7eafb81e790e244cdfdd7.tar.zst
yuzu-7e13e8bfcb4d3bb3c9d7eafb81e790e244cdfdd7.zip
Diffstat (limited to 'src')
-rw-r--r--src/video_core/shader/decode/predicate_set_register.cpp17
1 files changed, 16 insertions, 1 deletions
diff --git a/src/video_core/shader/decode/predicate_set_register.cpp b/src/video_core/shader/decode/predicate_set_register.cpp
index 67a06b5b4..04ddd9f9e 100644
--- a/src/video_core/shader/decode/predicate_set_register.cpp
+++ b/src/video_core/shader/decode/predicate_set_register.cpp
@@ -16,7 +16,22 @@ u32 ShaderIR::DecodePredicateSetRegister(BasicBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr);
- UNIMPLEMENTED();
+ UNIMPLEMENTED_IF_MSG(instr.generates_cc,
+ "Condition codes generation in PSET is not implemented");
+
+ const Node op_a = GetPredicate(instr.pset.pred12, instr.pset.neg_pred12 != 0);
+ const Node op_b = GetPredicate(instr.pset.pred29, instr.pset.neg_pred29 != 0);
+ const Node first_pred = Operation(GetPredicateCombiner(instr.pset.cond), op_a, op_b);
+
+ const Node second_pred = GetPredicate(instr.pset.pred39, instr.pset.neg_pred39 != 0);
+
+ const OperationCode combiner = GetPredicateCombiner(instr.pset.op);
+ const Node result = Operation(combiner, first_pred, second_pred);
+
+ const Node true_value = instr.pset.bf ? Immediate(1.0f) : Immediate(0xffffffff);
+ const Node false_value = instr.pset.bf ? Immediate(0.0f) : Immediate(0);
+ const Node value = Operation(OperationCode::Select, PRECISE, true_value, false_value);
+ SetRegister(bb, instr.gpr0, value);
return pc;
}