diff options
Diffstat (limited to 'src/core')
| -rw-r--r-- | src/core/arm/interpreter/arminit.cpp | 9 | ||||
| -rw-r--r-- | src/core/arm/interpreter/armsupp.cpp | 5 |
2 files changed, 10 insertions, 4 deletions
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp index 710115375..c6b8197f6 100644 --- a/src/core/arm/interpreter/arminit.cpp +++ b/src/core/arm/interpreter/arminit.cpp @@ -16,6 +16,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <cstring> +#include "core/mem_map.h" #include "core/arm/skyeye_common/armdefs.h" #include "core/arm/skyeye_common/armemu.h" @@ -138,8 +139,16 @@ void ARMul_Reset(ARMul_State* state) state->Bank = SVCBANK; FLUSHPIPE; + // Reset CP15 ResetMPCoreCP15Registers(state); + // This is separate from the CP15 register reset function, as + // this isn't an ARM-defined reset value; it's set by the 3DS. + // + // TODO: Whenever TLS is implemented, this should contain + // the address of the 0x200-byte TLS + state->CP15[CP15(CP15_THREAD_URO)] = Memory::KERNEL_MEMORY_VADDR; + state->EndCondition = 0; state->ErrorCode = 0; diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp index 6a11a5804..f28fd8c9d 100644 --- a/src/core/arm/interpreter/armsupp.cpp +++ b/src/core/arm/interpreter/armsupp.cpp @@ -227,11 +227,8 @@ u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcod if (opcode_2 == 2) return cpu->CP15[CP15(CP15_THREAD_UPRW)]; - // TODO: Whenever TLS is implemented, this should return - // "cpu->CP15[CP15(CP15_THREAD_URO)];" - // which contains the address of the 0x200-byte TLS if (opcode_2 == 3) - return Memory::KERNEL_MEMORY_VADDR; + return cpu->CP15[CP15(CP15_THREAD_URO)]; } if (InAPrivilegedMode(cpu)) |