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-rw-r--r--src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp1
-rw-r--r--src/video_core/dma_pusher.cpp26
-rw-r--r--src/video_core/dma_pusher.h3
3 files changed, 1 insertions, 29 deletions
diff --git a/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp b/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp
index 152019548..b1d9d55b5 100644
--- a/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp
+++ b/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp
@@ -214,7 +214,6 @@ u32 nvhost_gpu::SubmitGPFIFOImpl(IoctlSubmitGpfifo& params, std::vector<u8>& out
params.fence_out.value = syncpoint_manager.GetSyncpointMax(params.fence_out.id);
}
- entries.RefreshIntegrityChecks(gpu);
gpu.PushGPUEntries(std::move(entries));
if (params.flags.add_increment.Value()) {
diff --git a/src/video_core/dma_pusher.cpp b/src/video_core/dma_pusher.cpp
index 105b85a92..d8801b1f5 100644
--- a/src/video_core/dma_pusher.cpp
+++ b/src/video_core/dma_pusher.cpp
@@ -13,20 +13,6 @@
namespace Tegra {
-void CommandList::RefreshIntegrityChecks(GPU& gpu) {
- command_list_hashes.resize(command_lists.size());
-
- for (std::size_t index = 0; index < command_lists.size(); ++index) {
- const CommandListHeader command_list_header = command_lists[index];
- std::vector<CommandHeader> command_headers(command_list_header.size);
- gpu.MemoryManager().ReadBlockUnsafe(command_list_header.addr, command_headers.data(),
- command_list_header.size * sizeof(u32));
- command_list_hashes[index] =
- Common::CityHash64(reinterpret_cast<char*>(command_headers.data()),
- command_list_header.size * sizeof(u32));
- }
-}
-
DmaPusher::DmaPusher(Core::System& system, GPU& gpu) : gpu{gpu}, system{system} {}
DmaPusher::~DmaPusher() = default;
@@ -77,8 +63,7 @@ bool DmaPusher::Step() {
dma_pushbuffer.pop();
} else {
const CommandListHeader command_list_header{
- command_list.command_lists[dma_pushbuffer_subindex]};
- const u64 next_hash = command_list.command_list_hashes[dma_pushbuffer_subindex++];
+ command_list.command_lists[dma_pushbuffer_subindex++]};
const GPUVAddr dma_get = command_list_header.addr;
if (dma_pushbuffer_subindex >= command_list.command_lists.size()) {
@@ -95,15 +80,6 @@ bool DmaPusher::Step() {
command_headers.resize(command_list_header.size);
gpu.MemoryManager().ReadBlockUnsafe(dma_get, command_headers.data(),
command_list_header.size * sizeof(u32));
-
- // Integrity check
- const u64 new_hash = Common::CityHash64(reinterpret_cast<char*>(command_headers.data()),
- command_list_header.size * sizeof(u32));
- if (new_hash != next_hash) {
- LOG_CRITICAL(HW_GPU, "CommandList at addr=0x{:X} is corrupt, skipping!", dma_get);
- dma_pushbuffer.pop();
- return true;
- }
}
for (std::size_t index = 0; index < command_headers.size();) {
const CommandHeader& command_header = command_headers[index];
diff --git a/src/video_core/dma_pusher.h b/src/video_core/dma_pusher.h
index 9d9a750d9..96ac267f7 100644
--- a/src/video_core/dma_pusher.h
+++ b/src/video_core/dma_pusher.h
@@ -90,10 +90,7 @@ struct CommandList final {
explicit CommandList(std::vector<Tegra::CommandHeader>&& prefetch_command_list)
: prefetch_command_list{std::move(prefetch_command_list)} {}
- void RefreshIntegrityChecks(GPU& gpu);
-
std::vector<Tegra::CommandListHeader> command_lists;
- std::vector<u64> command_list_hashes;
std::vector<Tegra::CommandHeader> prefetch_command_list;
};