diff options
Diffstat (limited to 'private/ntos/nthals/haltimbr/alpha')
57 files changed, 3207 insertions, 0 deletions
diff --git a/private/ntos/nthals/haltimbr/alpha/28f008sa.c b/private/ntos/nthals/haltimbr/alpha/28f008sa.c new file mode 100644 index 000000000..2865a2061 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/28f008sa.c @@ -0,0 +1 @@ +#include "../halalpha/28f008sa.c" diff --git a/private/ntos/nthals/haltimbr/alpha/29f040.c b/private/ntos/nthals/haltimbr/alpha/29f040.c new file mode 100644 index 000000000..2c2b423af --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/29f040.c @@ -0,0 +1 @@ +#include "../halalpha/29f040.c" diff --git a/private/ntos/nthals/haltimbr/alpha/adjust.c b/private/ntos/nthals/haltimbr/alpha/adjust.c new file mode 100644 index 000000000..47c267fb8 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/adjust.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\adjust.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/allstart.c b/private/ntos/nthals/haltimbr/alpha/allstart.c new file mode 100644 index 000000000..42f70b7ca --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/allstart.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\allstart.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/apecs.c b/private/ntos/nthals/haltimbr/alpha/apecs.c new file mode 100644 index 000000000..06eb91348 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/apecs.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\apecs.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/apecserr.c b/private/ntos/nthals/haltimbr/alpha/apecserr.c new file mode 100644 index 000000000..441154cc9 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/apecserr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\apecserr.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/apecsio.s b/private/ntos/nthals/haltimbr/alpha/apecsio.s new file mode 100644 index 000000000..27bb7caa7 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/apecsio.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\apecsio.s" + diff --git a/private/ntos/nthals/haltimbr/alpha/bios.c b/private/ntos/nthals/haltimbr/alpha/bios.c new file mode 100644 index 000000000..3a9d3aa50 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/bios.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\bios.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/busdata.c b/private/ntos/nthals/haltimbr/alpha/busdata.c new file mode 100644 index 000000000..cc2a153c1 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/busdata.c @@ -0,0 +1,125 @@ +/*++ + + +Copyright (c) 1989 Microsoft Corporation +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + busdata.c + +Abstract: + + This module contains get/set bus data routines. + +Author: + + Darryl E. Havens (darrylh) 11-Apr-1990 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#include "halp.h" + +// +// External Function Prototypes +// + +ULONG +HalpNoBusData ( + IN PVOID BusHandler, + IN PVOID RootHandler, + IN ULONG SlotNumber, + IN PVOID Buffer, + IN ULONG Offset, + IN ULONG Length + ); + +#ifdef ALLOC_PRAGMA +#pragma alloc_text(INIT,HalpRegisterInternalBusHandlers) +#endif + + +VOID +HalpRegisterInternalBusHandlers ( + VOID + ) +/*++ + +Routine Description: + + This function registers the bushandlers for buses on the system + that will always be present on the system. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + PBUS_HANDLER Bus; + + // + // Initalize BusHandler data before registering any handlers + // + + HalpInitBusHandler (); + + // + // Build the processor internal bus 0 + // + + HaliRegisterBusHandler (ProcessorInternal, // Bus Type + -1, // No config space + 0, // Bus Number + -1, // No parent bus type + 0, // No parent bus number + 0, // No extension data + NULL, // No install handler + &Bus); // Bushandler return + + Bus->GetInterruptVector = HalpGetSystemInterruptVector; + + // + // Build internal-bus 0, or system level bus + // + + HaliRegisterBusHandler (Internal, // Bus Type + -1, // No config space + 0, // Bus Number + -1, // No parent bus type + 0, // No parent bus number + 0, // No extension data + NULL, // No install handler + &Bus); // Bushandler return + + Bus->GetInterruptVector = HalpGetSystemInterruptVector; + Bus->TranslateBusAddress = HalpTranslateSystemBusAddress; + + // + // Build Isa bus #0 + // + + HaliRegisterBusHandler (Isa, // Bus Type + -1, // No config space + 0, // Internal bus #0 + Internal, // Parent bus type + 0, // Parent bus number + 0, // No extension data + NULL, // No install handler + &Bus); // Bushandler return + + Bus->GetBusData = HalpNoBusData; + Bus->AdjustResourceList = HalpAdjustIsaResourceList; + +} diff --git a/private/ntos/nthals/haltimbr/alpha/cache.c b/private/ntos/nthals/haltimbr/alpha/cache.c new file mode 100644 index 000000000..561528477 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/cache.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\cache.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/cia.c b/private/ntos/nthals/haltimbr/alpha/cia.c new file mode 100644 index 000000000..7948bfe16 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/cia.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\cia.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/ciaaddr.c b/private/ntos/nthals/haltimbr/alpha/ciaaddr.c new file mode 100644 index 000000000..b85818ac0 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ciaaddr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ciaaddr.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/ciaerr.c b/private/ntos/nthals/haltimbr/alpha/ciaerr.c new file mode 100644 index 000000000..bfb9efc93 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ciaerr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ciaerr.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/ciaio.s b/private/ntos/nthals/haltimbr/alpha/ciaio.s new file mode 100644 index 000000000..16202a7e1 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ciaio.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ciaio.s" + diff --git a/private/ntos/nthals/haltimbr/alpha/ciamapio.c b/private/ntos/nthals/haltimbr/alpha/ciamapio.c new file mode 100644 index 000000000..3e9f7a9c1 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ciamapio.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ciamapio.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/cmos8k.c b/private/ntos/nthals/haltimbr/alpha/cmos8k.c new file mode 100644 index 000000000..091dfa410 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/cmos8k.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\cmos8k.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/devintr.s b/private/ntos/nthals/haltimbr/alpha/devintr.s new file mode 100644 index 000000000..d861febd2 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/devintr.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\devintr.s" + diff --git a/private/ntos/nthals/haltimbr/alpha/eb164.h b/private/ntos/nthals/haltimbr/alpha/eb164.h new file mode 100644 index 000000000..700aa4e34 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/eb164.h @@ -0,0 +1,120 @@ +/*++ + +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + eb164.h + +Abstract: + + This file contains definitions specific to the EB164 platform. + +Author: + + Joe Notarangelo 06-Sep-1994 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#ifndef _EB164H_ +#define _EB164H_ + +// +// Include definitions for the components that make up EB164. +// + +#include "axp21164.h" // 21164 (EV5) microprocessor definitions +#include "cia.h" // CIA controller definitions + +// +// Define number of PCI, ISA, and combo slots +// + +#define NUMBER_ISA_SLOTS 3 +#define NUMBER_PCI_SLOTS 4 +#define NUMBER_COMBO_SLOTS 1 + +// +// PCI bus address values: +// + +#define PCI_MAX_LOCAL_DEVICE (PCI_MAX_DEVICES - 1) +#define PCI_MAX_INTERRUPT_VECTOR (MAXIMUM_PCI_VECTOR - PCI_VECTORS) +#define PCI_MAX_INTERRUPT (0x15) + +// +// Define numbers and names of cpus. +// + +#define HAL_PRIMARY_PROCESSOR ((ULONG)0) +#define HAL_MAXIMUM_PROCESSOR ((ULONG)0) + +// +// Define default processor frequency. +// + +#define DEFAULT_PROCESSOR_FREQUENCY_MHZ (250) + +// +// Define EB164-specific routines that are really macros for performance. +// + +#define HalpAcknowledgeEisaInterrupt(x) INTERRUPT_ACKNOWLEDGE(x) + +// +// Define the per-processor data structures allocated in the PCR. +// + +typedef struct _EB164_PCR{ + ULONGLONG HalpCycleCount; // 64-bit per-processor cycle count + ULONG Reserved[3]; // Pad ProfileCount to offset 20 + EV5ProfileCount ProfileCount; // Profile counter state + } EB164_PCR, *PEB164_PCR; + +#define HAL_PCR ( (PEB164_PCR)(&(PCR->HalReserved)) ) + +// +// Define the locations of the interrupt mask registers. +// + +#define INTERRUPT_MASK0_QVA \ + ((ULONG)HAL_MAKE_QVA(CIA_PCI_SPARSE_IO_PHYSICAL) + 0x804) +#define INTERRUPT_MASK1_QVA \ + ((ULONG)HAL_MAKE_QVA(CIA_PCI_SPARSE_IO_PHYSICAL) + 0x805) +#define INTERRUPT_MASK2_QVA \ + ((ULONG)HAL_MAKE_QVA(CIA_PCI_SPARSE_IO_PHYSICAL) + 0x806) + +// +// Define the location of the flash environment block +// + +#define NVRAM_ENVIRONMENT_QVA \ + ((ULONG)HAL_MAKE_QVA(CIA_PCI_SPARSE_MEMORY_PHYSICAL) + 0xf0000) + +#define CIA_MCR_QVA ((ULONG)HAL_MAKE_QVA(CIA_MEMORY_CSRS_PHYSICAL)) + +// +// Define EB164 SIO dispatch +// +BOOLEAN +HalpEB164SioDispatch( + PKINTERRUPT Interrupt, + PVOID ServiceContext, + PKTRAP_FRAME TrapFrame + ); + +typedef BOOLEAN (*PEB164_SECOND_LEVEL_DISPATCH)( + PKINTERRUPT Interrupt, + PVOID ServiceContext, + PKTRAP_FRAME TrapFrame + ); + +#endif //_EB164H_ + diff --git a/private/ntos/nthals/haltimbr/alpha/eb164err.c b/private/ntos/nthals/haltimbr/alpha/eb164err.c new file mode 100644 index 000000000..d305a0704 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/eb164err.c @@ -0,0 +1,122 @@ +/*++ + +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + eb164err.c + +Abstract: + + This module implements error handling (machine checks and error + interrupts) for the EB164 platform. + +Author: + + Joe Notarangelo 06-Sep-1994 + +Environment: + + Kernel mode only. + +Revision History: + +--*/ + +#include "halp.h" +#include "eb164.h" + +// +// Declare the extern variable UncorrectableError declared in +// inithal.c. +// +extern PERROR_FRAME PUncorrectableError; + + +VOID +HalpErrorInterrupt( + VOID + ) +/*++ + +Routine Description: + + This routine is the interrupt handler for an EB164 machine check interrupt + The function calls HalpCiaReportFatalError() + +Arguments: + + None. + +Return Value: + + None. If a Fatal Error is detected the system is crashed. + +--*/ +{ + + HalAcquireDisplayOwnership(NULL); + + // + // Display the dreaded banner. + // + + HalDisplayString( "\nFatal system hardware error.\n\n" ); + + // + // Report the error and crash the system + // + + HalpCiaReportFatalError(); + + KeBugCheckEx( DATA_BUS_ERROR, + 0xfacefeed, //jnfix - quick error interrupt id + 0, + 0, + (ULONG)PUncorrectableError ); + + + return; // never +} + + +BOOLEAN +HalpPlatformMachineCheck( + IN PEXCEPTION_RECORD ExceptionRecord, + IN PKEXCEPTION_FRAME ExceptionFrame, + IN PKTRAP_FRAME TrapFrame + ) +/*++ + +Routine Description: + + This routine is given control when an hard error is acknowledged + by the CIA chipset. The routine is given the chance to + correct and dismiss the error. + +Arguments: + + ExceptionRecord - Supplies a pointer to the exception record generated + at the point of the exception. + + ExceptionFrame - Supplies a pointer to the exception frame generated + at the point of the exception. + + TrapFrame - Supplies a pointer to the trap frame generated + at the point of the exception. + +Return Value: + + TRUE is returned if the machine check has been handled and dismissed - + indicating that execution can continue. FALSE is return otherwise. + +--*/ +{ + // + // All machine check handling is determined by the CIA + // + + return(HalpCiaMachineCheck( ExceptionRecord, + ExceptionFrame, + TrapFrame )); +} diff --git a/private/ntos/nthals/haltimbr/alpha/eb164io.s b/private/ntos/nthals/haltimbr/alpha/eb164io.s new file mode 100644 index 000000000..74e586ff2 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/eb164io.s @@ -0,0 +1,139 @@ + +/*++ + +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + eb164io.s + +Abstract: + + This module implements flashrom I/O access routines for EB164. + +Author: + + Chao Chen 14-Sep-1994 + Joe Notarangelo 14-Sep-1994 + Jeff Wiedermeier 14-Sep-1994 + +Environment: + + Executes in kernel mode. + +Revision History: + + +--*/ + +#include "halalpha.h" + +#define EB164_FLASH_BASE -0x37a9 // negative of 0xc857 +#define CIA_SPARSE_IO_SVA -0x37a8 // negative of 0xc858 +#define IO_BIT_SHIFT 5 + + +//++ +// +// UCHAR +// EB164_READ_FLASH_BYTE( +// ULONG Offset +// ) +// +// Routine Description: +// +// Read a byte of data from the flash rom at the specified offset. +// +// Arguments: +// +// Offset (a0) - Supplies a byte offset from the base of the flash rom. +// +// Return Value: +// +// (v0) Returns the byte of data read from the flash rom. +// +//-- + + LEAF_ENTRY(EB164_READ_FLASH_BYTE) + + and a0, 3, t2 // save byte lane to read + + srl a0, 19,t1 // get bank select to lsb + and t1, 1, t1 // mask it + lda t3, CIA_SPARSE_IO_SVA(zero) // 0xffff ffff ffff c858 + sll t3, 28, t3 // 0xffff fc85 8000 0000 + lda t4, 0x800(zero) // get port number for bank sel + sll t4, IO_BIT_SHIFT, t4 // put it in place + or t3, t4, t3 // and merge it + stl t1, 0(t3) // write the bank select + mb + + lda t0, EB164_FLASH_BASE(zero) // 0xffff ffff ffff c857 + sll t0, 4, t0 // 0xffff ffff fffc 8570 + lda t0, 0xf(t0) // 0xffff ffff fffc 857f + sll t0, 24, t0 // 0xffff fc85 7f00 0000 + + sll a0, IO_BIT_SHIFT, a0 // shift offset to sparse space + bis t0, a0, t0 // merge offset and base + + ldl v0, 0(t0) // read flash rom + extbl v0, t2, v0 // extract byte from appropriate lane + + ret zero, (ra) // return + + .end EB164_READ_FLASH_BYTE + +//++ +// +// VOID +// EB164_WRITE_FLASH_BYTE( +// ULONG Offset, +// UCHAR Data +// ) +// +// Routine Description: +// +// Write a byte of data to the flash rom at the specified offset. +// +// Arguments: +// +// Offset (a0) - Supplies a byte offset from the base of the flash rom. +// +// Data (a1) - Supplies the data to write. +// +// Return Value: +// +// None. +// +//-- + + LEAF_ENTRY(EB164_WRITE_FLASH_BYTE) + + and a0, 3, t2 // save byte lane to read + + srl a0, 19,t1 // get bank select to lsb + and t1, 1, t1 // mask it + lda t3, CIA_SPARSE_IO_SVA(zero) // 0xffff ffff ffff c858 + sll t3, 28, t3 // 0xffff fc85 8000 0000 + lda t4, 0x800(zero) // get port number for bank sel + sll t4, IO_BIT_SHIFT, t4 // put it in place + or t3, t4, t3 // and merge it + stl t1, 0(t3) // write the bank select + mb + + lda t0, EB164_FLASH_BASE(zero) // 0xffff ffff ffff c857 + sll t0, 4, t0 // 0xffff ffff fffc 8570 + lda t0, 0xf(t0) // 0xffff ffff fffc 857f + sll t0, 24, t0 // 0xffff fc85 7f00 0000 + + sll a0, IO_BIT_SHIFT, a0 // shift offset to sparse space + bis t0, a0, t0 // merge offset and base + + insbl a1, t2, a1 // put data into correct lane + stl a1, 0(t0) // write the flash rom + mb // order the write + + ret zero, (ra) // return + + .end EB164_WRITE_FLASH_BYTE + diff --git a/private/ntos/nthals/haltimbr/alpha/ebinitnt.c b/private/ntos/nthals/haltimbr/alpha/ebinitnt.c new file mode 100644 index 000000000..2e5c96b79 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ebinitnt.c @@ -0,0 +1,658 @@ +/*++ + +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + ebinitnt.c + +Abstract: + + + This module implements the platform-specific initialization for + an EB164 system. + +Author: + + Joe Notarangelo 06-Sep-1994 + +Environment: + + Kernel mode only. + +Revision History: + + +--*/ + +#include "halp.h" +#include "pcrtc.h" +#include "eb164.h" +#include "iousage.h" + +#include "fwcallbk.h" + +#include <ntverp.h> // to get the product build number. +// +// Define extern global buffer for the Uncorrectable Error Frame. +// declared in halalpha\inithal.c +// + +extern PERROR_FRAME PUncorrectableError; + + + +// +// Irql mask and tables +// +// irql 0 - passive +// irql 1 - sfw apc level +// irql 2 - sfw dispatch level +// irql 3 - device low +// irql 4 - device high +// irql 5 - interval clock +// irql 6 - not used +// irql 7 - error, mchk, nmi, performance counters +// +// + +// +// The hardware interrupt pins are used as follows for EB164 +// +// IRQ0 = CIA_INT +// IRQ1 = SYS_INT (PCI and ESC interrupts) +// IRQ2 = Interval Clock +// IRQ3 = Error Interrupts + +// +// Define the bus type, this value allows us to distinguish between +// EISA and ISA systems. We're only interested in distinguishing +// between just those two buses. +// + +ULONG HalpBusType = MACHINE_TYPE_ISA; + +// +// Define global data used to communicate new clock rates to the clock +// interrupt service routine. +// + +ULONG HalpCurrentTimeIncrement; +ULONG HalpNextRateSelect; +ULONG HalpNextTimeIncrement; +ULONG HalpNewTimeIncrement; + +// +// External references. +// + +extern ULONG HalDisablePCIParityChecking; + +// +// Function prototypes. +// + +BOOLEAN +HalpInitializeEB164Interrupts ( + VOID + ); + +VOID +HalpParseLoaderBlock( + PLOADER_PARAMETER_BLOCK LoaderBlock + ); + +VOID +HalpErrorInterrupt( + VOID + ); + +BOOLEAN +HalpInitializeInterrupts ( + VOID + ) + +/*++ + +Routine Description: + + This function initializes interrupts for an EB164 system. + +Arguments: + + None. + +Return Value: + + A value of TRUE is returned if the initialization is successfully + completed. Otherwise a value of FALSE is returned. + +--*/ + +{ + + extern ULONG Halp21164CorrectedErrorInterrupt(); + extern ULONG HalpCiaErrorInterrupt(); + extern ULONG HalpDeviceInterrupt(); + extern ULONG HalpHaltInterrupt(); + ULONG Vector; + + // + // Initialize HAL processor parameters based on estimated CPU speed. + // This must be done before HalpStallExecution is called. Compute integral + // megahertz first to avoid rounding errors due to imprecise cycle clock + // period values. + // + + HalpInitializeProcessorParameters(); + + // + // Start the periodic interrupt from the RTC + // + + HalpProgramIntervalTimer(MAXIMUM_RATE_SELECT); + + // + // Initialize EB164 interrupts. + // + + HalpInitializeEB164Interrupts(); + + // + // Initialize the EV5 (21164) interrupts. + // + + HalpInitialize21164Interrupts(); + + PCR->InterruptRoutine[EV5_IRQ0_VECTOR] = (PKINTERRUPT_ROUTINE)HalpCiaErrorInterrupt; + + PCR->InterruptRoutine[EV5_IRQ1_VECTOR] = (PKINTERRUPT_ROUTINE)HalpDeviceInterrupt; + + PCR->InterruptRoutine[EV5_IRQ2_VECTOR] = (PKINTERRUPT_ROUTINE)HalpClockInterrupt; + + PCR->InterruptRoutine[EV5_HALT_VECTOR] = (PKINTERRUPT_ROUTINE)HalpHaltInterrupt; + + PCR->InterruptRoutine[EV5_MCHK_VECTOR] = (PKINTERRUPT_ROUTINE)HalpErrorInterrupt; + + PCR->InterruptRoutine[EV5_CRD_VECTOR] = (PKINTERRUPT_ROUTINE)Halp21164CorrectedErrorInterrupt; + + HalpStart21164Interrupts(); + + + return TRUE; + +} + + +VOID +HalpSetTimeIncrement( + VOID + ) +/*++ + +Routine Description: + + This routine is responsible for setting the time increment for an EV4 + based machine via a call into the kernel. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + // + // Set the time increment value. + // + + HalpCurrentTimeIncrement = MAXIMUM_INCREMENT; + HalpNextTimeIncrement = MAXIMUM_INCREMENT; + HalpNextRateSelect = 0; + KeSetTimeIncrement( MAXIMUM_INCREMENT, MINIMUM_INCREMENT ); + +} + + + +// +// Define global data used to calibrate and stall processor execution. +// + +ULONG HalpProfileCountRate; + +VOID +HalpInitializeClockInterrupts( + VOID + ) + +/*++ + +Routine Description: + + This function is called during phase 1 initialization to complete + the initialization of clock interrupts. For EV4, this function + connects the true clock interrupt handler and initializes the values + required to handle profile interrupts. + +Arguments: + + None. + +Return Value: + + None. + +--*/ + +{ + + // + // Compute the profile interrupt rate. + // + + HalpProfileCountRate = ((1000 * 1000 * 10) / KeQueryTimeIncrement()); + + return; +} + + +VOID +HalpEstablishErrorHandler( + VOID + ) +/*++ + +Routine Description: + + This routine performs the initialization necessary for the HAL to + begin servicing machine checks. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + BOOLEAN PciParityChecking; + BOOLEAN ReportCorrectables; + + // + // Connect the machine check handler via the PCR. + // + + PCR->MachineCheckError = HalMachineCheck; + + HalpInitializeCiaMachineChecks( ReportCorrectables = FALSE, + PciParityChecking = FALSE ); + + return; +} + + +VOID +HalpInitializeMachineDependent( + IN ULONG Phase, + IN PLOADER_PARAMETER_BLOCK LoaderBlock + ) +/*++ + +Routine Description: + + This function performs any EV4-specific initialization based on + the current phase on initialization. + +Arguments: + + Phase - Supplies an indicator for phase of initialization, phase 0 or + phase 1. + + LoaderBlock - supplies a pointer to the loader block. + +Return Value: + + None. + +--*/ +{ + ULONG BusIrql; + ULONG BusNumber; + BOOLEAN ReportCorrectables; + BOOLEAN PciParityChecking; + + // + // Since we have a flash device mapped in PCI memory space, but its + // HAL driver is pretending to be a cmos8k driver - override the + // HalpCMOSRamBase value set in HalpMapIoSpace (ciamapio.c) with the + // correct QVA to reach the environment block in the flash through + // the SIO. + // + HalpCMOSRamBase = (PVOID)NVRAM_ENVIRONMENT_QVA; + + if( Phase == 0 ){ + + // + // Phase 0 Initialization. + // + +#ifdef HALDBG + DbgPrint("LOOK AT THIS ONE\r\n"); + DumpCia(CiaGeneralRegisters | + CiaErrorRegisters | + CiaScatterGatherRegisters); +#endif + // + // Parse the Loader Parameter block looking for PCI entry to determine + // if PCI parity should be disabled + // + + HalpParseLoaderBlock( LoaderBlock ); + + // + // Establish the error handler, to reflect the PCI parity checking. + // + + PciParityChecking = (BOOLEAN)(HalDisablePCIParityChecking == 0); + + HalpInitializeCiaMachineChecks(ReportCorrectables = TRUE, + PciParityChecking); + + } else { + + // + // Phase 1 Initialization. + // + + // + // Initialize the existing bus handlers. + // + + HalpRegisterInternalBusHandlers(); + + // + // Initialize PCI Bus. + // + + HalpInitializePCIBus(LoaderBlock); + + // + // Initialize profiler. + // + + HalpInitializeProfiler(); + + } + + return; + +} + + +ULONG +HalSetTimeIncrement ( + IN ULONG DesiredIncrement + ) + +/*++ + +Routine Description: + + This function is called to set the clock interrupt rate to the frequency + required by the specified time increment value. + +Arguments: + + DesiredIncrement - Supplies desired number of 100ns units between clock + interrupts. + +Return Value: + + The actual time increment in 100ns units. + +--*/ + +{ + ULONG NewTimeIncrement; + ULONG NextRateSelect; + KIRQL OldIrql; + + // + // Raise IRQL to the highest level, set the new clock interrupt + // parameters, lower IRQl, and return the new time increment value. + // + + KeRaiseIrql(HIGH_LEVEL, &OldIrql); + + if (DesiredIncrement < MINIMUM_INCREMENT) { + DesiredIncrement = MINIMUM_INCREMENT; + } + if (DesiredIncrement > MAXIMUM_INCREMENT) { + DesiredIncrement = MAXIMUM_INCREMENT; + } + + // + // Find the allowed increment that is less than or equal to + // the desired increment. + // + + if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS4) { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS4; + NextRateSelect = RTC_RATE_SELECT4; + } else if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS3) { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS3; + NextRateSelect = RTC_RATE_SELECT3; + } else if (DesiredIncrement >= RTC_PERIOD_IN_CLUNKS2) { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS2; + NextRateSelect = RTC_RATE_SELECT2; + } else { + NewTimeIncrement = RTC_PERIOD_IN_CLUNKS1; + NextRateSelect = RTC_RATE_SELECT1; + } + + HalpNextRateSelect = NextRateSelect; + HalpNewTimeIncrement = NewTimeIncrement; + + KeLowerIrql(OldIrql); + + return NewTimeIncrement; +} + + +// +//jnfix +// +// This routine is bogus and does not apply to EB164 and the call should be +// ripped out of fwreturn (or at least changed to something that is more +// abstract). +// + +VOID +HalpResetHAERegisters( + VOID + ) +{ + return; +} + + +VOID +HalpGetMachineDependentErrorFrameSizes( + PULONG RawProcessorSize, + PULONG RawSystemInfoSize + ) +/*++ + +Routine Description: + + This function returns the size of the system specific structures. + + +Arguments: + + RawProcessorSize - Pointer to a buffer that will receive the + size of the processor specific error information buffer. + + RawSystemInfoSize - Pointer to a buffer that will receive the + size of the system specific error information buffer. + +Return Value: + + none + +--*/ +{ + *RawProcessorSize = sizeof(PROCESSOR_EV5_UNCORRECTABLE); + *RawSystemInfoSize = sizeof(CIA_UNCORRECTABLE_FRAME); + return; +} + + +VOID +HalpGetSystemInfo(SYSTEM_INFORMATION *SystemInfo) +/*++ + +Routine Description: + + This function fills in the System information. + + +Arguments: + + SystemInfo - Pointer to the SYSTEM_INFORMATION buffer that needs + to be filled in. + +Return Value: + + none + +--*/ +{ + char systemtype[] = "eb164"; + EXTENDED_SYSTEM_INFORMATION FwExtSysInfo; + + + VenReturnExtendedSystemInformation(&FwExtSysInfo); + + RtlCopyMemory(SystemInfo->FirmwareRevisionId, + FwExtSysInfo.FirmwareVersion, + 16); + + RtlCopyMemory(SystemInfo->SystemType,systemtype, 8); + + SystemInfo->ClockSpeed = + ((1000 * 1000) + (PCR->CycleClockPeriod >> 1)) / PCR->CycleClockPeriod; + + SystemInfo->SystemRevision = PCR->SystemRevision; + + RtlCopyMemory(SystemInfo->SystemSerialNumber, + PCR->SystemSerialNumber, + 16); + + SystemInfo->SystemVariant = PCR->SystemVariant; + + + SystemInfo->PalMajorVersion = PCR->PalMajorVersion; + SystemInfo->PalMinorVersion = PCR->PalMinorVersion; + + SystemInfo->OsRevisionId = VER_PRODUCTBUILD; + + // + // For now fill in dummy values. + // + SystemInfo->ModuleVariant = 1UL; + SystemInfo->ModuleRevision = 1UL; + SystemInfo->ModuleSerialNumber = 0; + + return; +} + +VOID +HalpInitializeUncorrectableErrorFrame ( + VOID + ) +/*++ + +Routine Description: + + This function Allocates an Uncorrectable Error frame for this + system and initializes the frame with certain constant/global + values. + + This is routine called during machine dependent system + Initialization. + +Arguments: + + none + +Return Value: + + none + +--*/ +{ + PROCESSOR_EV5_UNCORRECTABLE processorFrame; + + // + // If the Uncorrectable error buffer is not set then simply return + // + if(PUncorrectableError == NULL) + return; + + PUncorrectableError->Signature = ERROR_FRAME_SIGNATURE; + + PUncorrectableError->FrameType = UncorrectableFrame; + + // + // ERROR_FRAME_VERSION is define in errframe.h and will + // change as and when there is a change in the errframe.h. + // This Version number helps the service, that reads this + // information from the dumpfile, to check if it knows about + // this frmae version type to decode. If it doesn't know, it + // will dump the entire frame to the EventLog with a message + // "Error Frame Version Mismatch". + // + + PUncorrectableError->VersionNumber = ERROR_FRAME_VERSION; + + // + // The sequence number will always be 1 for Uncorrectable errors. + // + + PUncorrectableError->SequenceNumber = 1; + + // + // The PerformanceCounterValue field is not used for Uncorrectable + // errors. + // + + PUncorrectableError->PerformanceCounterValue = 0; + + // + // We will fill in the UncorrectableFrame.SystemInfo here. + // + + HalpGetSystemInfo(&PUncorrectableError->UncorrectableFrame.System); + + PUncorrectableError->UncorrectableFrame.Flags.SystemInformationValid = 1; + + return; +} + +// +//jnfix - this variable is needed because the clock interrupt handler +// - in intsup.s was made to be familiar with ev4prof.c, unfortunate +// - since we don't use ev4prof.c, so for now this is a hack, later +// - we will either fix intsup.s or create a new intsup.s that does +// - not have this hack +// + +ULONG HalpNumberOfTicksReload; + diff --git a/private/ntos/nthals/haltimbr/alpha/ebintsup.c b/private/ntos/nthals/haltimbr/alpha/ebintsup.c new file mode 100644 index 000000000..3beb9df13 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ebintsup.c @@ -0,0 +1,619 @@ +/*++ + +Copyright (c) 1990 Microsoft Corporation +Copyright (c) 1992, 1993 Digital Equipment Corporation + +Module Name: + + ebintsup.c + +Abstract: + + The module provides the interrupt support for EB164 systems. + +Author: + + Eric Rehm (DEC) 29-December-1993 + +Revision History: + + Chao Chen (DEC) 06-Sept-1994 + Adapted from Avanti module for EB164. + +--*/ + + +#include "halp.h" +#include "eisa.h" +#include "ebsgdma.h" +#include "eb164.h" +#include "pcrtc.h" +#include "pintolin.h" + + +// +// Declare the interrupt masks. +// + +UCHAR IntMask0, IntMask1, IntMask2; + +// +// Define the context structure for use by interrupt service routines. +// + +typedef BOOLEAN (*PSECOND_LEVEL_DISPATCH)( + PKINTERRUPT InterruptObject, + PVOID ServiceContext, + PKTRAP_FRAME TrapFrame + ); + +// +// The following is the interrupt object used for DMA controller interrupts. +// DMA controller interrupts occur when a memory parity error occurs or a +// programming error occurs to the DMA controller. +// + +KINTERRUPT HalpEisaNmiInterrupt; + +// +// The following function initializes NMI handling. +// + +VOID +HalpInitializeNMI( + VOID + ); + +// +// The following function is called when an ISA NMI occurs. +// + +BOOLEAN +HalHandleNMI( + IN PKINTERRUPT Interrupt, + IN PVOID ServiceContext + ); + +// +// The following functions handle the PCI interrupts. +// + +VOID +HalpInitializePciInterrupts ( + VOID + ); + +VOID +HalpDisablePciInterrupt( + IN ULONG Vector + ); + +VOID +HalpEnablePciInterrupt( + IN ULONG Vector, + IN KINTERRUPT_MODE InterruptMode + ); + +BOOLEAN +HalpPciDispatch( + IN PKINTERRUPT Interrupt, + IN PVOID ServiceContext, + IN PKTRAP_FRAME TrapFrame + ); + + +BOOLEAN +HalpInitializeEB164Interrupts ( + VOID + ) +/*++ + +Routine Description: + + This routine initializes the structures necessary for ISA & PCI operations + and connects the intermediate interrupt dispatchers. It also initializes + the ISA interrupt controller. + +Arguments: + + None. + +Return Value: + + If the second level interrupt dispatchers are connected, then a value of + TRUE is returned. Otherwise, a value of FALSE is returned. + +--*/ + +{ + KIRQL oldIrql; + + // + // Initialize the ISA NMI interrupt. + // + + HalpInitializeNMI(); + + (PVOID) HalpPCIPinToLineTable = (PVOID) EB164PCIPinToLineTable; + + // + // Intitialize interrupt controller + // + + KeRaiseIrql(DEVICE_HIGH_LEVEL, &oldIrql); + + // + // Initialize the PCI interrupts. + // + + HalpInitializePciInterrupts(); + + // + // Initialize the SIO's PICs for ISA interrupts. + // + + HalpInitializeSioInterrupts(); + + // + // Restore the IRQL. + // + + KeLowerIrql(oldIrql); + + // + // Initialize the EISA DMA mode registers to a default value. + // Disable all of the DMA channels except channel 4 which is the + // cascade of channels 0-3. + // + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Dma1BasePort.AllMask, + 0x0F + ); + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Dma2BasePort.AllMask, + 0x0E + ); + + return(TRUE); +} + + +VOID +HalpInitializeNMI( + VOID + ) +/*++ + +Routine Description: + + This function is called to intialize ESC NMI interrupts. + +Arguments: + + None. + +Return Value: + + None. +--*/ +{ + UCHAR DataByte; + + // + // Initialize the ESC NMI interrupt. + // + + KeInitializeInterrupt( &HalpEisaNmiInterrupt, + HalHandleNMI, + NULL, + NULL, + EISA_NMI_VECTOR, + EISA_NMI_LEVEL, + EISA_NMI_LEVEL, + LevelSensitive, + FALSE, + 0, + FALSE + ); + + // + // Don't fail if the interrupt cannot be connected. + // + + KeConnectInterrupt( &HalpEisaNmiInterrupt ); + + // + // Clear the Eisa NMI disable bit. This bit is the high order of the + // NMI enable register. + // + + DataByte = 0; + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable, + DataByte + ); + +} + + +BOOLEAN +HalHandleNMI( + IN PKINTERRUPT Interrupt, + IN PVOID ServiceContext + ) +/*++ + +Routine Description: + + This function is called when an EISA NMI occurs. It prints the + appropriate status information and bugchecks. + +Arguments: + + Interrupt - Supplies a pointer to the interrupt object + + ServiceContext - Bug number to call bugcheck with. + +Return Value: + + Returns TRUE. + +--*/ +{ + UCHAR StatusByte; + + StatusByte = + READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiStatus); + + if (StatusByte & 0x80) { + HalDisplayString ("NMI: Parity Check / Parity Error\n"); + } + + if (StatusByte & 0x40) { + HalDisplayString ("NMI: Channel Check / IOCHK\n"); + } + + KeBugCheck(NMI_HARDWARE_FAILURE); + return(TRUE); +} + + +VOID +HalpAcknowledgeClockInterrupt( + VOID + ) +/*++ + +Routine Description: + + Acknowledge the clock interrupt from the interval timer. The interval + timer for EB164 comes from a Dallas real-time clock. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + + // + // Acknowledge the clock interrupt by reading the control register C of + // the Real Time Clock. + // + + HalpReadClockRegister( RTC_CONTROL_REGISTERC ); + + return; +} + + + +VOID +HalpInitializePciInterrupts ( + VOID + ) + +/*++ + +Routine Description: + + This routine initializes the EB164 PCI interrupts. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + // + // Clear all interrupt masks. + // Enable the SIO interrupt in the mask. + // + + IntMask0 = 0x10; + IntMask1 = 0x00; + IntMask2 = 0x00; + + // + // Disable interrupts except for SIO. + // + + WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK0_QVA, ~IntMask0); + WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK1_QVA, ~IntMask1); + WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK2_QVA, ~IntMask2); + +} + + +VOID +HalpDisablePciInterrupt( + IN ULONG Vector + ) + +/*++ + +Routine Description: + + This function disables the PCI interrupt specified by Vector. + +Arguments: + + Vector - Supplies the vector of the PCI interrupt that is disabled. + +Return Value: + + None. + +--*/ + +{ + // + // Calculate the PCI interrupt vector, relative to 0. + // + + Vector -= PCI_VECTORS; + + // + // Get the current state of the interrupt mask register, then set + // the bit corresponding to the adjusted value of Vector to zero, + // to disable that PCI interrupt. + // + + if (Vector >= 0 && Vector <= 7) { + + IntMask0 &= (UCHAR)~(1 << Vector); + WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK0_QVA, ~IntMask0); + + } else if (Vector >= 8 && Vector <= 0xf) { + + IntMask1 &= (UCHAR)~(1 << (Vector - 8)); + WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK1_QVA, ~IntMask1); + + } else if (Vector >= 0x10 && Vector <=0x17) { + + IntMask2 &= (UCHAR)~(1 << (Vector - 16)); + WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK2_QVA, ~IntMask2); + + } else { + +#if HALDBG + DbgPrint("HalpDisablePciInterrupt: bad vector!\n"); +#endif + + } +} + + +VOID +HalpEnablePciInterrupt( + IN ULONG Vector, + IN KINTERRUPT_MODE InterruptMode + ) + +/*++ + +Routine Description: + + This function enables the PCI interrupt specified by Vector. +Arguments: + + Vector - Supplies the vector of the PCI interrupt that is enabled. + + InterruptMode - Supplies the mode of the interrupt; LevelSensitive or + Latched (ignored for EB164 PCI interrupts; they're always levels). + +Return Value: + + None. + +--*/ + +{ + // + // Calculate the PCI interrupt vector, relative to 0. + // + + Vector -= PCI_VECTORS; + + // + // Get the current state of the interrupt mask register, then set + // the bit corresponding to the adjusted value of Vector to one, + // to ensable that PCI interrupt. + // + + if (Vector >= 0 && Vector <= 7) { + + IntMask0 |= (UCHAR) (1 << Vector); + WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK0_QVA, ~IntMask0); + + } else if (Vector >= 8 && Vector <= 0xf) { + + IntMask1 |= (UCHAR) (1 << (Vector - 8)); + WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK1_QVA, ~IntMask1); + + } else if (Vector >= 0x10 && Vector <= 0x17) { + + IntMask2 |= (UCHAR) (1 << (Vector - 16)); + WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK2_QVA, ~IntMask2); + + } else { + +#if HALDBG + DbgPrint("HalpEnablePciInterrupt: bad vector!\n"); +#endif + + } +} + + +BOOLEAN +HalpDeviceDispatch( + IN PKINTERRUPT Interrupt, + IN PVOID ServiceContext, + IN PKTRAP_FRAME TrapFrame + ) +/*++ + +Routine Description: + + This routine is entered as the result of an interrupt being generated + via the vector that is connected to an interrupt object associated with + the PCI device interrupts. Its function is to call the second-level + interrupt dispatch routine. + +Arguments: + + Interrupt - Supplies a pointer to the interrupt object. + + ServiceContext - Supplies a pointer to the PCI interrupt register. + + TrapFrame - Supplies a pointer to the trap frame for this interrupt. + +Return Value: + + Returns the value returned from the second level routine. + +--*/ +{ + PULONG DispatchCode; + ULONG IdtIndex; + ULONG IntNumber; + PKINTERRUPT InterruptObject; + UCHAR PCIVector; + + // + // Read in the 1st interrupt register. + // + + PCIVector = READ_PORT_UCHAR((PUCHAR)INTERRUPT_MASK0_QVA) & IntMask0; + + // + // Did ISA interrupt occur? + // + + if (PCIVector & 0x10) { + + // + // ISA interrupt. Call HalpEB164SioDispatch. + // + + return (HalpEB164SioDispatch( Interrupt, NULL, TrapFrame ) ); + + } + + // + // Which PCI interrupt occurred? + // + + IdtIndex = PCI_MAX_INTERRUPT + 1; + + if (PCIVector) { + + for (IntNumber = 0; IntNumber < 8; IntNumber++) { + + if (PCIVector & 0x01) { + IdtIndex = IntNumber; + break; + } else { + PCIVector = PCIVector >> 1; + } + + } + + } else { + + PCIVector = READ_PORT_UCHAR((PUCHAR)INTERRUPT_MASK1_QVA) & IntMask1; + + if (PCIVector) { + + for (IntNumber = 0; IntNumber < 8; IntNumber++) { + + if (PCIVector & 0x01) { + IdtIndex = IntNumber + 8; + break; + } else { + PCIVector = PCIVector >> 1; + } + + } + + } else { + + PCIVector = READ_PORT_UCHAR((PUCHAR)INTERRUPT_MASK2_QVA) & IntMask2; + + for (IntNumber = 0; IntNumber < 8; IntNumber++) { + + if (PCIVector & 0x01) { + IdtIndex = IntNumber + 16; + break; + } else { + PCIVector = PCIVector >> 1; + } + + } + + } + + } + + // + // If no PCI interrupt is enabled and asserted then this is a passive + // release. + // + + if( IdtIndex > PCI_MAX_INTERRUPT ){ + +#if HALDBG + + DbgPrint( "HalpDeviceDispatch: PCI Passive Release.\n" ); + +#endif //HALDBG + + return FALSE; + + } + + IdtIndex += PCI_VECTORS; + DispatchCode = (PULONG)PCR->InterruptRoutine[IdtIndex]; + InterruptObject = CONTAINING_RECORD( DispatchCode, + KINTERRUPT, + DispatchCode ); + + return( ((PSECOND_LEVEL_DISPATCH)InterruptObject->DispatchAddress)( + InterruptObject, + InterruptObject->ServiceContext, + TrapFrame) ); + +} + diff --git a/private/ntos/nthals/haltimbr/alpha/ebsgdma.c b/private/ntos/nthals/haltimbr/alpha/ebsgdma.c new file mode 100644 index 000000000..80a9fdfd3 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ebsgdma.c @@ -0,0 +1,6 @@ +// +// This file includes the source file from the Alcor HAL directory. +// + +#include "..\halalcor\alpha\ebsgdma.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/ebsysint.c b/private/ntos/nthals/haltimbr/alpha/ebsysint.c new file mode 100644 index 000000000..a597a13b9 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ebsysint.c @@ -0,0 +1,425 @@ +/*++ + +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + ebsysint.c + +Abstract: + + This module implements the HAL enable/disable system interrupt, and + request interprocessor interrupt routines for the EB164 system. + +Author: + + Joe Notarangelo 20-Jul-1994 + +Environment: + + Kernel mode + +Revision History: + +--*/ + +#include "halp.h" +#include "eb164.h" + + +// +// Function prototype +// + +VOID +HalpDisablePciInterrupt( + IN ULONG Vector + ); + +VOID +HalpEnablePciInterrupt( + IN ULONG Vector, + IN KINTERRUPT_MODE InterruptMode + ); + + +VOID +HalDisableSystemInterrupt ( + IN ULONG Vector, + IN KIRQL Irql + ) + +/*++ + +Routine Description: + + This routine disables the specified system interrupt. + +Arguments: + + Vector - Supplies the vector of the system interrupt that is disabled. + + Irql - Supplies the IRQL of the interrupting source. + +Return Value: + + None. + +--*/ + +{ + + KIRQL OldIrql; + + // + // Raise IRQL to the highest level. + // + + KeRaiseIrql(HIGH_LEVEL, &OldIrql); + + // + // If the vector number is within the range of the ISA interrupts, then + // disable the ISA interrrupt. + // + + if (Vector >= ISA_VECTORS && + Vector < MAXIMUM_ISA_VECTOR && + Irql == DEVICE_HIGH_LEVEL) { + HalpDisableSioInterrupt(Vector); + } + + // + // If the vector number is within the range of the PCI interrupts, then + // disable the PCI interrrupt. + // + + if (Vector >= PCI_VECTORS && + Vector < MAXIMUM_PCI_VECTOR && + Irql == DEVICE_HIGH_LEVEL) { + HalpDisablePciInterrupt(Vector); + } + + // + // If the vector is a performance counter vector we will ignore + // the enable - the performance counters are enabled directly by + // the wrperfmon callpal. Wrperfmon must be controlled directly + // by the driver. + // + + switch (Vector) { + + case PC0_VECTOR: + case PC1_VECTOR: + case PC2_VECTOR: + + break; + + } //end switch Vector + + // + // Lower IRQL to the previous level. + // + + KeLowerIrql(OldIrql); + return; +} + + +BOOLEAN +HalEnableSystemInterrupt ( + IN ULONG Vector, + IN KIRQL Irql, + IN KINTERRUPT_MODE InterruptMode + ) + +/*++ + +Routine Description: + + This routine enables the specified system interrupt. + +Arguments: + + Vector - Supplies the vector of the system interrupt that is enabled. + + Irql - Supplies the IRQL of the interrupting source. + + InterruptMode - Supplies the mode of the interrupt; LevelSensitive or + Latched. + +Return Value: + + TRUE if the system interrupt was enabled + +--*/ + +{ + BOOLEAN Enabled = FALSE; + KIRQL OldIrql; + + // + // Raise IRQL to the highest level. + // + + KeRaiseIrql(HIGH_LEVEL, &OldIrql); + + // + // If the vector number is within the range of the ISA interrupts, then + // enable the ISA interrrupt and set the Level/Edge register. + // + + if (Vector >= ISA_VECTORS && + Vector < MAXIMUM_ISA_VECTOR && + Irql == DEVICE_HIGH_LEVEL) { + HalpEnableSioInterrupt( Vector, InterruptMode ); + Enabled = TRUE; + } + + // + // If the vector number is within the range of the PCI interrupts, then + // enable the PCI interrrupt. + // + + if (Vector >= PCI_VECTORS && + Vector < MAXIMUM_PCI_VECTOR && + Irql == DEVICE_HIGH_LEVEL) { + HalpEnablePciInterrupt( Vector, InterruptMode ); + Enabled = TRUE; + } + + // + // If the vector is a performance counter vector we will ignore + // the enable - the performance counters are enabled directly by + // the wrperfmon callpal. Wrperfmon must be controlled directly + // by the driver. + // + + switch (Vector) { + + case PC0_VECTOR: + case PC1_VECTOR: + case PC2_VECTOR: + + Enabled = TRUE; + break; + + } //end switch Vector + + // + // Lower IRQL to the previous level. + // + + KeLowerIrql(OldIrql); + return Enabled; + +} + + +ULONG +HalpGetSystemInterruptVector( + IN PBUS_HANDLER BusHandler, + IN PBUS_HANDLER RootHandler, + IN ULONG BusInterruptLevel, + IN ULONG BusInterruptVector, + OUT PKIRQL Irql, + OUT PKAFFINITY Affinity + ) + +/*++ + +Routine Description: + + This function returns the system interrupt vector and IRQL level + corresponding to the specified bus interrupt level and/or vector. The + system interrupt vector and IRQL are suitable for use in a subsequent + call to KeInitializeInterrupt. + + We only use InterfaceType and BusInterruptLevel. BusInterruptVector + for EISA and ISA are the same as the InterruptLevel, so ignore. + +Arguments: + + BusHandler - Registered BUSHANDLER for the target configuration space + + RootHandler - Registered BUSHANDLER for the orginating HalGetBusData + request. + + BusInterruptLevel - Supplies the bus-specific interrupt level. + + BusInterruptVector - Supplies the bus-specific interrupt vector. + + Irql - Returns the system request priority. + + Affinity - Returns the affinity for the requested vector + +Return Value: + + Returns the system interrupt vector corresponding to the specified device. + +--*/ + +{ + INTERFACE_TYPE InterfaceType = BusHandler->InterfaceType; + ULONG BusNumber = BusHandler->BusNumber; + + ULONG Vector; + + *Affinity = 1; + + switch (InterfaceType) { + + case ProcessorInternal: + + // + // Handle the internal defined for the processor itself + // and used to control the performance counters in the 21064. + // + + if( (Vector = HalpGet21164PerformanceVector( BusInterruptLevel, + Irql)) != 0 ){ + + // + // Performance counter was successfully recognized. + // + + *Affinity = HalpActiveProcessors; + return Vector; + + } else { + + // + // Unrecognized processor interrupt. + // + + *Irql = 0; + *Affinity = 0; + return 0; + + } //end if Vector + + break; + + case Internal: + + // + // This bus type is for things connected to the processor + // in some way other than a standard bus, e.g., (E)ISA, PCI. + // Since devices on this "bus," apart from the special case of + // the processor, above, interrupt via the 82c59 cascade in the + // ESC, we assign vectors based on (E)ISA_VECTORS - see below. + // Firmware must agree on these vectors, as it puts them in + // the CDS. + // + + *Irql = DEVICE_HIGH_LEVEL; + + return(BusInterruptLevel + ISA_VECTORS); + break; + + case Isa: + + // + // Assumes all ISA devices coming in on same processor pin + // + + *Irql = DEVICE_HIGH_LEVEL; + + // + // The vector is equal to the specified bus level plus ISA_VECTORS. + // N.B.: this encoding technique uses the notion of defining a + // base interrupt vector in the space defined by the constant, + // ISA_VECTORS, which may or may not differ from EISA_VECTORS or + // PCI_VECTORS. + // + + return(BusInterruptLevel + ISA_VECTORS); + break; + + + case Eisa: + + // + // Assumes all EISA devices coming in on same processor pin + // + + *Irql = DEVICE_HIGH_LEVEL; + + // + // The vector is equal to the specified bus level plus the EISA_VECTOR. + // + + return(BusInterruptLevel + EISA_VECTORS); + break; + + case PCIBus: + + // + // Assumes all PCI devices coming in on same processor pin + // + + *Irql = DEVICE_HIGH_LEVEL; + + // + // The vector is equal to the specified bus level plus the PCI_VECTOR + // + // N.B. The BusInterruptLevel is one-based while the vectors + // themselves are zero-based. The BusInterruptLevel must be + // one-based because if scsiport sees a zero vector then it + // will believe the interrupt is not connected. So in PCI + // configuration we have made the interrupt vector correspond + // to the slot and interrupt pin. + // + + return( (BusInterruptLevel - 1) + PCI_VECTORS); + + break; + + default: + + // + // Not an interface supported on EB164 systems. + // + +#if defined(HALDBG) + + DbgPrint("EBSYSINT: InterfaceType (%x) not supported on EB164\n", + InterfaceType); + +#endif + + *Irql = 0; + *Affinity = 0; + return(0); + break; + + } //end switch(InterfaceType) + +} + + +VOID +HalRequestIpi ( + IN ULONG Mask + ) +/*++ + +Routine Description: + + This routine requests an interprocessor interrupt on a set of processors. + This routine performs no function on an EB164 because it is a + uni-processor system. + +Arguments: + + Mask - Supplies the set of processors that are sent an interprocessor + interrupt. + +Return Value: + + None. + +--*/ + +{ + return; +} diff --git a/private/ntos/nthals/haltimbr/alpha/eisasup.c b/private/ntos/nthals/haltimbr/alpha/eisasup.c new file mode 100644 index 000000000..6cec04bf6 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/eisasup.c @@ -0,0 +1,6 @@ +// +// This file includes the source file from the Alcor HAL directory. +// + +#include "..\halalcor\alpha\eisasup.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/environ.c b/private/ntos/nthals/haltimbr/alpha/environ.c new file mode 100644 index 000000000..75015a0a0 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/environ.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\environ.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/ev5cache.c b/private/ntos/nthals/haltimbr/alpha/ev5cache.c new file mode 100644 index 000000000..cd83f7451 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ev5cache.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev5cache.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/ev5int.c b/private/ntos/nthals/haltimbr/alpha/ev5int.c new file mode 100644 index 000000000..23727330f --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ev5int.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev5int.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/ev5ints.s b/private/ntos/nthals/haltimbr/alpha/ev5ints.s new file mode 100644 index 000000000..66852f382 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ev5ints.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev5ints.s" + diff --git a/private/ntos/nthals/haltimbr/alpha/ev5mchk.c b/private/ntos/nthals/haltimbr/alpha/ev5mchk.c new file mode 100644 index 000000000..0bedd3dfc --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ev5mchk.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev5mchk.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/ev5mem.s b/private/ntos/nthals/haltimbr/alpha/ev5mem.s new file mode 100644 index 000000000..dcad6563c --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ev5mem.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev5mem.s" + diff --git a/private/ntos/nthals/haltimbr/alpha/ev5prof.c b/private/ntos/nthals/haltimbr/alpha/ev5prof.c new file mode 100644 index 000000000..839438fd9 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ev5prof.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ev5prof.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/flash8k.c b/private/ntos/nthals/haltimbr/alpha/flash8k.c new file mode 100644 index 000000000..4d59fc2f7 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/flash8k.c @@ -0,0 +1 @@ +#include "../halalpha/flash8k.c" diff --git a/private/ntos/nthals/haltimbr/alpha/flashdrv.c b/private/ntos/nthals/haltimbr/alpha/flashdrv.c new file mode 100644 index 000000000..ad0994d4d --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/flashdrv.c @@ -0,0 +1,3 @@ +#include "../halalpha/flashdrv.c" + + diff --git a/private/ntos/nthals/haltimbr/alpha/fwreturn.c b/private/ntos/nthals/haltimbr/alpha/fwreturn.c new file mode 100644 index 000000000..65ae88cb8 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/fwreturn.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\fwreturn.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/haldebug.c b/private/ntos/nthals/haltimbr/alpha/haldebug.c new file mode 100644 index 000000000..ce91863ec --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/haldebug.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\haldebug.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/halpal.s b/private/ntos/nthals/haltimbr/alpha/halpal.s new file mode 100644 index 000000000..fc89f8370 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/halpal.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\halpal.s" + diff --git a/private/ntos/nthals/haltimbr/alpha/haltsup.s b/private/ntos/nthals/haltimbr/alpha/haltsup.s new file mode 100644 index 000000000..b8a697144 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/haltsup.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\haltsup.s" + diff --git a/private/ntos/nthals/haltimbr/alpha/idle.s b/private/ntos/nthals/haltimbr/alpha/idle.s new file mode 100644 index 000000000..f517bab2f --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/idle.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\idle.s" + diff --git a/private/ntos/nthals/haltimbr/alpha/info.c b/private/ntos/nthals/haltimbr/alpha/info.c new file mode 100644 index 000000000..22aef63a3 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/info.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\info.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/inithal.c b/private/ntos/nthals/haltimbr/alpha/inithal.c new file mode 100644 index 000000000..a79b38372 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/inithal.c @@ -0,0 +1,6 @@ +// +// This file includes the source file from the Alcor HAL directory. +// + +#include "..\halalcor\alpha\inithal.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/intsup.s b/private/ntos/nthals/haltimbr/alpha/intsup.s new file mode 100644 index 000000000..a7d9f8f4f --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/intsup.s @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// +#include "pcrtc.h" +#include "..\halalpha\intsup.s" + diff --git a/private/ntos/nthals/haltimbr/alpha/ioproc.c b/private/ntos/nthals/haltimbr/alpha/ioproc.c new file mode 100644 index 000000000..cc65eacde --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/ioproc.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\ioproc.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/iousage.c b/private/ntos/nthals/haltimbr/alpha/iousage.c new file mode 100644 index 000000000..83cbfb656 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/iousage.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\iousage.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/machdep.h b/private/ntos/nthals/haltimbr/alpha/machdep.h new file mode 100644 index 000000000..8dec64c29 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/machdep.h @@ -0,0 +1,42 @@ +/*++ + +Copyright (c) 1993 Digital Equipment Corporation + +Module Name: + + machdep.h + +Abstract: + + This file includes the platform-dependent include files used to + build the HAL. + +Author: + + Joe Notarangelo 01-Dec-1993 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +#ifndef _MACHDEP_ +#define _MACHDEP_ + +// +// Include EB164 platform-specific definitions. +// + +#include "eb164.h" + +// +// Include scatter/gather definitions. +// + +#include "ebsgdma.h" + +#endif //_MACHDEP_ diff --git a/private/ntos/nthals/haltimbr/alpha/memory.c b/private/ntos/nthals/haltimbr/alpha/memory.c new file mode 100644 index 000000000..76b1eb7df --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/memory.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\memory.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/nvenv.c b/private/ntos/nthals/haltimbr/alpha/nvenv.c new file mode 100644 index 000000000..ba5a5c8f7 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/nvenv.c @@ -0,0 +1 @@ +#include "..\halalpha\nvenv.c" diff --git a/private/ntos/nthals/haltimbr/alpha/nvram.c b/private/ntos/nthals/haltimbr/alpha/nvram.c new file mode 100644 index 000000000..879c41c68 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/nvram.c @@ -0,0 +1 @@ +#include "..\halalpha\nvram.c" diff --git a/private/ntos/nthals/haltimbr/alpha/pcibus.c b/private/ntos/nthals/haltimbr/alpha/pcibus.c new file mode 100644 index 000000000..a32e6bfcd --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/pcibus.c @@ -0,0 +1,6 @@ +// +// This file includes the source file from the Alcor HAL directory. +// + +#include "..\halalcor\alpha\pcibus.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/pcisio.c b/private/ntos/nthals/haltimbr/alpha/pcisio.c new file mode 100644 index 000000000..43ff9900a --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/pcisio.c @@ -0,0 +1,493 @@ +/*++ + +Copyright (c) 1990 Microsoft Corporation +Copyright (c) 1992, 1993, 1994 Digital Equipment Corporation + +Module Name: + + pic8259.c + +Abstract: + + The module provides the interrupt support for the PCI SIO + programmable interrupt controller. + + +Author: + + Eric Rehm (DEC) 4-Feburary-1994 + +Revision History: + + +--*/ + +#include "halp.h" +#include "eisa.h" + +// +// Import save area for SIO interrupt mask registers. +// + +UCHAR HalpSioInterrupt1Mask; +UCHAR HalpSioInterrupt2Mask; +UCHAR HalpSioInterrupt1Level; +UCHAR HalpSioInterrupt2Level; + +// +// Define the context structure for use by interrupt service routines. +// + +typedef BOOLEAN (*PSECOND_LEVEL_DISPATCH)( + PKINTERRUPT InterruptObject + ); + + +VOID +HalpInitializeSioInterrupts ( + VOID + ) + +/*++ + +Routine Description: + + This routine initializes the standard dual 8259 programmable interrupt + controller. + +Arguments: + + None. + +Return Value: + + None. + +--*/ +{ + UCHAR DataByte; + + // + // Initialize the SIO interrupt controller. There are two cascaded + // interrupt controllers, each of which must initialized with 4 initialize + // control words. + // + + DataByte = 0; + ((PINITIALIZATION_COMMAND_1) &DataByte)->Icw4Needed = 1; + ((PINITIALIZATION_COMMAND_1) &DataByte)->InitializationFlag = 1; + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0, + DataByte + ); + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0, + DataByte + ); + + // + // The second intitialization control word sets the iterrupt vector to + // 0-15. + // + + DataByte = 0; + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1, + DataByte + ); + + DataByte = 0x08; + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1, + DataByte + ); + + // + // The thrid initialization control word set the controls for slave mode. + // The master ICW3 uses bit position and the slave ICW3 uses a numberic. + // + + DataByte = 1 << SLAVE_IRQL_LEVEL; + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1, + DataByte + ); + + DataByte = SLAVE_IRQL_LEVEL; + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1, + DataByte + ); + + // + // The fourth initialization control word is used to specify normal + // end-of-interrupt mode and not special-fully-nested mode. + // + + DataByte = 0; + ((PINITIALIZATION_COMMAND_4) &DataByte)->I80x86Mode = 1; + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1, + DataByte + ); + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1, + DataByte + ); + + + // + // Disable all of the interrupts except the slave. + // + + HalpSioInterrupt1Mask = (UCHAR)(~(1 << SLAVE_IRQL_LEVEL)); + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1, + HalpSioInterrupt1Mask + ); + + HalpSioInterrupt2Mask = 0xFF; + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1, + HalpSioInterrupt2Mask + ); + + + // + // Initialize the edge/level register masks to 0 which is the default + // edge sensitive value. + // + + HalpSioInterrupt1Level = 0; + HalpSioInterrupt2Level = 0; + + return; + +} + +VOID +HalpDisableSioInterrupt( + IN ULONG Vector + ) + +/*++ + +Routine Description: + + This function Disables the SIO bus specified SIO bus interrupt. + +Arguments: + + Vector - Supplies the vector of the ESIA interrupt that is Disabled. + +Return Value: + + None. + +--*/ + +{ + + // + // Calculate the SIO interrupt vector. + // + + Vector -= ISA_VECTORS; + + // + // Determine if this vector is for interrupt controller 1 or 2. + // + + if (Vector & 0x08) { + + // + // The interrupt is in controller 2. + // + + Vector &= 0x7; + + HalpSioInterrupt2Mask |= (UCHAR) 1 << Vector; + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1, + HalpSioInterrupt2Mask + ); + + } else { + + // + // The interrupt is in controller 1. + // + + Vector &= 0x7; + + // + // never disable IRQL2, it is the slave interrupt + // + + if (Vector != SLAVE_IRQL_LEVEL) { + HalpSioInterrupt1Mask |= (ULONG) 1 << Vector; + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1, + HalpSioInterrupt1Mask + ); + } + + } + +} + +VOID +HalpEnableSioInterrupt( + IN ULONG Vector, + IN KINTERRUPT_MODE InterruptMode + ) + +/*++ + +Routine Description: + + This function enables the SIO bus specified SIO bus interrupt. +Arguments: + + Vector - Supplies the vector of the SIO interrupt that is enabled. + + InterruptMode - Supplies the mode of the interrupt; LevelSensitive or + Latched. + +Return Value: + + None. + +--*/ + +{ + + // + // Calculate the SIO interrupt vector. + // + + Vector -= ISA_VECTORS; + + // + // Determine if this vector is for interrupt controller 1 or 2. + // + + if (Vector & 0x08) { + + // + // The interrupt is in controller 2. + // + + Vector &= 0x7; + + HalpSioInterrupt2Mask &= (UCHAR) ~(1 << Vector); + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1, + HalpSioInterrupt2Mask + ); + + // + // Set the level/edge control register. + // + + if (InterruptMode == LevelSensitive) { + + HalpSioInterrupt2Level |= (UCHAR) (1 << Vector); + + } else { + + HalpSioInterrupt2Level &= (UCHAR) ~(1 << Vector); + + } + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2EdgeLevel, + HalpSioInterrupt2Level + ); + + } else { + + // + // The interrupt is in controller 1. + // + + Vector &= 0x7; + + HalpSioInterrupt1Mask &= (UCHAR) ~(1 << Vector); + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1, + HalpSioInterrupt1Mask + ); + + // + // Set the level/edge control register. + // + + if (InterruptMode == LevelSensitive) { + + HalpSioInterrupt1Level |= (UCHAR) (1 << Vector); + + } else { + + HalpSioInterrupt1Level &= (UCHAR) ~(1 << Vector); + + } + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1EdgeLevel, + HalpSioInterrupt1Level + ); + } + +} + +BOOLEAN +HalpEB164SioDispatch( + PKINTERRUPT Interrupt, + PVOID ServiceContext, + PKTRAP_FRAME TrapFrame + ) +/*++ + +Routine Description: + + This routine is entered as the result of an interrupt being generated + via the vector that is directly connected to an interrupt object that + describes the SIO device interrupts. Its function is to call the second + level interrupt dispatch routine and acknowledge the interrupt at the SIO + controller. + +Arguments: + + Interrupt - Supplies a pointer to the interrupt object. + + ServiceContext - not used. + + TrapFrame - Supplies a pointer to the interrupt trap frame. + +Return Value: + + Returns the value returned from the second level routine. + +--*/ +{ + UCHAR ISAVector; + PKPRCB Prcb; + BOOLEAN returnValue; + USHORT PCRInOffset; + UCHAR Int1Isr; + UCHAR Int2Isr; + PULONG DispatchCode; + PKINTERRUPT InterruptObject; + + // + // Acknowledge the Interrupt controller and receive the returned + // interrupt vector. + // + + //ISAVector = READ_PORT_UCHAR(HalpEisaIntAckBase); + ISAVector = (UCHAR)INTERRUPT_ACKNOWLEDGE(ServiceContext); + + + if ((ISAVector & 0x07) == 0x07) { + + // + // Check for a passive release by looking at the inservice register. + // If there is a real IRQL7 interrupt, just go along normally. If there + // is not, then it is a passive release. So just dismiss it. + // + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0, + 0x0B + ); + + Int1Isr = READ_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0); + + // + // do second controller + // + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0, + 0x0B + ); + + Int2Isr = READ_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0); + + + if (!(Int2Isr & 0x80) && !(Int1Isr & 0x80)) { + + // + // Clear the master controller to clear situation + // + + if (!(Int2Isr & 0x80)) { + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0, + NONSPECIFIC_END_OF_INTERRUPT + ); + + } + + return FALSE; // ecrfix - now returns a value + + } + + + } + + // + // Dispatch to the secondary interrupt service routine. + // + + PCRInOffset = ISAVector + ISA_VECTORS; + DispatchCode = (PULONG)PCR->InterruptRoutine[PCRInOffset]; + InterruptObject = CONTAINING_RECORD(DispatchCode, + KINTERRUPT, + DispatchCode); + + returnValue = ((PEB164_SECOND_LEVEL_DISPATCH)InterruptObject->DispatchAddress)( + InterruptObject, + InterruptObject->ServiceContext, + TrapFrame ); + + // + // Dismiss the interrupt in the SIO interrupt controllers. + // + + // + // If this is a cascaded interrupt then the interrupt must be dismissed in + // both controlles. + // + + if (ISAVector & 0x08) { + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0, + NONSPECIFIC_END_OF_INTERRUPT + ); + + } + + WRITE_PORT_UCHAR( + &((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0, + NONSPECIFIC_END_OF_INTERRUPT + ); + + return(returnValue); +} + + diff --git a/private/ntos/nthals/haltimbr/alpha/pcisup.c b/private/ntos/nthals/haltimbr/alpha/pcisup.c new file mode 100644 index 000000000..c4432fd4b --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/pcisup.c @@ -0,0 +1,6 @@ +// +// This file includes the source file from the Alcor HAL directory. +// + +#include "..\halalcor\alpha\pcisup.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/pcrtc.c b/private/ntos/nthals/haltimbr/alpha/pcrtc.c new file mode 100644 index 000000000..2e57b87d6 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/pcrtc.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcrtc.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/pcserial.c b/private/ntos/nthals/haltimbr/alpha/pcserial.c new file mode 100644 index 000000000..a2f159c48 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/pcserial.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcserial.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/pcspeakr.c b/private/ntos/nthals/haltimbr/alpha/pcspeakr.c new file mode 100644 index 000000000..807b6f324 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/pcspeakr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\pcspeakr.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/perfcntr.c b/private/ntos/nthals/haltimbr/alpha/perfcntr.c new file mode 100644 index 000000000..6c0a8f892 --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/perfcntr.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\perfcntr.c" + diff --git a/private/ntos/nthals/haltimbr/alpha/pintolin.h b/private/ntos/nthals/haltimbr/alpha/pintolin.h new file mode 100644 index 000000000..b60949dee --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/pintolin.h @@ -0,0 +1,174 @@ +/*++ + +Copyright (c) 1993 Microsoft Corporation +Copyright (c) 1994 Digital Equipment Corporation + +Module Name: + + pintolin.h + +Abstract: + + This file includes the platform-dependent Pin To Line Tables + +Author: + + Chao Chen 6-Sept 1994 + +Environment: + + Kernel mode + +Revision History: + + +--*/ + +// +// These tables represent the mapping from slot number and interrupt pin +// into a PCI Interrupt Vector. +// +// Formally, these mappings can be expressed as: +// +// PCIPinToLine: +// SlotNumber.DeviceNumber x InterruptPin -> InterruptLine +// +// LineToVector: +// InterruptLine -> InterruptVector +// +// VectorToIRRBit: +// InterruptVector -> InterruptRequestRegisterBit +// +// VectorToIMRBit: +// InterruptVector -> InterruptMaskRegisterBit +// +// SlotNumberToIDSEL: +// SlotNumber.DeviceNumber -> IDSEL +// +// subject to following invariants (predicates must always be true): +// +// Slot.DeviceNumber in {0,...,15} +// +// InterruptPin in {1, 2, 3, 4} +// +// InterruptRequestRegisterBit in {0,...,15} +// +// InterruptMaskRegisterBit in {0,...,15} +// +// PCIPinToLine(SlotNumber.DeviceNumber, InterruptPin) = +// PCIPinToLineTable[SlotNumber.DeviceNumber, InterruptPin] +// (Table-lookup function initialized below) +// +// LineToVector(InterruptLine) = PCI_VECTORS + InterruptLine +// +// VectorToIRRBit(InterruptVector) = InterruptVector - 1 +// +// VectorToIMRBit(InterruptVector) [see below] +// +// SlotNumberToIDSEL(SlotNumber.DeviceNumber) = (1 << (Slot.DeviceNumber+11)) +// +// where: +// +// SlotNumber.DeviceNumber: +// Alpha AXP Platforms receive interrupts on local PCI buses only, which +// are limited to 16 devices (PCI AD[11]-AD[26]). (We loose AD[27]-AD[31] +// since PCI Config space is a sparse space, requiring a five-bit shift.) +// +// InterruptPin: +// Each virtual slot has up to four interrupt pins INTA#, INTB#, INTC#, INTD#, +// as per the PCI Spec. V2.0, Section 2.2.6. (FYI, only multifunction devices +// use INTB#, INTC#, INTD#.) +// +// PCI configuration space indicates which interrupt pin a device will use +// in the InterruptPin register, which has the values: +// +// INTA# = 1, INTB#=2, INTC#=3, INTD# = 4 +// +// Note that there may be up to 8 functions/device on a PCI multifunction +// device plugged into the option slots, e.g., Slot #0. +// Each function has it's own PCI configuration space, addressed +// by the SlotNumber.FunctionNumber field, and will identify which +// interrput pin of the four it will use in it's own InterruptPin register. +// +// If the option is a PCI-PCI bridge, interrupts across the bridge will +// somehow be combined to appear on some combination of the four +// interrupt pins that the bridge plugs into. +// +// InterruptLine: +// This PCI Configuration register, unlike x86 PC's, is maintained by +// software and represents offset into PCI interrupt vectors. +// Whenever HalGetBusData or HalGetBusDataByOffset is called, +// HalpPCIPinToLine() computes the correct InterruptLine register value +// by using the HalpPCIPinToLineTable mapping. +// +// InterruptRequestRegisterBit: +// 0xff is used to mark an invalid IRR bit, hence an invalid request +// for a vector. Also, note that the 16 bits of the EB66 IRR must +// be access as two 8-bit reads. +// +// InterruptMaskRegisterBit: +// On EB66, the PinToLine table may also be find the to write the +// InterruptMaskRegister. Formally, we can express this invariant as +// +// VectorToIMRBit(InterrruptVector) = InterruptVector - 1 +// +// +// IDSEL: +// For accessing PCI configuration space on a local PCI bus (as opposed +// to over a PCI-PCI bridge), type 0 configuration cycles must be generated. +// In this case, the IDSEL pin of the device to be accessed is tied to one +// of the PCI Address lines AD[11] - AD[26]. (The function field in the +// PCI address is used should we be accessing a multifunction device.) +// Anyway, virtual slot 0 represents the device with IDSEL = AD[11], and +// so on. +// + +// +// Interrupt Vector Table Mapping for EB164. +// +// EB164 PCI interrupts are mapped to arbitrary interrupt numbers +// in the table below. The values are a 1-1 map of the bit numbers +// in the EB164 PCI interrupt register that are connected to PCI +// devices. N.B.: there are two other interrupts in this register, +// but they are not connected to I/O devices, so they're not +// represented in the table. +// +// Limit init table to 14 entries, which is the +// MAX_PCI_LOCAL_DEVICES_MIKASA. +// +// We won't ever try to set an InterruptLine register of a slot +// greater than Virtual slot 13 = PCI_AD[24]. +// + +ULONG *HalpPCIPinToLineTable; + +ULONG EB164PCIPinToLineTable[][4]= +{ +// Pin 1 Pin 2 Pin 3 Pin 4 +// ----- ----- ----- ----- + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 0 = PCI_AD[11] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 1 = PCI_AD[12] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 2 = PCI_AD[13] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 3 = PCI_AD[14] + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 4 = PCI_AD[15] + { 0x3, 0x8, 0xc, 0x10 }, // Virtual Slot 5 = PCI_AD[16] bridge + { 0x1, 0x6, 0xa, 0xe }, // Virtual Slot 6 = PCI_AD[17] Slot #0 + { 0x2, 0x7, 0xb, 0xf }, // Virtual Slot 7 = PCI_AD[18] Slot #1 + { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 8 = PCI_AD[19] SIO + { 0x4, 0x9, 0xd, 0x11 }, // Virtual Slot 9 = PCI_AD[20] Slot #2 + { 0x12, 0x13, 0x14, 0x15 } // Virtual Slot 10 = PCI_AD[21] Slot #3 +// { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 0 = PCI_AD[11] +// { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 1 = PCI_AD[12] +// { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 2 = PCI_AD[13] +// { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 3 = PCI_AD[14] +// { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 4 = PCI_AD[15] +// { 0x03, 0x08, 0x0c, 0x10 }, // Virtual Slot 5 = PCI_AD[16] PCI Slot 2 +// { 0x01, 0x06, 0x0a, 0x0e }, // Virtual Slot 6 = PCI_AD[17] PCI Slot 0 +// { 0x02, 0x07, 0x0b, 0x0f }, // Virtual Slot 7 = PCI_AD[18] PCI Slot 1 +// { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 8 = PCI_AD[19] PCI/ISA Bridge +// { 0x04, 0x09, 0x0d, 0x11 }, // Virtual Slot 9 = PCI_AD[20] PCI Slot 3 +// { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 10 = PCI_AD[21] +// { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 11 = PCI_AD[22] +// { 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 12 = PCI_AD[23] +}; + diff --git a/private/ntos/nthals/haltimbr/alpha/vga.c b/private/ntos/nthals/haltimbr/alpha/vga.c new file mode 100644 index 000000000..764c585af --- /dev/null +++ b/private/ntos/nthals/haltimbr/alpha/vga.c @@ -0,0 +1,7 @@ +// +// This file simply includes the source file from the common Alpha +// HAL directory. +// + +#include "..\halalpha\vga.c" + |