2 files changed, 15 insertions, 16 deletions

diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index d9db0daa0..a81bb8e91 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -51,22 +51,21 @@ typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
 // Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.
 // This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to
 // support LDR/STREXD.
-static const ARMword RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
+static const u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
 
 // Exclusive memory access
-static int exclusive_detect(ARMul_State* state, ARMword addr) {
+static int exclusive_detect(ARMul_State* state, u32 addr) {
     if(state->exclusive_tag == (addr & RESERVATION_GRANULE_MASK))
         return 0;
     else
         return -1;
 }
 
-static void add_exclusive_addr(ARMul_State* state, ARMword addr){
+static void add_exclusive_addr(ARMul_State* state, u32 addr){
     state->exclusive_tag = addr & RESERVATION_GRANULE_MASK;
-    return;
 }
 
-static void remove_exclusive(ARMul_State* state, ARMword addr){
+static void remove_exclusive(ARMul_State* state, u32 addr){
     state->exclusive_tag = 0xFFFFFFFF;
 }
 
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
index 13cc34be4..2860af376 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
@@ -14,7 +14,7 @@
 
 tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
     tdstate valid = t_uninitialized;
-    ARMword tinstr = instr;
+    u32 tinstr = instr;
 
     // The endian should be judge here
     if((addr & 0x3) != 0)
@@ -37,7 +37,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
 
     case 3: // ADD/SUB
         {
-            static const ARMword subset[4] = {
+            static const u32 subset[4] = {
                 0xE0900000,     // ADDS Rd,Rs,Rn
                 0xE0500000,     // SUBS Rd,Rs,Rn
                 0xE2900000,     // ADDS Rd,Rs,#imm3
@@ -56,7 +56,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
     case 6: // ADD
     case 7: // SUB
         {
-            static const ARMword subset[4] = {
+            static const u32 subset[4] = {
                 0xE3B00000,     // MOVS Rd,#imm8
                 0xE3500000,     // CMP  Rd,#imm8
                 0xE2900000,     // ADDS Rd,Rd,#imm8
@@ -85,7 +85,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
             };
 
             static const struct {
-                ARMword opcode;
+                u32 opcode;
                 otype type;
             } subset[16] = {
                 { 0xE0100000, t_norm },     // ANDS Rd,Rd,Rs
@@ -130,8 +130,8 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
                 break;
             }
         } else {
-            ARMword Rd = ((tinstr & 0x0007) >> 0);
-            ARMword Rs = ((tinstr & 0x0078) >> 3);
+            u32 Rd = ((tinstr & 0x0007) >> 0);
+            u32 Rs = ((tinstr & 0x0078) >> 3);
 
             if (tinstr & (1 << 7))
                 Rd += 8;
@@ -185,7 +185,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
     case 10:
     case 11:
         {
-            static const ARMword subset[8] = {
+            static const u32 subset[8] = {
                 0xE7800000, // STR   Rd,[Rb,Ro]
                 0xE18000B0, // STRH  Rd,[Rb,Ro]
                 0xE7C00000, // STRB  Rd,[Rb,Ro]
@@ -208,7 +208,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
     case 14: // STRB Rd,[Rb,#imm5]
     case 15: // LDRB Rd,[Rb,#imm5]
         {
-            static const ARMword subset[4] = {
+            static const u32 subset[4] = {
                 0xE5800000,     // STR  Rd,[Rb,#imm5]
                 0xE5900000,     // LDR  Rd,[Rb,#imm5]
                 0xE5C00000,     // STRB Rd,[Rb,#imm5]
@@ -275,7 +275,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
                 | BITS(tinstr, 0, 3)          // imm4 field;
                 | (BITS(tinstr, 4, 7) << 8);  // beginning 4 bits of imm12
         } else if ((tinstr & 0x0F00) == 0x0200) {
-            static const ARMword subset[4] = {
+            static const u32 subset[4] = {
                 0xE6BF0070, // SXTH
                 0xE6AF0070, // SXTB
                 0xE6FF0070, // UXTH
@@ -299,7 +299,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
                     | (BIT(tinstr, 4) << 18); // enable bit
             }
         } else if ((tinstr & 0x0F00) == 0x0a00) {
-            static const ARMword subset[3] = {
+            static const u32 subset[3] = {
                 0xE6BF0F30, // REV
                 0xE6BF0FB0, // REV16
                 0xE6FF0FB0, // REVSH
@@ -309,7 +309,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
                 | (BITS(tinstr, 0, 2) << 12)     // Rd
                 | BITS(tinstr, 3, 5);            // Rm
         } else {
-            static const ARMword subset[4] = {
+            static const u32 subset[4] = {
                 0xE92D0000, // STMDB sp!,{rlist}
                 0xE92D4000, // STMDB sp!,{rlist,lr}
                 0xE8BD0000, // LDMIA sp!,{rlist}