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| author | bunnei <bunneidev@gmail.com> | 2018-08-30 16:31:26 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-30 16:31:26 +0200 |
| commit | d6accf96ff08450f17c9ec71425037aa2dbddd7f (patch) | |
| tree | e9110ef0cd78b866ced55aac4aeeefa458c66bc9 /src/video_core/renderer_opengl | |
| parent | Merge pull request #1198 from lioncash/kernel (diff) | |
| parent | gl_shader_decompiler: Improve IPA for Pass mode with Position attribute. (diff) | |
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Diffstat (limited to 'src/video_core/renderer_opengl')
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 7e5ebfe24..7b6eb25a4 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp @@ -2100,7 +2100,39 @@ private: } case OpCode::Id::IPA: { const auto& attribute = instr.attribute.fmt28; - regs.SetRegisterToInputAttibute(instr.gpr0, attribute.element, attribute.index); + const auto& reg = instr.gpr0; + switch (instr.ipa.mode) { + case Tegra::Shader::IpaMode::Pass: + if (stage == Maxwell3D::Regs::ShaderStage::Fragment && + attribute.index == Attribute::Index::Position) { + switch (attribute.element) { + case 0: + shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.x;"); + break; + case 1: + shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.y;"); + break; + case 2: + shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.z;"); + break; + case 3: + shader.AddLine(regs.GetRegisterAsFloat(reg) + " = 1.0;"); + break; + } + } else { + regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); + } + break; + case Tegra::Shader::IpaMode::None: + regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); + break; + default: + LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}", + static_cast<u32>(instr.ipa.mode.Value())); + UNREACHABLE(); + regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); + } + break; } case OpCode::Id::SSY: { |